From: Yu Tu <yu.tu@amlogic.com>
To: <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-amlogic@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Neil Armstrong <narmstrong@baylibre.com>,
Jerome Brunet <jbrunet@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: Yu Tu <yu.tu@amlogic.com>
Subject: [PATCH V3 1/6] dt-bindings: clock: meson: add S4 SoC PLL clock controller bindings
Date: Fri, 5 Aug 2022 16:57:11 +0800 [thread overview]
Message-ID: <20220805085716.5635-2-yu.tu@amlogic.com> (raw)
In-Reply-To: <20220805085716.5635-1-yu.tu@amlogic.com>
Add the documentation to support Amlogic S4 SoC PLL clock driver and
add S4 SoC PLL clock controller bindings.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
.../bindings/clock/amlogic,s4-pll-clkc.yaml | 51 +++++++++++++++++++
MAINTAINERS | 1 +
.../dt-bindings/clock/amlogic,s4-pll-clkc.h | 30 +++++++++++
3 files changed, 82 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
create mode 100644 include/dt-bindings/clock/amlogic,s4-pll-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
new file mode 100644
index 000000000000..079ae905b69e
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/amlogic,s4-pll-clkc.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson S serials PLL Clock Controller Device Tree Bindings
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+ - Jerome Brunet <jbrunet@baylibre.com>
+ - Yu Tu <yu.hu@amlogic.com>
+
+
+properties:
+ compatible:
+ const: amlogic,s4-pll-clkc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: xtal
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc_pll: pll-clock-controller@fe008000 {
+ compatible = "amlogic,s4-pll-clkc";
+ reg = <0xfe008000 0x348>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ #clock-cells = <1>;
+ };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 64379c699903..b039cf953520 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1774,6 +1774,7 @@ L: linux-amlogic@lists.infradead.org
S: Maintained
F: Documentation/devicetree/bindings/clock/amlogic*
F: drivers/clk/meson/
+F: include/dt-bindings/clock/amlogic*
F: include/dt-bindings/clock/gxbb*
F: include/dt-bindings/clock/meson*
diff --git a/include/dt-bindings/clock/amlogic,s4-pll-clkc.h b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h
new file mode 100644
index 000000000000..08b7c5c5ba01
--- /dev/null
+++ b/include/dt-bindings/clock/amlogic,s4-pll-clkc.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H
+#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 3
+#define CLKID_FCLK_DIV3 5
+#define CLKID_FCLK_DIV4 7
+#define CLKID_FCLK_DIV5 9
+#define CLKID_FCLK_DIV7 11
+#define CLKID_FCLK_DIV2P5 13
+#define CLKID_GP0_PLL 15
+#define CLKID_HIFI_PLL 17
+#define CLKID_HDMI_PLL 20
+#define CLKID_MPLL_50M 22
+#define CLKID_MPLL0 25
+#define CLKID_MPLL1 27
+#define CLKID_MPLL2 29
+#define CLKID_MPLL3 31
+
+#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_CLKC_H */
--
2.33.1
next prev parent reply other threads:[~2022-08-05 8:59 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 8:57 [PATCH V3 0/6] Add S4 SoC PLL and Peripheral clock controller Yu Tu
2022-08-05 8:57 ` Yu Tu [this message]
2022-08-05 9:13 ` [PATCH V3 1/6] dt-bindings: clock: meson: add S4 SoC PLL clock controller bindings Krzysztof Kozlowski
2022-08-05 8:57 ` [PATCH V3 2/6] arm64: dts: meson: add S4 Soc PLL clock controller in DT Yu Tu
2022-08-05 9:16 ` Krzysztof Kozlowski
2022-08-05 9:39 ` Yu Tu
2022-08-10 13:32 ` Jerome Brunet
2022-08-15 6:17 ` Yu Tu
2022-08-29 9:43 ` Jerome Brunet
2022-08-30 6:05 ` Yu Tu
2022-08-30 6:36 ` Jerome Brunet
2022-08-30 7:06 ` Yu Tu
2022-08-05 8:57 ` [PATCH V3 3/6] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver Yu Tu
2022-08-10 13:47 ` Jerome Brunet
2022-08-15 6:34 ` Yu Tu
2022-08-15 13:20 ` Yu Tu
2022-08-29 9:48 ` Jerome Brunet
2022-08-30 6:13 ` Yu Tu
2022-08-30 6:44 ` Jerome Brunet
2022-08-30 7:37 ` Yu Tu
2022-09-21 8:40 ` Yu Tu
2022-09-28 15:27 ` Jerome Brunet
2022-09-29 7:07 ` Yu Tu
2022-10-22 12:22 ` Jerome Brunet
2022-10-24 11:33 ` Yu Tu
2022-08-29 9:46 ` Jerome Brunet
2022-08-30 6:08 ` Yu Tu
2022-08-05 8:57 ` [PATCH V3 4/6] dt-bindings: clk: meson: add S4 SoC peripheral clock controller bindings Yu Tu
2022-08-05 9:15 ` Krzysztof Kozlowski
2022-08-05 9:33 ` Yu Tu
2022-08-08 6:16 ` Krzysztof Kozlowski
2022-08-08 10:00 ` Yu Tu
2022-08-05 8:57 ` [PATCH V3 5/6] arm64: dts: meson: add S4 Soc Peripheral clock controller in DT Yu Tu
2022-08-05 9:16 ` Krzysztof Kozlowski
2022-08-05 9:36 ` Yu Tu
2022-08-08 6:17 ` Krzysztof Kozlowski
2022-08-08 10:02 ` Yu Tu
2022-08-05 8:57 ` [PATCH V3 6/6] clk: meson: s4: add s4 SoC peripheral clock controller driver Yu Tu
2022-08-10 13:57 ` Jerome Brunet
2022-08-16 12:00 ` Yu Tu
2022-08-29 12:19 ` Jerome Brunet
2022-08-30 8:20 ` Yu Tu
2022-09-21 9:01 ` Yu Tu
2022-09-28 15:35 ` Jerome Brunet
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