* [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont
@ 2016-12-09 0:14 Andi Kleen
2016-12-09 15:49 ` Peter Zijlstra
2016-12-12 6:49 ` [tip:perf/core] " tip-bot for Andi Kleen
0 siblings, 2 replies; 6+ messages in thread
From: Andi Kleen @ 2016-12-09 0:14 UTC (permalink / raw)
To: peterz; +Cc: linux-kernel, Andi Kleen, alexander.shishkin, kan.liang, stable
From: Andi Kleen <ak@linux.intel.com>
An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.
Marking for stable because this allows crashing kernels. Also
should be merged for 4.9.
Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Cc: alexander.shishkin@intel.com
Cc: kan.liang@intel.com
Cc: <stable@vger.kernel.org>
v2: Paint bike shed differently.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/events/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d0efb5cb1b00..baa1eed55e88 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
{
int i;
- if (x86_pmu.lbr_pt_coexist)
+ if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return 0;
if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -387,7 +387,7 @@ fail_unlock:
void x86_del_exclusive(unsigned int what)
{
- if (x86_pmu.lbr_pt_coexist)
+ if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return;
atomic_dec(&x86_pmu.lbr_exclusive[what]);
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont
2016-12-09 0:14 [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Andi Kleen
@ 2016-12-09 15:49 ` Peter Zijlstra
2016-12-12 6:49 ` [tip:perf/core] " tip-bot for Andi Kleen
1 sibling, 0 replies; 6+ messages in thread
From: Peter Zijlstra @ 2016-12-09 15:49 UTC (permalink / raw)
To: Andi Kleen
Cc: linux-kernel, Andi Kleen, alexander.shishkin, kan.liang, stable,
Thomas Gleixner, Ingo Molnar
On Thu, Dec 08, 2016 at 04:14:17PM -0800, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> An earlier patch allowed enabling PT and LBR at the same
> time on Goldmont. However it also allowed enabling BTS and LBR
> at the same time, which is still not supported. Fix this by
> bypassing the check only for PT.
>
> Marking for stable because this allows crashing kernels. Also
> should be merged for 4.9.
>
> Fixes: ccbebba4c6bf ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
> Cc: alexander.shishkin@intel.com
> Cc: kan.liang@intel.com
> Cc: <stable@vger.kernel.org>
> v2: Paint bike shed differently.
Now, if only you'd also clarified the point I asked about. By
documenting these cases we not only get easier to read code, but can
also verify if the code does what is intended.
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> ---
Changed that to the below, which is more explicit on the what is and is
not allowed. And fixed the definition of lbr_pt_coexist.
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what)
{
int i;
- if (x86_pmu.lbr_pt_coexist)
+ /*
+ * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
+ * LBR and BTS are still mutually exclusive.
+ */
+ if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return 0;
if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -388,7 +392,7 @@ int x86_add_exclusive(unsigned int what)
void x86_del_exclusive(unsigned int what)
{
- if (x86_pmu.lbr_pt_coexist)
+ if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return;
atomic_dec(&x86_pmu.lbr_exclusive[what]);
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -604,7 +604,7 @@ struct x86_pmu {
u64 lbr_sel_mask; /* LBR_SELECT valid bits */
const int *lbr_sel_map; /* lbr_select mappings */
bool lbr_double_abort; /* duplicated lbr aborts */
- bool lbr_pt_coexist; /* LBR may coexist with PT */
+ bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
/*
* Intel PT/LBR/BTS are exclusive
^ permalink raw reply [flat|nested] 6+ messages in thread* [tip:perf/core] perf/x86: Fix exclusion of BTS and LBR for Goldmont
2016-12-09 0:14 [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont Andi Kleen
2016-12-09 15:49 ` Peter Zijlstra
@ 2016-12-12 6:49 ` tip-bot for Andi Kleen
1 sibling, 0 replies; 6+ messages in thread
From: tip-bot for Andi Kleen @ 2016-12-12 6:49 UTC (permalink / raw)
To: linux-tip-commits
Cc: linux-kernel, ak, tglx, stable, hpa, peterz, mingo, torvalds
Commit-ID: b0c1ef52959582144bbea9a2b37db7f4c9e399f7
Gitweb: http://git.kernel.org/tip/b0c1ef52959582144bbea9a2b37db7f4c9e399f7
Author: Andi Kleen <ak@linux.intel.com>
AuthorDate: Thu, 8 Dec 2016 16:14:17 -0800
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Sun, 11 Dec 2016 13:06:09 +0100
perf/x86: Fix exclusion of BTS and LBR for Goldmont
An earlier patch allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: alexander.shishkin@intel.com
Cc: kan.liang@intel.com
Cc: <stable@vger.kernel.org>
Fixes: ccbebba4c6bf ("perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Link: http://lkml.kernel.org/r/20161209001417.4713-1-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/events/core.c | 8 ++++++--
arch/x86/events/perf_event.h | 2 +-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 6e395c9..7fe88bb 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -365,7 +365,11 @@ int x86_add_exclusive(unsigned int what)
{
int i;
- if (x86_pmu.lbr_pt_coexist)
+ /*
+ * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS.
+ * LBR and BTS are still mutually exclusive.
+ */
+ if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return 0;
if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -388,7 +392,7 @@ fail_unlock:
void x86_del_exclusive(unsigned int what)
{
- if (x86_pmu.lbr_pt_coexist)
+ if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt)
return;
atomic_dec(&x86_pmu.lbr_exclusive[what]);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index a77ee02..bcbb1d2 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -604,7 +604,7 @@ struct x86_pmu {
u64 lbr_sel_mask; /* LBR_SELECT valid bits */
const int *lbr_sel_map; /* lbr_select mappings */
bool lbr_double_abort; /* duplicated lbr aborts */
- bool lbr_pt_coexist; /* LBR may coexist with PT */
+ bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
/*
* Intel PT/LBR/BTS are exclusive
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont
@ 2016-12-02 23:17 Andi Kleen
2016-12-06 12:38 ` Peter Zijlstra
0 siblings, 1 reply; 6+ messages in thread
From: Andi Kleen @ 2016-12-02 23:17 UTC (permalink / raw)
To: peterz; +Cc: linux-kernel, Andi Kleen, alexander.shishkin, kan.liang, stable
From: Andi Kleen <ak@linux.intel.com>
The earlier patch ccbebba4 allowed enabling PT and LBR at the same
time on Goldmont. However it also allowed enabling BTS and LBR
at the same time, which is still not supported. Fix this by
bypassing the check only for PT.
Marking for stable because this allows crashing kernels. Also
should be merged for 4.9.
Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
Cc: alexander.shishkin@intel.com
Cc: kan.liang@intel.com
Cc: stable@vger.kernel.org # 4.6+
Signed-off-by: Andi Kleen <ak@linux.intel.com>
---
arch/x86/events/core.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index d0efb5cb1b00..baa1eed55e88 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
{
int i;
- if (x86_pmu.lbr_pt_coexist)
+ if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return 0;
if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
@@ -387,7 +387,7 @@ fail_unlock:
void x86_del_exclusive(unsigned int what)
{
- if (x86_pmu.lbr_pt_coexist)
+ if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
return;
atomic_dec(&x86_pmu.lbr_exclusive[what]);
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont
2016-12-02 23:17 [PATCH] " Andi Kleen
@ 2016-12-06 12:38 ` Peter Zijlstra
2016-12-06 14:53 ` Andi Kleen
0 siblings, 1 reply; 6+ messages in thread
From: Peter Zijlstra @ 2016-12-06 12:38 UTC (permalink / raw)
To: Andi Kleen
Cc: linux-kernel, Andi Kleen, alexander.shishkin, kan.liang, stable
For some reason this patch never hit my inbox, it could be because
you're wrecked the Cc line and either infradead or my mta dropped the
email because of that.
On Fri, Dec 02, 2016 at 03:17:32PM -0800, Andi Kleen wrote:
> From: Andi Kleen <ak@linux.intel.com>
>
> The earlier patch ccbebba4 allowed enabling PT and LBR at the same
SHAs should be 12 chars.
> time on Goldmont. However it also allowed enabling BTS and LBR
> at the same time, which is still not supported. Fix this by
> bypassing the check only for PT.
>
> Marking for stable because this allows crashing kernels. Also
> should be merged for 4.9.
>
> Fixes: ccbebba4 ("erf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it")
same
> Cc: alexander.shishkin@intel.com
> Cc: kan.liang@intel.com
> Cc: stable@vger.kernel.org # 4.6+
> Signed-off-by: Andi Kleen <ak@linux.intel.com>
> ---
> arch/x86/events/core.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
> index d0efb5cb1b00..baa1eed55e88 100644
> --- a/arch/x86/events/core.c
> +++ b/arch/x86/events/core.c
> @@ -364,7 +364,7 @@ int x86_add_exclusive(unsigned int what)
> {
> int i;
>
> - if (x86_pmu.lbr_pt_coexist)
> + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
> return 0;
This would also allow PT & BTS at the same time, is that a supported
configuration?
>
> if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) {
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH] perf/x86: Fix exclusion of BTS and LBR for Goldmont
2016-12-06 12:38 ` Peter Zijlstra
@ 2016-12-06 14:53 ` Andi Kleen
0 siblings, 0 replies; 6+ messages in thread
From: Andi Kleen @ 2016-12-06 14:53 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Andi Kleen, linux-kernel, Andi Kleen, alexander.shishkin,
kan.liang, stable
> > - if (x86_pmu.lbr_pt_coexist)
> > + if (what == x86_lbr_exclusive_pt && x86_pmu.lbr_pt_coexist)
> > return 0;
>
> This would also allow PT & BTS at the same time, is that a supported
> configuration?
Yes it is on Goldmont.
-Andi
^ permalink raw reply [flat|nested] 6+ messages in thread
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2016-12-09 15:49 ` Peter Zijlstra
2016-12-12 6:49 ` [tip:perf/core] " tip-bot for Andi Kleen
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