From: Songjun Wu <songjun.wu@linux.intel.com>
To: hua.ma@linux.intel.com, yixin.zhu@linux.intel.com,
chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com
Cc: linux-mips@linux-mips.org, linux-clk@vger.kernel.org,
linux-serial@vger.kernel.org, devicetree@vger.kernel.org,
Songjun Wu <songjun.wu@linux.intel.com>,
James Hogan <jhogan@kernel.org>,
linux-kernel@vger.kernel.org, Paul Burton <paul.burton@mips.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Ralf Baechle <ralf@linux-mips.org>
Subject: [PATCH v2 04/18] MIPS: dts: Add initial support for Intel MIPS SoCs
Date: Fri, 3 Aug 2018 11:02:23 +0800 [thread overview]
Message-ID: <20180803030237.3366-5-songjun.wu@linux.intel.com> (raw)
In-Reply-To: <20180803030237.3366-1-songjun.wu@linux.intel.com>
From: Hua Ma <hua.ma@linux.intel.com>
Add dts files to support Intel MIPS SoCs:
- xrx500.dtsi is the chip dts
- easy350_anywan.dts is the board dts
Signed-off-by: Hua Ma <hua.ma@linux.intel.com>
Signed-off-by: Songjun Wu <songjun.wu@linux.intel.com>
---
Changes in v2:
- New patch split from previous patch
- The memory address is changed to @20000000
- Update to obj-$(CONFIG_BUILTIN_DTB) as per commit fca3aa166422
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/intel-mips/Makefile | 4 ++
arch/mips/boot/dts/intel-mips/easy350_anywan.dts | 26 ++++++++++
arch/mips/boot/dts/intel-mips/xrx500.dtsi | 66 ++++++++++++++++++++++++
4 files changed, 97 insertions(+)
create mode 100644 arch/mips/boot/dts/intel-mips/Makefile
create mode 100644 arch/mips/boot/dts/intel-mips/easy350_anywan.dts
create mode 100644 arch/mips/boot/dts/intel-mips/xrx500.dtsi
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index 1e79cab8e269..05f52f279047 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -3,6 +3,7 @@ subdir-y += brcm
subdir-y += cavium-octeon
subdir-y += img
subdir-y += ingenic
+subdir-y += intel-mips
subdir-y += lantiq
subdir-y += mscc
subdir-y += mti
diff --git a/arch/mips/boot/dts/intel-mips/Makefile b/arch/mips/boot/dts/intel-mips/Makefile
new file mode 100644
index 000000000000..adfaabbbb07c
--- /dev/null
+++ b/arch/mips/boot/dts/intel-mips/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DTB_INTEL_MIPS_GRX500) += easy350_anywan.dtb
+
+obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
diff --git a/arch/mips/boot/dts/intel-mips/easy350_anywan.dts b/arch/mips/boot/dts/intel-mips/easy350_anywan.dts
new file mode 100644
index 000000000000..e5e95f90c5e7
--- /dev/null
+++ b/arch/mips/boot/dts/intel-mips/easy350_anywan.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+#include <dt-bindings/clock/intel,grx500-clk.h>
+
+#include "xrx500.dtsi"
+
+/ {
+ model = "EASY350 ANYWAN (GRX350) Main model";
+ compatible = "intel,easy350-anywan";
+
+ aliases {
+ serial0 = &asc0;
+ };
+
+ chosen {
+ bootargs = "earlycon=lantiq,0x16600000 clk_ignore_unused";
+ stdout-path = "serial0";
+ };
+
+ memory@20000000 {
+ device_type = "memory";
+ reg = <0x20000000 0x0e000000>;
+ };
+};
diff --git a/arch/mips/boot/dts/intel-mips/xrx500.dtsi b/arch/mips/boot/dts/intel-mips/xrx500.dtsi
new file mode 100644
index 000000000000..54c5f8f8b604
--- /dev/null
+++ b/arch/mips/boot/dts/intel-mips/xrx500.dtsi
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "intel,xrx500";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "mti,interaptiv";
+ clocks = <&cgu CLK_CPU>;
+ reg = <0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "mti,interaptiv";
+ reg = <1>;
+ };
+ };
+
+ cpu_intc: interrupt-controller {
+ compatible = "mti,cpu-interrupt-controller";
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ gic: gic@12320000 {
+ compatible = "mti,gic";
+ reg = <0x12320000 0x20000>;
+
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ /*
+ * Declare the interrupt-parent even though the mti,gic
+ * binding doesn't require it, such that the kernel can
+ * figure out that cpu_intc is the root interrupt
+ * controller & should be probed first.
+ */
+ interrupt-parent = <&cpu_intc>;
+ mti,reserved-ipi-vectors = <56 8>;
+ };
+
+ cgu: cgu@16200000 {
+ compatible = "intel,grx500-cgu", "syscon";
+ reg = <0x16200000 0x200>;
+ #clock-cells = <1>;
+ };
+
+ asc0: serial@16600000 {
+ compatible = "lantiq,asc";
+ reg = <0x16600000 0x100000>;
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SHARED 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
+ clock-names = "freq", "asc";
+ };
+};
--
2.11.0
next prev parent reply other threads:[~2018-08-03 3:03 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-03 3:02 [PATCH v2 00/18] MIPS: intel: add initial support for Intel MIPS SoCs Songjun Wu
2018-08-03 3:02 ` [PATCH v2 01/18] MIPS: intel: Add " Songjun Wu
2018-08-03 17:49 ` Paul Burton
2018-08-06 9:12 ` Hua Ma
2018-08-03 3:02 ` [PATCH v2 02/18] clk: intel: Add clock driver " Songjun Wu
2018-08-06 15:19 ` Rob Herring
2018-08-08 2:51 ` yixin zhu
2018-08-08 5:50 ` Stephen Boyd
2018-08-08 8:52 ` yixin zhu
2018-08-27 19:09 ` Stephen Boyd
2018-08-29 6:56 ` Zhu, Yi Xin
2018-08-31 17:10 ` Stephen Boyd
2018-09-03 10:47 ` Zhu, Yi Xin
2018-08-29 10:34 ` Zhu, Yi Xin
2018-08-31 17:13 ` Stephen Boyd
2018-09-03 10:52 ` Zhu, Yi Xin
2018-08-03 3:02 ` [PATCH v2 03/18] dt-bindings: clk: Add documentation of grx500 clock controller Songjun Wu
2018-08-06 15:18 ` Rob Herring
2018-08-08 3:08 ` yixin zhu
2018-08-08 14:54 ` Rob Herring
2018-08-03 3:02 ` Songjun Wu [this message]
2018-08-04 11:11 ` [PATCH v2 04/18] MIPS: dts: Add initial support for Intel MIPS SoCs Hauke Mehrtens
2018-08-06 9:20 ` Hua Ma
2018-08-03 3:02 ` [PATCH v2 05/18] dt-binding: MIPS: Add documentation of " Songjun Wu
2018-08-06 15:16 ` Rob Herring
2018-08-03 3:02 ` [PATCH v2 06/18] MIPS: dts: Change upper case to lower case Songjun Wu
2018-08-06 15:14 ` Rob Herring
2018-08-03 3:02 ` [PATCH v2 07/18] MIPS: dts: Add aliases node for lantiq danube serial Songjun Wu
2018-08-03 3:02 ` [PATCH v2 08/18] serial: intel: Get serial id from dts Songjun Wu
2018-08-03 5:43 ` Greg Kroah-Hartman
2018-08-06 9:32 ` Wu, Songjun
2018-08-07 7:33 ` Geert Uytterhoeven
2018-08-08 4:05 ` Wu, Songjun
2018-08-08 8:33 ` Geert Uytterhoeven
2018-08-10 8:13 ` Wu, Songjun
2018-08-03 3:02 ` [PATCH v2 09/18] serial: intel: Change ltq_w32_mask to asc_update_bits Songjun Wu
2018-08-03 3:02 ` [PATCH v2 10/18] MIPS: lantiq: Unselect SWAP_IO_SPACE when LANTIQ is selected Songjun Wu
2018-08-03 3:02 ` [PATCH v2 11/18] serial: intel: Use readl/writel instead of ltq_r32/ltq_w32 Songjun Wu
2018-08-03 3:02 ` [PATCH v2 12/18] serial: intel: Rename fpiclk to freqclk Songjun Wu
2018-08-03 3:02 ` [PATCH v2 13/18] serial: intel: Replace clk_enable/clk_disable with clk generic API Songjun Wu
2018-08-03 3:02 ` [PATCH v2 14/18] serial: intel: Add CCF support Songjun Wu
2018-08-03 5:56 ` Greg Kroah-Hartman
2018-08-03 7:33 ` Wu, Songjun
2018-08-03 10:30 ` Greg Kroah-Hartman
2018-08-04 10:54 ` Hauke Mehrtens
2018-08-04 12:43 ` Greg Kroah-Hartman
2018-08-04 21:03 ` Arnd Bergmann
2018-08-06 7:05 ` Wu, Songjun
2018-08-06 7:20 ` Geert Uytterhoeven
2018-08-06 8:58 ` Wu, Songjun
2018-08-06 9:29 ` Geert Uytterhoeven
2018-08-07 7:18 ` Wu, Songjun
2018-08-07 7:33 ` Geert Uytterhoeven
2018-08-03 3:02 ` [PATCH v2 15/18] serial: intel: Support more platform Songjun Wu
2018-08-03 5:57 ` Greg Kroah-Hartman
2018-08-03 7:21 ` Wu, Songjun
2018-08-05 8:37 ` Christoph Hellwig
2018-08-06 7:20 ` Wu, Songjun
2018-08-03 3:02 ` [PATCH v2 16/18] serial: intel: Reorder the head files Songjun Wu
2018-08-03 3:02 ` [PATCH v2 17/18] serial: intel: Change init_lqasc to static declaration Songjun Wu
2018-08-03 3:02 ` [PATCH v2 18/18] dt-bindings: serial: lantiq: Add optional properties for CCF Songjun Wu
2018-08-13 17:53 ` Rob Herring
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