From: Rob Herring <robh+dt@kernel.org>
To: Songjun Wu <songjun.wu@linux.intel.com>
Cc: hua.ma@linux.intel.com, yixin zhu <yixin.zhu@linux.intel.com>,
chuanhua.lei@linux.intel.com, qi-ming.wu@intel.com,
Linux-MIPS <linux-mips@linux-mips.org>,
linux-clk <linux-clk@vger.kernel.org>,
"open list:SERIAL DRIVERS" <linux-serial@vger.kernel.org>,
devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Mark Rutland <mark.rutland@arm.com>
Subject: Re: [PATCH v2 02/18] clk: intel: Add clock driver for Intel MIPS SoCs
Date: Mon, 6 Aug 2018 09:19:59 -0600 [thread overview]
Message-ID: <CAL_JsqK5pFNKyAhTTmNpaSnKa_beY3kS8FGtYim8oTgw6oO9Rw@mail.gmail.com> (raw)
In-Reply-To: <20180803030237.3366-3-songjun.wu@linux.intel.com>
On Thu, Aug 2, 2018 at 9:03 PM Songjun Wu <songjun.wu@linux.intel.com> wrote:
>
> From: Yixin Zhu <yixin.zhu@linux.intel.com>
>
> This driver provides PLL clock registration as well as various clock
> branches, e.g. MUX clock, gate clock, divider clock and so on.
>
> PLLs that provide clock to DDR, CPU and peripherals are shown below:
>
> +---------+
> |--->| LCPLL3 0|--PCIe clk-->
> XO | +---------+
> +-----------|
> | +---------+
> | | 3|--PAE clk-->
> |--->| PLL0B 2|--GSWIP clk-->
> | | 1|--DDR clk-->DDR PHY clk-->
> | | 0|--CPU1 clk--+ +-----+
> | +---------+ |--->0 |
> | | MUX |--CPU clk-->
> | +---------+ |--->1 |
> | | 0|--CPU0 clk--+ +-----+
> |--->| PLLOA 1|--SSX4 clk-->
> | 2|--NGI clk-->
> | 3|--CBM clk-->
> +---------+
>
> Signed-off-by: Yixin Zhu <yixin.zhu@linux.intel.com>
> Signed-off-by: Songjun Wu <songjun.wu@linux.intel.com>
> ---
>
> Changes in v2:
> - Rewrite clock driver, add platform clock description details in
> clock driver.
>
> drivers/clk/Kconfig | 1 +
> drivers/clk/Makefile | 3 +
> drivers/clk/intel/Kconfig | 20 ++
> drivers/clk/intel/Makefile | 7 +
> drivers/clk/intel/clk-cgu-pll.c | 166 ++++++++++
> drivers/clk/intel/clk-cgu-pll.h | 34 ++
> drivers/clk/intel/clk-cgu.c | 470 +++++++++++++++++++++++++++
> drivers/clk/intel/clk-cgu.h | 259 +++++++++++++++
> drivers/clk/intel/clk-grx500.c | 168 ++++++++++
> include/dt-bindings/clock/intel,grx500-clk.h | 69 ++++
This belongs with the clk binding patch.
Rob
next prev parent reply other threads:[~2018-08-06 15:20 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-03 3:02 [PATCH v2 00/18] MIPS: intel: add initial support for Intel MIPS SoCs Songjun Wu
2018-08-03 3:02 ` [PATCH v2 01/18] MIPS: intel: Add " Songjun Wu
2018-08-03 17:49 ` Paul Burton
2018-08-06 9:12 ` Hua Ma
2018-08-03 3:02 ` [PATCH v2 02/18] clk: intel: Add clock driver " Songjun Wu
2018-08-06 15:19 ` Rob Herring [this message]
2018-08-08 2:51 ` yixin zhu
2018-08-08 5:50 ` Stephen Boyd
2018-08-08 8:52 ` yixin zhu
2018-08-27 19:09 ` Stephen Boyd
2018-08-29 6:56 ` Zhu, Yi Xin
2018-08-31 17:10 ` Stephen Boyd
2018-09-03 10:47 ` Zhu, Yi Xin
2018-08-29 10:34 ` Zhu, Yi Xin
2018-08-31 17:13 ` Stephen Boyd
2018-09-03 10:52 ` Zhu, Yi Xin
2018-08-03 3:02 ` [PATCH v2 03/18] dt-bindings: clk: Add documentation of grx500 clock controller Songjun Wu
2018-08-06 15:18 ` Rob Herring
2018-08-08 3:08 ` yixin zhu
2018-08-08 14:54 ` Rob Herring
2018-08-03 3:02 ` [PATCH v2 04/18] MIPS: dts: Add initial support for Intel MIPS SoCs Songjun Wu
2018-08-04 11:11 ` Hauke Mehrtens
2018-08-06 9:20 ` Hua Ma
2018-08-03 3:02 ` [PATCH v2 05/18] dt-binding: MIPS: Add documentation of " Songjun Wu
2018-08-06 15:16 ` Rob Herring
2018-08-03 3:02 ` [PATCH v2 06/18] MIPS: dts: Change upper case to lower case Songjun Wu
2018-08-06 15:14 ` Rob Herring
2018-08-03 3:02 ` [PATCH v2 07/18] MIPS: dts: Add aliases node for lantiq danube serial Songjun Wu
2018-08-03 3:02 ` [PATCH v2 08/18] serial: intel: Get serial id from dts Songjun Wu
2018-08-03 5:43 ` Greg Kroah-Hartman
2018-08-06 9:32 ` Wu, Songjun
2018-08-07 7:33 ` Geert Uytterhoeven
2018-08-08 4:05 ` Wu, Songjun
2018-08-08 8:33 ` Geert Uytterhoeven
2018-08-10 8:13 ` Wu, Songjun
2018-08-03 3:02 ` [PATCH v2 09/18] serial: intel: Change ltq_w32_mask to asc_update_bits Songjun Wu
2018-08-03 3:02 ` [PATCH v2 10/18] MIPS: lantiq: Unselect SWAP_IO_SPACE when LANTIQ is selected Songjun Wu
2018-08-03 3:02 ` [PATCH v2 11/18] serial: intel: Use readl/writel instead of ltq_r32/ltq_w32 Songjun Wu
2018-08-03 3:02 ` [PATCH v2 12/18] serial: intel: Rename fpiclk to freqclk Songjun Wu
2018-08-03 3:02 ` [PATCH v2 13/18] serial: intel: Replace clk_enable/clk_disable with clk generic API Songjun Wu
2018-08-03 3:02 ` [PATCH v2 14/18] serial: intel: Add CCF support Songjun Wu
2018-08-03 5:56 ` Greg Kroah-Hartman
2018-08-03 7:33 ` Wu, Songjun
2018-08-03 10:30 ` Greg Kroah-Hartman
2018-08-04 10:54 ` Hauke Mehrtens
2018-08-04 12:43 ` Greg Kroah-Hartman
2018-08-04 21:03 ` Arnd Bergmann
2018-08-06 7:05 ` Wu, Songjun
2018-08-06 7:20 ` Geert Uytterhoeven
2018-08-06 8:58 ` Wu, Songjun
2018-08-06 9:29 ` Geert Uytterhoeven
2018-08-07 7:18 ` Wu, Songjun
2018-08-07 7:33 ` Geert Uytterhoeven
2018-08-03 3:02 ` [PATCH v2 15/18] serial: intel: Support more platform Songjun Wu
2018-08-03 5:57 ` Greg Kroah-Hartman
2018-08-03 7:21 ` Wu, Songjun
2018-08-05 8:37 ` Christoph Hellwig
2018-08-06 7:20 ` Wu, Songjun
2018-08-03 3:02 ` [PATCH v2 16/18] serial: intel: Reorder the head files Songjun Wu
2018-08-03 3:02 ` [PATCH v2 17/18] serial: intel: Change init_lqasc to static declaration Songjun Wu
2018-08-03 3:02 ` [PATCH v2 18/18] dt-bindings: serial: lantiq: Add optional properties for CCF Songjun Wu
2018-08-13 17:53 ` Rob Herring
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAL_JsqK5pFNKyAhTTmNpaSnKa_beY3kS8FGtYim8oTgw6oO9Rw@mail.gmail.com \
--to=robh+dt@kernel.org \
--cc=chuanhua.lei@linux.intel.com \
--cc=devicetree@vger.kernel.org \
--cc=hua.ma@linux.intel.com \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mips@linux-mips.org \
--cc=linux-serial@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mturquette@baylibre.com \
--cc=qi-ming.wu@intel.com \
--cc=sboyd@kernel.org \
--cc=songjun.wu@linux.intel.com \
--cc=yixin.zhu@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).