* [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-30 22:25 ` Rob Herring
2020-11-23 2:34 ` [PATCH v5 02/16] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
` (14 subsequent siblings)
15 siblings, 1 reply; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
YAML schemas Device Tree (DT) binding is the new format for DT to replace
the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
remove the old version.
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../bindings/dma/snps,dw-axi-dmac.txt | 39 ------
.../bindings/dma/snps,dw-axi-dmac.yaml | 126 ++++++++++++++++++
2 files changed, 126 insertions(+), 39 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
deleted file mode 100644
index dbe160400adc..000000000000
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Synopsys DesignWare AXI DMA Controller
-
-Required properties:
-- compatible: "snps,axi-dma-1.01a"
-- reg: Address range of the DMAC registers. This should include
- all of the per-channel registers.
-- interrupt: Should contain the DMAC interrupt number.
-- dma-channels: Number of channels supported by hardware.
-- snps,dma-masters: Number of AXI masters supported by the hardware.
-- snps,data-width: Maximum AXI data width supported by hardware.
- (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
-- snps,priority: Priority of channel. Array size is equal to the number of
- dma-channels. Priority value must be programmed within [0:dma-channels-1]
- range. (0 - minimum priority)
-- snps,block-size: Maximum block size supported by the controller channel.
- Array size is equal to the number of dma-channels.
-
-Optional properties:
-- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
- in this property. If this property is missing the maximum AXI burst length
- supported by DMAC is used. [1:256]
-
-Example:
-
-dmac: dma-controller@80000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x80000 0x400>;
- clocks = <&core_clk>, <&cfgr_clk>;
- clock-names = "core-clk", "cfgr-clk";
- interrupt-parent = <&intc>;
- interrupts = <27>;
-
- dma-channels = <4>;
- snps,dma-masters = <2>;
- snps,data-width = <3>;
- snps,block-size = <4096 4096 4096 4096>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <16>;
-};
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
new file mode 100644
index 000000000000..6c2e8e612af5
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DesignWare AXI DMA Controller
+
+maintainers:
+ - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
+
+description: |
+ Synopsys DesignWare AXI DMA Controller DT Binding
+
+properties:
+ compatible:
+ enum:
+ - snps,axi-dma-1.01a
+
+ reg:
+ items:
+ - description: Address range of the DMAC registers
+
+ reg-names:
+ items:
+ - const: axidma_ctrl_regs
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Bus Clock
+ - description: Module Clock
+
+ clock-names:
+ items:
+ - const: core-clk
+ - const: cfgr-clk
+
+ '#dma-cells':
+ const: 1
+
+ dma-channels:
+ description: |
+ Number of channels supported by hardware.
+
+ snps,dma-masters:
+ description: |
+ Number of AXI masters supported by the hardware.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [1, 2]
+ default: 2
+
+ snps,data-width:
+ description: |
+ AXI data width supported by hardware.
+ (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [0, 1, 2, 3, 4, 5, 6]
+ default: 4
+
+ snps,priority:
+ description: |
+ Channel priority specifier associated with the DMA channels.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 1
+ maxItems: 8
+ default: [0, 1, 2, 3]
+
+ snps,block-size:
+ description: |
+ Channel block size specifier associated with the DMA channels.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32-array
+ - minItems: 1
+ maxItems: 8
+ default: [4096, 4096, 4096, 4096]
+
+ snps,axi-max-burst-len:
+ description: |
+ Restrict master AXI burst length by value specified in this property.
+ If this property is missing the maximum AXI burst length supported by
+ DMAC is used. [1:256]
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ default: 16
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - '#dma-cells'
+ - dma-channels
+ - snps,dma-masters
+ - snps,data-width
+ - snps,priority
+ - snps,block-size
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ /* example with snps,dw-axi-dmac */
+ dmac: dma-controller@80000 {
+ compatible = "snps,axi-dma-1.01a";
+ reg = <0x80000 0x400>;
+ clocks = <&core_clk>, <&cfgr_clk>;
+ clock-names = "core-clk", "cfgr-clk";
+ interrupt-parent = <&intc>;
+ interrupts = <27>;
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ snps,dma-masters = <2>;
+ snps,data-width = <3>;
+ snps,block-size = <4096 4096 4096 4096>;
+ snps,priority = <0 1 2 3>;
+ snps,axi-max-burst-len = <16>;
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
2020-11-23 2:34 ` [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
@ 2020-11-30 22:25 ` Rob Herring
2020-12-09 3:21 ` Sia, Jee Heng
0 siblings, 1 reply; 24+ messages in thread
From: Rob Herring @ 2020-11-30 22:25 UTC (permalink / raw)
To: Sia Jee Heng
Cc: vkoul, Eugeniy.Paltsev, andriy.shevchenko, dmaengine,
linux-kernel, devicetree
On Mon, Nov 23, 2020 at 10:34:37AM +0800, Sia Jee Heng wrote:
> YAML schemas Device Tree (DT) binding is the new format for DT to replace
> the old format. Introduce YAML schemas DT binding for dw-axi-dmac and
> remove the old version.
>
> Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> ---
> .../bindings/dma/snps,dw-axi-dmac.txt | 39 ------
> .../bindings/dma/snps,dw-axi-dmac.yaml | 126 ++++++++++++++++++
> 2 files changed, 126 insertions(+), 39 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
>
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> deleted file mode 100644
> index dbe160400adc..000000000000
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> +++ /dev/null
> @@ -1,39 +0,0 @@
> -Synopsys DesignWare AXI DMA Controller
> -
> -Required properties:
> -- compatible: "snps,axi-dma-1.01a"
> -- reg: Address range of the DMAC registers. This should include
> - all of the per-channel registers.
> -- interrupt: Should contain the DMAC interrupt number.
> -- dma-channels: Number of channels supported by hardware.
> -- snps,dma-masters: Number of AXI masters supported by the hardware.
> -- snps,data-width: Maximum AXI data width supported by hardware.
> - (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> -- snps,priority: Priority of channel. Array size is equal to the number of
> - dma-channels. Priority value must be programmed within [0:dma-channels-1]
> - range. (0 - minimum priority)
> -- snps,block-size: Maximum block size supported by the controller channel.
> - Array size is equal to the number of dma-channels.
> -
> -Optional properties:
> -- snps,axi-max-burst-len: Restrict master AXI burst length by value specified
> - in this property. If this property is missing the maximum AXI burst length
> - supported by DMAC is used. [1:256]
> -
> -Example:
> -
> -dmac: dma-controller@80000 {
> - compatible = "snps,axi-dma-1.01a";
> - reg = <0x80000 0x400>;
> - clocks = <&core_clk>, <&cfgr_clk>;
> - clock-names = "core-clk", "cfgr-clk";
> - interrupt-parent = <&intc>;
> - interrupts = <27>;
> -
> - dma-channels = <4>;
> - snps,dma-masters = <2>;
> - snps,data-width = <3>;
> - snps,block-size = <4096 4096 4096 4096>;
> - snps,priority = <0 1 2 3>;
> - snps,axi-max-burst-len = <16>;
> -};
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> new file mode 100644
> index 000000000000..6c2e8e612af5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -0,0 +1,126 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Synopsys DesignWare AXI DMA Controller
> +
> +maintainers:
> + - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
> +
> +description: |
Don't need '|' unless there's formatting to preserve.
> + Synopsys DesignWare AXI DMA Controller DT Binding
And should be 2 space indent.
> +
> +properties:
> + compatible:
> + enum:
> + - snps,axi-dma-1.01a
> +
> + reg:
> + items:
> + - description: Address range of the DMAC registers
Just 'maxItems: 1'
> +
> + reg-names:
> + items:
> + - const: axidma_ctrl_regs
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Bus Clock
> + - description: Module Clock
> +
> + clock-names:
> + items:
> + - const: core-clk
> + - const: cfgr-clk
> +
> + '#dma-cells':
> + const: 1
> +
> + dma-channels:
> + description: |
> + Number of channels supported by hardware.
No need to describe a common property. You do need to provide some
constraints. I'd assume there's less than 2^32 channels.
> +
> + snps,dma-masters:
> + description: |
> + Number of AXI masters supported by the hardware.
> + allOf:
You don't need to use allOf with a $ref anymore.
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [1, 2]
> + default: 2
> +
> + snps,data-width:
> + description: |
> + AXI data width supported by hardware.
> + (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [0, 1, 2, 3, 4, 5, 6]
> + default: 4
> +
> + snps,priority:
> + description: |
> + Channel priority specifier associated with the DMA channels.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32-array
> + - minItems: 1
> + maxItems: 8
> + default: [0, 1, 2, 3]
> +
> + snps,block-size:
> + description: |
> + Channel block size specifier associated with the DMA channels.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32-array
> + - minItems: 1
> + maxItems: 8
> + default: [4096, 4096, 4096, 4096]
> +
> + snps,axi-max-burst-len:
> + description: |
> + Restrict master AXI burst length by value specified in this property.
> + If this property is missing the maximum AXI burst length supported by
> + DMAC is used. [1:256]
Looks like some constraints.
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + default: 16
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - '#dma-cells'
> + - dma-channels
> + - snps,dma-masters
> + - snps,data-width
> + - snps,priority
> + - snps,block-size
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + /* example with snps,dw-axi-dmac */
> + dmac: dma-controller@80000 {
> + compatible = "snps,axi-dma-1.01a";
> + reg = <0x80000 0x400>;
> + clocks = <&core_clk>, <&cfgr_clk>;
> + clock-names = "core-clk", "cfgr-clk";
> + interrupt-parent = <&intc>;
> + interrupts = <27>;
> + #dma-cells = <1>;
> + dma-channels = <4>;
> + snps,dma-masters = <2>;
> + snps,data-width = <3>;
> + snps,block-size = <4096 4096 4096 4096>;
> + snps,priority = <0 1 2 3>;
> + snps,axi-max-burst-len = <16>;
> + };
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 24+ messages in thread* RE: [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
2020-11-30 22:25 ` Rob Herring
@ 2020-12-09 3:21 ` Sia, Jee Heng
2020-12-10 1:22 ` Sia, Jee Heng
0 siblings, 1 reply; 24+ messages in thread
From: Sia, Jee Heng @ 2020-12-09 3:21 UTC (permalink / raw)
To: Rob Herring
Cc: vkoul, Eugeniy.Paltsev, andriy.shevchenko, dmaengine,
linux-kernel, devicetree
Hi Rob,
Regarding the comment " You don't need to use allOf with a $ref anymore."
I get dt compile error after remove the allOf and $ref. Error message shown below:
'$ref' is a required property
'allOf' is a required property
snps,dma-masters:
description: |
Number of AXI masters supported by the hardware.
enum: [1, 2]
default: 2
Thanks
Regards
Jee Heng
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 01 December 2020 6:26 AM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: vkoul@kernel.org; Eugeniy.Paltsev@synopsys.com;
> andriy.shevchenko@linux.intel.com; dmaengine@vger.kernel.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas
> for dw-axi-dmac
>
> On Mon, Nov 23, 2020 at 10:34:37AM +0800, Sia Jee Heng wrote:
> > YAML schemas Device Tree (DT) binding is the new format for DT to
> > replace the old format. Introduce YAML schemas DT binding for
> > dw-axi-dmac and remove the old version.
> >
> > Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> > ---
> > .../bindings/dma/snps,dw-axi-dmac.txt | 39 ------
> > .../bindings/dma/snps,dw-axi-dmac.yaml | 126
> ++++++++++++++++++
> > 2 files changed, 126 insertions(+), 39 deletions(-) delete mode
> > 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.txt
> > create mode 100644
> > Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> > b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> > deleted file mode 100644
> > index dbe160400adc..000000000000
> > --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.txt
> > +++ /dev/null
> > @@ -1,39 +0,0 @@
> > -Synopsys DesignWare AXI DMA Controller
> > -
> > -Required properties:
> > -- compatible: "snps,axi-dma-1.01a"
> > -- reg: Address range of the DMAC registers. This should include
> > - all of the per-channel registers.
> > -- interrupt: Should contain the DMAC interrupt number.
> > -- dma-channels: Number of channels supported by hardware.
> > -- snps,dma-masters: Number of AXI masters supported by the
> hardware.
> > -- snps,data-width: Maximum AXI data width supported by hardware.
> > - (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> > -- snps,priority: Priority of channel. Array size is equal to the
> > number of
> > - dma-channels. Priority value must be programmed within
> > [0:dma-channels-1]
> > - range. (0 - minimum priority)
> > -- snps,block-size: Maximum block size supported by the controller
> channel.
> > - Array size is equal to the number of dma-channels.
> > -
> > -Optional properties:
> > -- snps,axi-max-burst-len: Restrict master AXI burst length by value
> > specified
> > - in this property. If this property is missing the maximum AXI burst
> > length
> > - supported by DMAC is used. [1:256]
> > -
> > -Example:
> > -
> > -dmac: dma-controller@80000 {
> > - compatible = "snps,axi-dma-1.01a";
> > - reg = <0x80000 0x400>;
> > - clocks = <&core_clk>, <&cfgr_clk>;
> > - clock-names = "core-clk", "cfgr-clk";
> > - interrupt-parent = <&intc>;
> > - interrupts = <27>;
> > -
> > - dma-channels = <4>;
> > - snps,dma-masters = <2>;
> > - snps,data-width = <3>;
> > - snps,block-size = <4096 4096 4096 4096>;
> > - snps,priority = <0 1 2 3>;
> > - snps,axi-max-burst-len = <16>;
> > -};
> > diff --git
> > a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > new file mode 100644
> > index 000000000000..6c2e8e612af5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.yaml
> > @@ -0,0 +1,126 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML
> 1.2
> > +---
> > +$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Synopsys DesignWare AXI DMA Controller
> > +
> > +maintainers:
> > + - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
> > +
> > +description: |
>
> Don't need '|' unless there's formatting to preserve.
>
> > + Synopsys DesignWare AXI DMA Controller DT Binding
>
> And should be 2 space indent.
>
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - snps,axi-dma-1.01a
> > +
> > + reg:
> > + items:
> > + - description: Address range of the DMAC registers
>
> Just 'maxItems: 1'
>
> > +
> > + reg-names:
> > + items:
> > + - const: axidma_ctrl_regs
> > +
> > + interrupts:
> > + maxItems: 1
> > +
> > + clocks:
> > + items:
> > + - description: Bus Clock
> > + - description: Module Clock
> > +
> > + clock-names:
> > + items:
> > + - const: core-clk
> > + - const: cfgr-clk
> > +
> > + '#dma-cells':
> > + const: 1
> > +
> > + dma-channels:
> > + description: |
> > + Number of channels supported by hardware.
>
> No need to describe a common property. You do need to provide
> some constraints. I'd assume there's less than 2^32 channels.
>
> > +
> > + snps,dma-masters:
> > + description: |
> > + Number of AXI masters supported by the hardware.
> > + allOf:
>
> You don't need to use allOf with a $ref anymore.
>
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [1, 2]
> > + default: 2
> > +
> > + snps,data-width:
> > + description: |
> > + AXI data width supported by hardware.
> > + (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [0, 1, 2, 3, 4, 5, 6]
> > + default: 4
> > +
> > + snps,priority:
> > + description: |
> > + Channel priority specifier associated with the DMA channels.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32-array
> > + - minItems: 1
> > + maxItems: 8
> > + default: [0, 1, 2, 3]
> > +
> > + snps,block-size:
> > + description: |
> > + Channel block size specifier associated with the DMA channels.
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32-array
> > + - minItems: 1
> > + maxItems: 8
> > + default: [4096, 4096, 4096, 4096]
> > +
> > + snps,axi-max-burst-len:
> > + description: |
> > + Restrict master AXI burst length by value specified in this
> property.
> > + If this property is missing the maximum AXI burst length
> supported by
> > + DMAC is used. [1:256]
>
> Looks like some constraints.
>
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 16
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - interrupts
> > + - '#dma-cells'
> > + - dma-channels
> > + - snps,dma-masters
> > + - snps,data-width
> > + - snps,priority
> > + - snps,block-size
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + /* example with snps,dw-axi-dmac */
> > + dmac: dma-controller@80000 {
> > + compatible = "snps,axi-dma-1.01a";
> > + reg = <0x80000 0x400>;
> > + clocks = <&core_clk>, <&cfgr_clk>;
> > + clock-names = "core-clk", "cfgr-clk";
> > + interrupt-parent = <&intc>;
> > + interrupts = <27>;
> > + #dma-cells = <1>;
> > + dma-channels = <4>;
> > + snps,dma-masters = <2>;
> > + snps,data-width = <3>;
> > + snps,block-size = <4096 4096 4096 4096>;
> > + snps,priority = <0 1 2 3>;
> > + snps,axi-max-burst-len = <16>;
> > + };
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 24+ messages in thread* RE: [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac
2020-12-09 3:21 ` Sia, Jee Heng
@ 2020-12-10 1:22 ` Sia, Jee Heng
0 siblings, 0 replies; 24+ messages in thread
From: Sia, Jee Heng @ 2020-12-10 1:22 UTC (permalink / raw)
To: Rob Herring
Cc: vkoul, Eugeniy.Paltsev, andriy.shevchenko, dmaengine,
linux-kernel, devicetree
Hi Rob,
I think I still need the 'ref', but can remove the 'allOf'.
Thanks
Regards
Jee Heng
> -----Original Message-----
> From: Sia, Jee Heng
> Sent: 09 December 2020 11:21 AM
> To: Rob Herring <robh@kernel.org>
> Cc: vkoul@kernel.org; Eugeniy.Paltsev@synopsys.com;
> andriy.shevchenko@linux.intel.com; dmaengine@vger.kernel.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: RE: [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas
> for dw-axi-dmac
>
> Hi Rob,
>
> Regarding the comment " You don't need to use allOf with a $ref
> anymore."
> I get dt compile error after remove the allOf and $ref. Error message
> shown below:
> '$ref' is a required property
> 'allOf' is a required property
>
> snps,dma-masters:
> description: |
> Number of AXI masters supported by the hardware.
> enum: [1, 2]
> default: 2
>
> Thanks
> Regards
> Jee Heng
>
> > -----Original Message-----
> > From: Rob Herring <robh@kernel.org>
> > Sent: 01 December 2020 6:26 AM
> > To: Sia, Jee Heng <jee.heng.sia@intel.com>
> > Cc: vkoul@kernel.org; Eugeniy.Paltsev@synopsys.com;
> > andriy.shevchenko@linux.intel.com; dmaengine@vger.kernel.org;
> > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> > Subject: Re: [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas
> for
> > dw-axi-dmac
> >
> > On Mon, Nov 23, 2020 at 10:34:37AM +0800, Sia Jee Heng wrote:
> > > YAML schemas Device Tree (DT) binding is the new format for DT
> to
> > > replace the old format. Introduce YAML schemas DT binding for
> > > dw-axi-dmac and remove the old version.
> > >
> > > Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> > > ---
> > > .../bindings/dma/snps,dw-axi-dmac.txt | 39 ------
> > > .../bindings/dma/snps,dw-axi-dmac.yaml | 126
> > ++++++++++++++++++
> > > 2 files changed, 126 insertions(+), 39 deletions(-) delete mode
> > > 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-
> > dmac.txt
> > > create mode 100644
> > > Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> > > b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> > > deleted file mode 100644
> > > index dbe160400adc..000000000000
> > > --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-
> > dmac.txt
> > > +++ /dev/null
> > > @@ -1,39 +0,0 @@
> > > -Synopsys DesignWare AXI DMA Controller
> > > -
> > > -Required properties:
> > > -- compatible: "snps,axi-dma-1.01a"
> > > -- reg: Address range of the DMAC registers. This should include
> > > - all of the per-channel registers.
> > > -- interrupt: Should contain the DMAC interrupt number.
> > > -- dma-channels: Number of channels supported by hardware.
> > > -- snps,dma-masters: Number of AXI masters supported by the
> > hardware.
> > > -- snps,data-width: Maximum AXI data width supported by
> hardware.
> > > - (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> > > -- snps,priority: Priority of channel. Array size is equal to the
> > > number of
> > > - dma-channels. Priority value must be programmed within
> > > [0:dma-channels-1]
> > > - range. (0 - minimum priority)
> > > -- snps,block-size: Maximum block size supported by the controller
> > channel.
> > > - Array size is equal to the number of dma-channels.
> > > -
> > > -Optional properties:
> > > -- snps,axi-max-burst-len: Restrict master AXI burst length by value
> > > specified
> > > - in this property. If this property is missing the maximum AXI
> > > burst length
> > > - supported by DMAC is used. [1:256]
> > > -
> > > -Example:
> > > -
> > > -dmac: dma-controller@80000 {
> > > - compatible = "snps,axi-dma-1.01a";
> > > - reg = <0x80000 0x400>;
> > > - clocks = <&core_clk>, <&cfgr_clk>;
> > > - clock-names = "core-clk", "cfgr-clk";
> > > - interrupt-parent = <&intc>;
> > > - interrupts = <27>;
> > > -
> > > - dma-channels = <4>;
> > > - snps,dma-masters = <2>;
> > > - snps,data-width = <3>;
> > > - snps,block-size = <4096 4096 4096 4096>;
> > > - snps,priority = <0 1 2 3>;
> > > - snps,axi-max-burst-len = <16>;
> > > -};
> > > diff --git
> > > a/Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.yaml
> > > b/Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.yaml
> > > new file mode 100644
> > > index 000000000000..6c2e8e612af5
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-
> > dmac.yaml
> > > @@ -0,0 +1,126 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML
> > 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/dma/snps,dw-axi-
> dmac.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Synopsys DesignWare AXI DMA Controller
> > > +
> > > +maintainers:
> > > + - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
> > > +
> > > +description: |
> >
> > Don't need '|' unless there's formatting to preserve.
> >
> > > + Synopsys DesignWare AXI DMA Controller DT Binding
> >
> > And should be 2 space indent.
> >
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - snps,axi-dma-1.01a
> > > +
> > > + reg:
> > > + items:
> > > + - description: Address range of the DMAC registers
> >
> > Just 'maxItems: 1'
> >
> > > +
> > > + reg-names:
> > > + items:
> > > + - const: axidma_ctrl_regs
> > > +
> > > + interrupts:
> > > + maxItems: 1
> > > +
> > > + clocks:
> > > + items:
> > > + - description: Bus Clock
> > > + - description: Module Clock
> > > +
> > > + clock-names:
> > > + items:
> > > + - const: core-clk
> > > + - const: cfgr-clk
> > > +
> > > + '#dma-cells':
> > > + const: 1
> > > +
> > > + dma-channels:
> > > + description: |
> > > + Number of channels supported by hardware.
> >
> > No need to describe a common property. You do need to provide
> some
> > constraints. I'd assume there's less than 2^32 channels.
> >
> > > +
> > > + snps,dma-masters:
> > > + description: |
> > > + Number of AXI masters supported by the hardware.
> > > + allOf:
> >
> > You don't need to use allOf with a $ref anymore.
> >
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - enum: [1, 2]
> > > + default: 2
> > > +
> > > + snps,data-width:
> > > + description: |
> > > + AXI data width supported by hardware.
> > > + (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + - enum: [0, 1, 2, 3, 4, 5, 6]
> > > + default: 4
> > > +
> > > + snps,priority:
> > > + description: |
> > > + Channel priority specifier associated with the DMA channels.
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32-array
> > > + - minItems: 1
> > > + maxItems: 8
> > > + default: [0, 1, 2, 3]
> > > +
> > > + snps,block-size:
> > > + description: |
> > > + Channel block size specifier associated with the DMA
> channels.
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32-array
> > > + - minItems: 1
> > > + maxItems: 8
> > > + default: [4096, 4096, 4096, 4096]
> > > +
> > > + snps,axi-max-burst-len:
> > > + description: |
> > > + Restrict master AXI burst length by value specified in this
> > property.
> > > + If this property is missing the maximum AXI burst length
> > supported by
> > > + DMAC is used. [1:256]
> >
> > Looks like some constraints.
> >
> > > + allOf:
> > > + - $ref: /schemas/types.yaml#/definitions/uint32
> > > + default: 16
> > > +
> > > +required:
> > > + - compatible
> > > + - reg
> > > + - clocks
> > > + - clock-names
> > > + - interrupts
> > > + - '#dma-cells'
> > > + - dma-channels
> > > + - snps,dma-masters
> > > + - snps,data-width
> > > + - snps,priority
> > > + - snps,block-size
> > > +
> > > +additionalProperties: false
> > > +
> > > +examples:
> > > + - |
> > > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > > + #include <dt-bindings/interrupt-controller/irq.h>
> > > + /* example with snps,dw-axi-dmac */
> > > + dmac: dma-controller@80000 {
> > > + compatible = "snps,axi-dma-1.01a";
> > > + reg = <0x80000 0x400>;
> > > + clocks = <&core_clk>, <&cfgr_clk>;
> > > + clock-names = "core-clk", "cfgr-clk";
> > > + interrupt-parent = <&intc>;
> > > + interrupts = <27>;
> > > + #dma-cells = <1>;
> > > + dma-channels = <4>;
> > > + snps,dma-masters = <2>;
> > > + snps,data-width = <3>;
> > > + snps,block-size = <4096 4096 4096 4096>;
> > > + snps,priority = <0 1 2 3>;
> > > + snps,axi-max-burst-len = <16>;
> > > + };
> > > --
> > > 2.18.0
> > >
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v5 02/16] dmaengine: dw-axi-dmac: simplify descriptor management
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
` (13 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Simplify and refactor the descriptor management by removing the redundant
Linked List Item (LLI) queue control logic from the AxiDMA driver.
The descriptor is split into virtual descriptor and hardware LLI so that
only hardware LLI memories are allocated from the DMA memory pool.
Up to 64 descriptors can be allocated within a PAGE_SIZE compare to 16
descriptors in previous version. This solves the problem where an
ALSA driver expects more than 16 DMA descriptors to run.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 164 ++++++++++--------
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 9 +-
2 files changed, 102 insertions(+), 71 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 14c1ac26f866..8cfd645479e1 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -21,6 +21,7 @@
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
+#include <linux/slab.h>
#include <linux/types.h>
#include "dw-axi-dmac.h"
@@ -195,43 +196,58 @@ static inline const char *axi_chan_name(struct axi_dma_chan *chan)
return dma_chan_name(&chan->vc.chan);
}
-static struct axi_dma_desc *axi_desc_get(struct axi_dma_chan *chan)
+static struct axi_dma_desc *axi_desc_alloc(u32 num)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_desc *desc;
+
+ desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
+ if (!desc)
+ return NULL;
+
+ desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT);
+ if (!desc->hw_desc) {
+ kfree(desc);
+ return NULL;
+ }
+
+ return desc;
+}
+
+static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
+ dma_addr_t *addr)
+{
+ struct dw_axi_dma *dw = chan->chip->dw;
+ struct axi_dma_lli *lli;
dma_addr_t phys;
- desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys);
- if (unlikely(!desc)) {
+ lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys);
+ if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors available\n",
axi_chan_name(chan));
return NULL;
}
atomic_inc(&chan->descs_allocated);
- INIT_LIST_HEAD(&desc->xfer_list);
- desc->vd.tx.phys = phys;
- desc->chan = chan;
+ *addr = phys;
- return desc;
+ return lli;
}
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
struct dw_axi_dma *dw = chan->chip->dw;
- struct axi_dma_desc *child, *_next;
- unsigned int descs_put = 0;
+ int count = atomic_read(&chan->descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ int descs_put;
- list_for_each_entry_safe(child, _next, &desc->xfer_list, xfer_list) {
- list_del(&child->xfer_list);
- dma_pool_free(dw->desc_pool, child, child->vd.tx.phys);
- descs_put++;
+ for (descs_put = 0; descs_put < count; descs_put++) {
+ hw_desc = &desc->hw_desc[descs_put];
+ dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
}
- dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys);
- descs_put++;
-
+ kfree(desc->hw_desc);
+ kfree(desc);
atomic_sub(descs_put, &chan->descs_allocated);
dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n",
axi_chan_name(chan), descs_put,
@@ -258,9 +274,9 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
return ret;
}
-static void write_desc_llp(struct axi_dma_desc *desc, dma_addr_t adr)
+static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
{
- desc->lli.llp = cpu_to_le64(adr);
+ desc->lli->llp = cpu_to_le64(adr);
}
static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr)
@@ -295,7 +311,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
axi_chan_iowrite32(chan, CH_CFG_H, reg);
- write_chan_llp(chan, first->vd.tx.phys | lms);
+ write_chan_llp(chan, first->hw_desc[0].llp | lms);
irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR;
axi_chan_irq_sig_set(chan, irq_mask);
@@ -378,67 +394,78 @@ static void dma_chan_free_chan_resources(struct dma_chan *dchan)
* transfer and completes the DMA transfer operation at the end of current
* block transfer.
*/
-static void set_desc_last(struct axi_dma_desc *desc)
+static void set_desc_last(struct axi_dma_hw_desc *desc)
{
u32 val;
- val = le32_to_cpu(desc->lli.ctl_hi);
+ val = le32_to_cpu(desc->lli->ctl_hi);
val |= CH_CTL_H_LLI_LAST;
- desc->lli.ctl_hi = cpu_to_le32(val);
+ desc->lli->ctl_hi = cpu_to_le32(val);
}
-static void write_desc_sar(struct axi_dma_desc *desc, dma_addr_t adr)
+static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
{
- desc->lli.sar = cpu_to_le64(adr);
+ desc->lli->sar = cpu_to_le64(adr);
}
-static void write_desc_dar(struct axi_dma_desc *desc, dma_addr_t adr)
+static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr)
{
- desc->lli.dar = cpu_to_le64(adr);
+ desc->lli->dar = cpu_to_le64(adr);
}
-static void set_desc_src_master(struct axi_dma_desc *desc)
+static void set_desc_src_master(struct axi_dma_hw_desc *desc)
{
u32 val;
/* Select AXI0 for source master */
- val = le32_to_cpu(desc->lli.ctl_lo);
+ val = le32_to_cpu(desc->lli->ctl_lo);
val &= ~CH_CTL_L_SRC_MAST;
- desc->lli.ctl_lo = cpu_to_le32(val);
+ desc->lli->ctl_lo = cpu_to_le32(val);
}
-static void set_desc_dest_master(struct axi_dma_desc *desc)
+static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
+ struct axi_dma_desc *desc)
{
u32 val;
/* Select AXI1 for source master if available */
- val = le32_to_cpu(desc->lli.ctl_lo);
+ val = le32_to_cpu(hw_desc->lli->ctl_lo);
if (desc->chan->chip->dw->hdata->nr_masters > 1)
val |= CH_CTL_L_DST_MAST;
else
val &= ~CH_CTL_L_DST_MAST;
- desc->lli.ctl_lo = cpu_to_le32(val);
+ hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
static struct dma_async_tx_descriptor *
dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
dma_addr_t src_adr, size_t len, unsigned long flags)
{
- struct axi_dma_desc *first = NULL, *desc = NULL, *prev = NULL;
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
size_t block_ts, max_block_ts, xfer_len;
- u32 xfer_width, reg;
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ u32 xfer_width, reg, num;
+ u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx",
axi_chan_name(chan), &src_adr, &dst_adr, len, flags);
max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+ xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len);
+ num = DIV_ROUND_UP(len, max_block_ts << xfer_width);
+ desc = axi_desc_alloc(num);
+ if (unlikely(!desc))
+ goto err_desc_get;
+ desc->chan = chan;
+ num = 0;
while (len) {
xfer_len = len;
+ hw_desc = &desc->hw_desc[num];
/*
* Take care for the alignment.
* Actually source and destination widths can be different, but
@@ -457,13 +484,13 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
xfer_len = max_block_ts << xfer_width;
}
- desc = axi_desc_get(chan);
- if (unlikely(!desc))
+ hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
+ if (unlikely(!hw_desc->lli))
goto err_desc_get;
- write_desc_sar(desc, src_adr);
- write_desc_dar(desc, dst_adr);
- desc->lli.block_ts_lo = cpu_to_le32(block_ts - 1);
+ write_desc_sar(hw_desc, src_adr);
+ write_desc_dar(hw_desc, dst_adr);
+ hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
reg = CH_CTL_H_LLI_VALID;
if (chan->chip->dw->hdata->restrict_axi_burst_len) {
@@ -474,7 +501,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
CH_CTL_H_AWLEN_EN |
burst_len << CH_CTL_H_AWLEN_POS);
}
- desc->lli.ctl_hi = cpu_to_le32(reg);
+ hw_desc->lli->ctl_hi = cpu_to_le32(reg);
reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS |
@@ -482,62 +509,61 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
xfer_width << CH_CTL_L_SRC_WIDTH_POS |
DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS);
- desc->lli.ctl_lo = cpu_to_le32(reg);
+ hw_desc->lli->ctl_lo = cpu_to_le32(reg);
- set_desc_src_master(desc);
- set_desc_dest_master(desc);
+ set_desc_src_master(hw_desc);
+ set_desc_dest_master(hw_desc, desc);
- /* Manage transfer list (xfer_list) */
- if (!first) {
- first = desc;
- } else {
- list_add_tail(&desc->xfer_list, &first->xfer_list);
- write_desc_llp(prev, desc->vd.tx.phys | lms);
- }
- prev = desc;
/* update the length and addresses for the next loop cycle */
len -= xfer_len;
dst_adr += xfer_len;
src_adr += xfer_len;
+ num++;
}
/* Total len of src/dest sg == 0, so no descriptor were allocated */
- if (unlikely(!first))
+ if (unlikely(!desc))
return NULL;
/* Set end-of-link to the last link descriptor of list */
- set_desc_last(desc);
+ set_desc_last(&desc->hw_desc[num - 1]);
+ /* Managed transfer list */
+ do {
+ hw_desc = &desc->hw_desc[--num];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (num);
- return vchan_tx_prep(&chan->vc, &first->vd, flags);
+ return vchan_tx_prep(&chan->vc, &desc->vd, flags);
err_desc_get:
- if (first)
- axi_desc_put(first);
+ if (desc)
+ axi_desc_put(desc);
return NULL;
}
static void axi_chan_dump_lli(struct axi_dma_chan *chan,
- struct axi_dma_desc *desc)
+ struct axi_dma_hw_desc *desc)
{
dev_err(dchan2dev(&chan->vc.chan),
"SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x",
- le64_to_cpu(desc->lli.sar),
- le64_to_cpu(desc->lli.dar),
- le64_to_cpu(desc->lli.llp),
- le32_to_cpu(desc->lli.block_ts_lo),
- le32_to_cpu(desc->lli.ctl_hi),
- le32_to_cpu(desc->lli.ctl_lo));
+ le64_to_cpu(desc->lli->sar),
+ le64_to_cpu(desc->lli->dar),
+ le64_to_cpu(desc->lli->llp),
+ le32_to_cpu(desc->lli->block_ts_lo),
+ le32_to_cpu(desc->lli->ctl_hi),
+ le32_to_cpu(desc->lli->ctl_lo));
}
static void axi_chan_list_dump_lli(struct axi_dma_chan *chan,
struct axi_dma_desc *desc_head)
{
- struct axi_dma_desc *desc;
+ int count = atomic_read(&chan->descs_allocated);
+ int i;
- axi_chan_dump_lli(chan, desc_head);
- list_for_each_entry(desc, &desc_head->xfer_list, xfer_list)
- axi_chan_dump_lli(chan, desc);
+ for (i = 0; i < count; i++)
+ axi_chan_dump_lli(chan, &desc_head->hw_desc[i]);
}
static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
@@ -872,7 +898,7 @@ static int dw_probe(struct platform_device *pdev)
/* Lli address must be aligned to a 64-byte boundary */
dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
- sizeof(struct axi_dma_desc), 64, 0);
+ sizeof(struct axi_dma_lli), 64, 0);
if (!dw->desc_pool) {
dev_err(chip->dev, "No memory for descriptors dma pool\n");
return -ENOMEM;
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 18b6014cf9b4..41e775e6e593 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -41,6 +41,7 @@ struct axi_dma_chan {
struct virt_dma_chan vc;
+ struct axi_dma_desc *desc;
/* these other elements are all protected by vc.lock */
bool is_paused;
};
@@ -80,12 +81,16 @@ struct __packed axi_dma_lli {
__le32 reserved_hi;
};
+struct axi_dma_hw_desc {
+ struct axi_dma_lli *lli;
+ dma_addr_t llp;
+};
+
struct axi_dma_desc {
- struct axi_dma_lli lli;
+ struct axi_dma_hw_desc *hw_desc;
struct virt_dma_desc vd;
struct axi_dma_chan *chan;
- struct list_head xfer_list;
};
static inline struct device *dchan2dev(struct dma_chan *dchan)
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources()
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 01/16] dt-bindings: dma: Add YAML schemas for dw-axi-dmac Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 02/16] dmaengine: dw-axi-dmac: simplify descriptor management Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
` (12 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
The DMA memory block is created at driver load time and exist for
device lifetime. Move the dma_pool_create() to the ->chan_resource()
callback function allowing the DMA memory blocks to be created as needed
and destroyed when the channel is freed.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 24 ++++++++++---------
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +-
2 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 8cfd645479e1..46e2ba978e20 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -216,11 +216,10 @@ static struct axi_dma_desc *axi_desc_alloc(u32 num)
static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
dma_addr_t *addr)
{
- struct dw_axi_dma *dw = chan->chip->dw;
struct axi_dma_lli *lli;
dma_addr_t phys;
- lli = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys);
+ lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys);
if (unlikely(!lli)) {
dev_err(chan2dev(chan), "%s: not enough descriptors available\n",
axi_chan_name(chan));
@@ -236,14 +235,13 @@ static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan,
static void axi_desc_put(struct axi_dma_desc *desc)
{
struct axi_dma_chan *chan = desc->chan;
- struct dw_axi_dma *dw = chan->chip->dw;
int count = atomic_read(&chan->descs_allocated);
struct axi_dma_hw_desc *hw_desc;
int descs_put;
for (descs_put = 0; descs_put < count; descs_put++) {
hw_desc = &desc->hw_desc[descs_put];
- dma_pool_free(dw->desc_pool, hw_desc->lli, hw_desc->llp);
+ dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp);
}
kfree(desc->hw_desc);
@@ -360,6 +358,15 @@ static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
return -EBUSY;
}
+ /* LLI address must be aligned to a 64-byte boundary */
+ chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)),
+ chan->chip->dev,
+ sizeof(struct axi_dma_lli),
+ 64, 0);
+ if (!chan->desc_pool) {
+ dev_err(chan2dev(chan), "No memory for descriptors\n");
+ return -ENOMEM;
+ }
dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan));
pm_runtime_get(chan->chip->dev);
@@ -381,6 +388,8 @@ static void dma_chan_free_chan_resources(struct dma_chan *dchan)
vchan_free_chan_resources(&chan->vc);
+ dma_pool_destroy(chan->desc_pool);
+ chan->desc_pool = NULL;
dev_vdbg(dchan2dev(dchan),
"%s: free resources, descriptor still allocated: %u\n",
axi_chan_name(chan), atomic_read(&chan->descs_allocated));
@@ -896,13 +905,6 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
return ret;
- /* Lli address must be aligned to a 64-byte boundary */
- dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
- sizeof(struct axi_dma_lli), 64, 0);
- if (!dw->desc_pool) {
- dev_err(chip->dev, "No memory for descriptors dma pool\n");
- return -ENOMEM;
- }
INIT_LIST_HEAD(&dw->dma.channels);
for (i = 0; i < hdata->nr_channels; i++) {
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 41e775e6e593..f886b2bb75de 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -39,6 +39,7 @@ struct axi_dma_chan {
u8 id;
atomic_t descs_allocated;
+ struct dma_pool *desc_pool;
struct virt_dma_chan vc;
struct axi_dma_desc *desc;
@@ -49,7 +50,6 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
- struct dma_pool *desc_pool;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (2 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 03/16] dmaengine: dw-axi-dmac: move dma_pool_create() to alloc_chan_resources() Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 05/16] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
` (11 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for device_synchronize() callback function to sync with
dmaengine_terminate_sync().
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 46e2ba978e20..56b213211341 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -347,6 +347,13 @@ static void dma_chan_issue_pending(struct dma_chan *dchan)
spin_unlock_irqrestore(&chan->vc.lock, flags);
}
+static void dw_axi_dma_synchronize(struct dma_chan *dchan)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ vchan_synchronize(&chan->vc);
+}
+
static int dma_chan_alloc_chan_resources(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
@@ -940,6 +947,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
+ dw->dma.device_synchronize = dw_axi_dma_synchronize;
platform_set_drvdata(pdev, chip);
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 05/16] dmaengine: dw-axi-dmac: Add device_config operation
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (3 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 04/16] dmaengine: dw-axi-dmac: Add device_synchronize() callback Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
` (10 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add device_config() callback function so that the device address
can be passed to the dma driver.
DMA clients use this interface to pass in the device address to the
AxiDMA. Without this interface, data transfer between device to memory
and memory to device would failed.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 11 +++++++++++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 56b213211341..16e6934ae9a1 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -559,6 +559,16 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
return NULL;
}
+static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan,
+ struct dma_slave_config *config)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+
+ memcpy(&chan->config, config, sizeof(*config));
+
+ return 0;
+}
+
static void axi_chan_dump_lli(struct axi_dma_chan *chan,
struct axi_dma_hw_desc *desc)
{
@@ -948,6 +958,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
dw->dma.device_synchronize = dw_axi_dma_synchronize;
+ dw->dma.device_config = dw_axi_dma_chan_slave_config;
platform_set_drvdata(pdev, chip);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index f886b2bb75de..a75b921d6b1a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -43,6 +43,7 @@ struct axi_dma_chan {
struct virt_dma_chan vc;
struct axi_dma_desc *desc;
+ struct dma_slave_config config;
/* these other elements are all protected by vc.lock */
bool is_paused;
};
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (4 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 05/16] dmaengine: dw-axi-dmac: Add device_config operation Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
` (9 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV
and DMA_DEV_TO_MEM operations in single mode can be supported.
Existing AxiDMA driver only support data transfer between
memory to memory. Data transfer between device to memory and
memory to device in single mode would failed if this interface
is not supported by the AxiDMA driver.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 154 ++++++++++++++++++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 155 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 16e6934ae9a1..1674dcb6fc5b 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -307,6 +307,22 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
priority << CH_CFG_H_PRIORITY_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_DST_POS |
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
+ DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg |= (chan->config.device_fc ?
+ DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
+ DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
+ << CH_CFG_H_TT_FC_POS;
+ break;
+ default:
+ break;
+ }
axi_chan_iowrite32(chan, CH_CFG_H, reg);
write_chan_llp(chan, first->hw_desc[0].llp | lms);
@@ -454,6 +470,141 @@ static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc,
hw_desc->lli->ctl_lo = cpu_to_le32(val);
}
+static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
+ struct axi_dma_hw_desc *hw_desc,
+ dma_addr_t mem_addr, size_t len)
+{
+ unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ unsigned int reg_width;
+ unsigned int mem_width;
+ dma_addr_t device_addr;
+ size_t axi_block_ts;
+ size_t block_ts;
+ u32 ctllo, ctlhi;
+ u32 burst_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ mem_width = __ffs(data_width | mem_addr | len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ switch (chan->direction) {
+ case DMA_MEM_TO_DEV:
+ reg_width = __ffs(chan->config.dst_addr_width);
+ device_addr = chan->config.dst_addr;
+ ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS |
+ mem_width << CH_CTL_L_SRC_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ device_addr = chan->config.src_addr;
+ ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS |
+ mem_width << CH_CTL_L_DST_WIDTH_POS |
+ DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS |
+ DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS;
+ block_ts = len >> reg_width;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (block_ts > axi_block_ts)
+ return -EINVAL;
+
+ hw_desc->lli = axi_desc_get(chan, &hw_desc->llp);
+ if (unlikely(!hw_desc->lli))
+ return -ENOMEM;
+
+ ctlhi = CH_CTL_H_LLI_VALID;
+
+ if (chan->chip->dw->hdata->restrict_axi_burst_len) {
+ burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
+ ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN |
+ burst_len << CH_CTL_H_ARLEN_POS |
+ burst_len << CH_CTL_H_AWLEN_POS;
+ }
+
+ hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi);
+
+ if (chan->direction == DMA_MEM_TO_DEV) {
+ write_desc_sar(hw_desc, mem_addr);
+ write_desc_dar(hw_desc, device_addr);
+ } else {
+ write_desc_sar(hw_desc, device_addr);
+ write_desc_dar(hw_desc, mem_addr);
+ }
+
+ hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1);
+
+ ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS |
+ DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS;
+ hw_desc->lli->ctl_lo = cpu_to_le32(ctllo);
+
+ set_desc_src_master(hw_desc);
+
+ return 0;
+}
+
+static struct dma_async_tx_descriptor *
+dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
+ unsigned int sg_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags, void *context)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ struct scatterlist *sg;
+ unsigned int i;
+ u32 mem, len;
+ int status;
+ u64 llp = 0;
+ u8 lms = 0; /* Select AXI0 master for LLI fetching */
+
+ if (unlikely(!is_slave_direction(direction) || !sg_len))
+ return NULL;
+
+ chan->direction = direction;
+
+ desc = axi_desc_alloc(sg_len);
+ if (unlikely(!desc))
+ goto err_desc_get;
+
+ desc->chan = chan;
+
+ for_each_sg(sgl, sg, sg_len, i) {
+ mem = sg_dma_address(sg);
+ len = sg_dma_len(sg);
+ hw_desc = &desc->hw_desc[i];
+
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
+ if (status < 0)
+ goto err_desc_get;
+ }
+
+ /* Set end-of-link to the last link descriptor of list */
+ set_desc_last(&desc->hw_desc[sg_len - 1]);
+
+ /* Managed transfer list */
+ do {
+ hw_desc = &desc->hw_desc[--sg_len];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (sg_len);
+
+ return vchan_tx_prep(&chan->vc, &desc->vd, flags);
+
+err_desc_get:
+ if (desc)
+ axi_desc_put(desc);
+
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *
dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
dma_addr_t src_adr, size_t len, unsigned long flags)
@@ -938,12 +1089,14 @@ static int dw_probe(struct platform_device *pdev)
/* Set capabilities */
dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
+ dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
/* DMA capabilities */
dw->dma.chancnt = hdata->nr_channels;
dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.directions = BIT(DMA_MEM_TO_MEM);
+ dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
dw->dma.dev = chip->dev;
@@ -959,6 +1112,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
dw->dma.device_synchronize = dw_axi_dma_synchronize;
dw->dma.device_config = dw_axi_dma_chan_slave_config;
+ dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
platform_set_drvdata(pdev, chip);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index a75b921d6b1a..ac49f2e14b0c 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -44,6 +44,7 @@ struct axi_dma_chan {
struct axi_dma_desc *desc;
struct dma_slave_config config;
+ enum dma_transfer_direction direction;
/* these other elements are all protected by vc.lock */
bool is_paused;
};
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (5 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 06/16] dmaengine: dw-axi-dmac: Support device_prep_slave_sg Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
` (8 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for device_prep_dma_cyclic() callback function to benefit
DMA cyclic client, for example ALSA.
Existing AxiDMA driver only support data transfer between memory to memory.
Data transfer between device to memory and memory to device in cyclic mode
would failed if this interface is not supported by the AxiDMA driver.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 111 ++++++++++++++++--
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 106 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 1674dcb6fc5b..b5f92f9cb2bc 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -15,6 +15,8 @@
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
@@ -549,6 +551,64 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
return 0;
}
+static struct dma_async_tx_descriptor *
+dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
+ size_t buf_len, size_t period_len,
+ enum dma_transfer_direction direction,
+ unsigned long flags)
+{
+ struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ struct axi_dma_hw_desc *hw_desc = NULL;
+ struct axi_dma_desc *desc = NULL;
+ dma_addr_t src_addr = dma_addr;
+ u32 num_periods = buf_len / period_len;
+ unsigned int i;
+ int status;
+ u64 llp = 0;
+ u8 lms = 0; /* Select AXI0 master for LLI fetching */
+
+ desc = axi_desc_alloc(num_periods);
+ if (unlikely(!desc))
+ goto err_desc_get;
+
+ chan->direction = direction;
+ desc->chan = chan;
+ chan->cyclic = true;
+
+ for (i = 0; i < num_periods; i++) {
+ hw_desc = &desc->hw_desc[i];
+
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
+ period_len);
+ if (status < 0)
+ goto err_desc_get;
+
+ /* Set end-of-link to the linked descriptor, so that cyclic
+ * callback function can be triggered during interrupt.
+ */
+ set_desc_last(hw_desc);
+
+ src_addr += period_len;
+ }
+
+ llp = desc->hw_desc[0].llp;
+
+ /* Managed transfer list */
+ do {
+ hw_desc = &desc->hw_desc[--num_periods];
+ write_desc_llp(hw_desc, llp | lms);
+ llp = hw_desc->llp;
+ } while (num_periods);
+
+ return vchan_tx_prep(&chan->vc, &desc->vd, flags);
+
+err_desc_get:
+ if (desc)
+ axi_desc_put(desc);
+
+ return NULL;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
unsigned int sg_len,
@@ -773,8 +833,13 @@ static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status)
static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
{
+ int count = atomic_read(&chan->descs_allocated);
+ struct axi_dma_hw_desc *hw_desc;
+ struct axi_dma_desc *desc;
struct virt_dma_desc *vd;
unsigned long flags;
+ u64 llp;
+ int i;
spin_lock_irqsave(&chan->vc.lock, flags);
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -785,12 +850,32 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
/* The completed descriptor currently is in the head of vc list */
vd = vchan_next_desc(&chan->vc);
- /* Remove the completed descriptor from issued list before completing */
- list_del(&vd->node);
- vchan_cookie_complete(vd);
- /* Submit queued descriptors after processing the completed ones */
- axi_chan_start_first_queued(chan);
+ if (chan->cyclic) {
+ vchan_cyclic_callback(vd);
+ desc = vd_to_axi_desc(vd);
+ if (desc) {
+ llp = lo_hi_readq(chan->chan_regs + CH_LLP);
+ for (i = 0; i < count; i++) {
+ hw_desc = &desc->hw_desc[i];
+ if (hw_desc->llp == llp) {
+ axi_chan_irq_clear(chan, hw_desc->lli->status_lo);
+ hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID;
+ desc->completed_blocks = i;
+ break;
+ }
+ }
+
+ axi_chan_enable(chan);
+ }
+ } else {
+ /* Remove the completed descriptor from issued list before completing */
+ list_del(&vd->node);
+ vchan_cookie_complete(vd);
+
+ /* Submit queued descriptors after processing the completed ones */
+ axi_chan_start_first_queued(chan);
+ }
spin_unlock_irqrestore(&chan->vc.lock, flags);
}
@@ -830,15 +915,25 @@ static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id)
static int dma_chan_terminate_all(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
+ u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
unsigned long flags;
+ u32 val;
+ int ret;
LIST_HEAD(head);
- spin_lock_irqsave(&chan->vc.lock, flags);
-
axi_chan_disable(chan);
+ ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val,
+ !(val & chan_active), 1000, 10000);
+ if (ret == -ETIMEDOUT)
+ dev_warn(dchan2dev(dchan),
+ "%s failed to stop\n", axi_chan_name(chan));
+
+ spin_lock_irqsave(&chan->vc.lock, flags);
+
vchan_get_all_descriptors(&chan->vc, &head);
+ chan->cyclic = false;
spin_unlock_irqrestore(&chan->vc.lock, flags);
vchan_dma_desc_free_list(&chan->vc, &head);
@@ -1090,6 +1185,7 @@ static int dw_probe(struct platform_device *pdev)
/* Set capabilities */
dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
dma_cap_set(DMA_SLAVE, dw->dma.cap_mask);
+ dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask);
/* DMA capabilities */
dw->dma.chancnt = hdata->nr_channels;
@@ -1113,6 +1209,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_synchronize = dw_axi_dma_synchronize;
dw->dma.device_config = dw_axi_dma_chan_slave_config;
dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
+ dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
platform_set_drvdata(pdev, chip);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index ac49f2e14b0c..a26b0a242a93 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -45,6 +45,7 @@ struct axi_dma_chan {
struct axi_dma_desc *desc;
struct dma_slave_config config;
enum dma_transfer_direction direction;
+ bool cyclic;
/* these other elements are all protected by vc.lock */
bool is_paused;
};
@@ -93,6 +94,7 @@ struct axi_dma_desc {
struct virt_dma_desc vd;
struct axi_dma_chan *chan;
+ u32 completed_blocks;
};
static inline struct device *dchan2dev(struct dma_chan *dchan)
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register()
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (6 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 07/16] dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic() Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
` (7 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for of_dma_controller_register() so that DMA clients
can pass in device handshake number to the AxiDMA driver.
DMA clients shall code the device handshake number in the Device tree.
When DMA activities are needed, DMA clients shall invoke OF helper
function to pass in the device handshake number to the AxiDMA.
Without register to the of_dma_controller_register(), data transfer
between memory to device and device to memory operations would failed.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 26 +++++++++++++++++++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index b5f92f9cb2bc..40c4af0e0421 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -20,6 +20,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_dma.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/property.h>
@@ -1044,6 +1045,22 @@ static int __maybe_unused axi_dma_runtime_resume(struct device *dev)
return axi_dma_resume(chip);
}
+static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *ofdma)
+{
+ struct dw_axi_dma *dw = ofdma->of_dma_data;
+ struct axi_dma_chan *chan;
+ struct dma_chan *dchan;
+
+ dchan = dma_get_any_slave_channel(&dw->dma);
+ if (!dchan)
+ return NULL;
+
+ chan = dchan_to_axi_dma_chan(dchan);
+ chan->hw_handshake_num = dma_spec->args[0];
+ return dchan;
+}
+
static int parse_device_properties(struct axi_dma_chip *chip)
{
struct device *dev = chip->dev;
@@ -1233,6 +1250,13 @@ static int dw_probe(struct platform_device *pdev)
if (ret)
goto err_pm_disable;
+ /* Register with OF helpers for DMA lookups */
+ ret = of_dma_controller_register(pdev->dev.of_node,
+ dw_axi_dma_of_xlate, dw);
+ if (ret < 0)
+ dev_warn(&pdev->dev,
+ "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n");
+
dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n",
dw->hdata->nr_channels);
@@ -1266,6 +1290,8 @@ static int dw_remove(struct platform_device *pdev)
devm_free_irq(chip->dev, chip->irq, chip);
+ of_dma_controller_free(chip->dev->of_node);
+
list_for_each_entry_safe(chan, _chan, &dw->dma.channels,
vc.chan.device_node) {
list_del(&chan->vc.chan.device_node);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index a26b0a242a93..3498bef5453b 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -37,6 +37,7 @@ struct axi_dma_chan {
struct axi_dma_chip *chip;
void __iomem *chan_regs;
u8 id;
+ u8 hw_handshake_num;
atomic_t descs_allocated;
struct dma_pool *desc_pool;
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (7 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 08/16] dmaengine: dw-axi-dmac: Support of_dma_controller_register() Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
` (6 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for DMA_RESIDUE_GRANULARITY_BURST so that AxiDMA can report
DMA residue.
Existing AxiDMA driver only support data transfer between
memory to memory operation, therefore reporting DMA residue
to the DMA clients is not supported.
Reporting DMA residue to the DMA clients is important as DMA clients
shall invoke dmaengine_tx_status() to understand the number of bytes
been transferred so that the buffer pointer can be updated accordingly.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 43 ++++++++++++++++---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 2 +
2 files changed, 38 insertions(+), 7 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 40c4af0e0421..29323e75bc44 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -265,14 +265,36 @@ dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie,
struct dma_tx_state *txstate)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
- enum dma_status ret;
+ struct virt_dma_desc *vdesc;
+ enum dma_status status;
+ u32 completed_length;
+ unsigned long flags;
+ u32 completed_blocks;
+ size_t bytes = 0;
+ u32 length;
+ u32 len;
- ret = dma_cookie_status(dchan, cookie, txstate);
+ status = dma_cookie_status(dchan, cookie, txstate);
+ if (status == DMA_COMPLETE || !txstate)
+ return status;
- if (chan->is_paused && ret == DMA_IN_PROGRESS)
- ret = DMA_PAUSED;
+ spin_lock_irqsave(&chan->vc.lock, flags);
- return ret;
+ vdesc = vchan_find_desc(&chan->vc, cookie);
+ if (vdesc) {
+ length = vd_to_axi_desc(vdesc)->length;
+ completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks;
+ len = vd_to_axi_desc(vdesc)->hw_desc[0].len;
+ completed_length = completed_blocks * len;
+ bytes = length - completed_length;
+ } else {
+ bytes = vd_to_axi_desc(vdesc)->length;
+ }
+
+ spin_unlock_irqrestore(&chan->vc.lock, flags);
+ dma_set_residue(txstate, bytes);
+
+ return status;
}
static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr)
@@ -549,6 +571,7 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
set_desc_src_master(hw_desc);
+ hw_desc->len = len;
return 0;
}
@@ -575,6 +598,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
chan->direction = direction;
desc->chan = chan;
chan->cyclic = true;
+ desc->length = 0;
for (i = 0; i < num_periods; i++) {
hw_desc = &desc->hw_desc[i];
@@ -584,6 +608,7 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
/* Set end-of-link to the linked descriptor, so that cyclic
* callback function can be triggered during interrupt.
*/
@@ -636,6 +661,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
goto err_desc_get;
desc->chan = chan;
+ desc->length = 0;
for_each_sg(sgl, sg, sg_len, i) {
mem = sg_dma_address(sg);
@@ -645,6 +671,7 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
if (status < 0)
goto err_desc_get;
+ desc->length += hw_desc->len;
}
/* Set end-of-link to the last link descriptor of list */
@@ -690,6 +717,7 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
desc->chan = chan;
num = 0;
+ desc->length = 0;
while (len) {
xfer_len = len;
@@ -742,7 +770,8 @@ dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr,
set_desc_src_master(hw_desc);
set_desc_dest_master(hw_desc, desc);
-
+ hw_desc->len = xfer_len;
+ desc->length += hw_desc->len;
/* update the length and addresses for the next loop cycle */
len -= xfer_len;
dst_adr += xfer_len;
@@ -1210,7 +1239,7 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
dw->dma.directions = BIT(DMA_MEM_TO_MEM);
dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM);
- dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
+ dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
dw->dma.dev = chip->dev;
dw->dma.device_tx_status = dma_chan_tx_status;
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3498bef5453b..46baf93de617 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -88,6 +88,7 @@ struct __packed axi_dma_lli {
struct axi_dma_hw_desc {
struct axi_dma_lli *lli;
dma_addr_t llp;
+ u32 len;
};
struct axi_dma_desc {
@@ -96,6 +97,7 @@ struct axi_dma_desc {
struct virt_dma_desc vd;
struct axi_dma_chan *chan;
u32 completed_blocks;
+ u32 length;
};
static inline struct device *dchan2dev(struct dma_chan *dchan)
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (8 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 09/16] dmaengine: dw-axi-dmac: Support burst residue granularity Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-30 22:29 ` Rob Herring
2020-11-23 2:34 ` [PATCH v5 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
` (5 subsequent siblings)
15 siblings, 1 reply; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for Intel KeemBay AxiDMA to the dw-axi-dmac
Schemas DT binding.
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../bindings/dma/snps,dw-axi-dmac.yaml | 27 +++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
index 6c2e8e612af5..9e3ca9083814 100644
--- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
@@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller
maintainers:
- Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
+ - Jee Heng Sia <jee.heng.sia@intel.com>
description: |
Synopsys DesignWare AXI DMA Controller DT Binding
@@ -16,14 +17,18 @@ properties:
compatible:
enum:
- snps,axi-dma-1.01a
+ - intel,kmb-axi-dma
reg:
+ minItems: 1
items:
- description: Address range of the DMAC registers
+ - description: Address range of the DMAC APB registers
reg-names:
items:
- const: axidma_ctrl_regs
+ - const: axidma_apb_regs
interrupts:
maxItems: 1
@@ -124,3 +129,25 @@ examples:
snps,priority = <0 1 2 3>;
snps,axi-max-burst-len = <16>;
};
+
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ /* example with intel,kmb-axi-dma */
+ #define KEEM_BAY_PSS_AXI_DMA
+ #define KEEM_BAY_PSS_APB_AXI_DMA
+ axi_dma: dma@28000000 {
+ compatible = "intel,kmb-axi-dma";
+ reg = <0x28000000 0x1000>, <0x20250000 0x24>;
+ reg-names = "axidma_ctrl_regs", "axidma_apb_regs";
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core-clk", "cfgr-clk";
+ clocks = <&scmi_clk KEEM_BAY_PSS_AXI_DMA>, <&scmi_clk KEEM_BAY_PSS_APB_AXI_DMA>;
+ #dma-cells = <1>;
+ dma-channels = <8>;
+ snps,dma-masters = <1>;
+ snps,data-width = <4>;
+ snps,priority = <0 0 0 0 0 0 0 0>;
+ snps,block-size = <1024 1024 1024 1024 1024 1024 1024 1024>;
+ snps,axi-max-burst-len = <16>;
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
2020-11-23 2:34 ` [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
@ 2020-11-30 22:29 ` Rob Herring
2020-12-09 1:53 ` Sia, Jee Heng
0 siblings, 1 reply; 24+ messages in thread
From: Rob Herring @ 2020-11-30 22:29 UTC (permalink / raw)
To: Sia Jee Heng
Cc: vkoul, Eugeniy.Paltsev, andriy.shevchenko, dmaengine,
linux-kernel, devicetree
On Mon, Nov 23, 2020 at 10:34:46AM +0800, Sia Jee Heng wrote:
> Add support for Intel KeemBay AxiDMA to the dw-axi-dmac
> Schemas DT binding.
>
> Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> ---
> .../bindings/dma/snps,dw-axi-dmac.yaml | 27 +++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> index 6c2e8e612af5..9e3ca9083814 100644
> --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller
>
> maintainers:
> - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
Also, for the first patch, missing a '>' on the end.
> + - Jee Heng Sia <jee.heng.sia@intel.com>
>
> description: |
> Synopsys DesignWare AXI DMA Controller DT Binding
> @@ -16,14 +17,18 @@ properties:
> compatible:
> enum:
> - snps,axi-dma-1.01a
> + - intel,kmb-axi-dma
>
> reg:
> + minItems: 1
> items:
> - description: Address range of the DMAC registers
> + - description: Address range of the DMAC APB registers
Nevermind for my 'reg' comment on the first patch.
>
> reg-names:
> items:
> - const: axidma_ctrl_regs
> + - const: axidma_apb_regs
>
> interrupts:
> maxItems: 1
> @@ -124,3 +129,25 @@ examples:
> snps,priority = <0 1 2 3>;
> snps,axi-max-burst-len = <16>;
> };
> +
> + - |
For what's just a new compatible and extra reg field, I don't think we
need another example.
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + /* example with intel,kmb-axi-dma */
> + #define KEEM_BAY_PSS_AXI_DMA
> + #define KEEM_BAY_PSS_APB_AXI_DMA
> + axi_dma: dma@28000000 {
> + compatible = "intel,kmb-axi-dma";
> + reg = <0x28000000 0x1000>, <0x20250000 0x24>;
> + reg-names = "axidma_ctrl_regs", "axidma_apb_regs";
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "core-clk", "cfgr-clk";
> + clocks = <&scmi_clk KEEM_BAY_PSS_AXI_DMA>, <&scmi_clk KEEM_BAY_PSS_APB_AXI_DMA>;
> + #dma-cells = <1>;
> + dma-channels = <8>;
> + snps,dma-masters = <1>;
> + snps,data-width = <4>;
> + snps,priority = <0 0 0 0 0 0 0 0>;
> + snps,block-size = <1024 1024 1024 1024 1024 1024 1024 1024>;
> + snps,axi-max-burst-len = <16>;
> + };
> --
> 2.18.0
>
^ permalink raw reply [flat|nested] 24+ messages in thread* RE: [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
2020-11-30 22:29 ` Rob Herring
@ 2020-12-09 1:53 ` Sia, Jee Heng
0 siblings, 0 replies; 24+ messages in thread
From: Sia, Jee Heng @ 2020-12-09 1:53 UTC (permalink / raw)
To: Rob Herring
Cc: vkoul, Eugeniy.Paltsev, andriy.shevchenko, dmaengine,
linux-kernel, devicetree
> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 01 December 2020 6:29 AM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: vkoul@kernel.org; Eugeniy.Paltsev@synopsys.com;
> andriy.shevchenko@linux.intel.com; dmaengine@vger.kernel.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add
> support for Intel KeemBay AxiDMA
>
> On Mon, Nov 23, 2020 at 10:34:46AM +0800, Sia Jee Heng wrote:
> > Add support for Intel KeemBay AxiDMA to the dw-axi-dmac Schemas
> DT
> > binding.
> >
> > Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
> > ---
> > .../bindings/dma/snps,dw-axi-dmac.yaml | 27
> +++++++++++++++++++
> > 1 file changed, 27 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> > index 6c2e8e612af5..9e3ca9083814 100644
> > --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.yaml
> > +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.yaml
> > @@ -8,6 +8,7 @@ title: Synopsys DesignWare AXI DMA Controller
> >
> > maintainers:
> > - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com
>
> Also, for the first patch, missing a '>' on the end.
[>>] Got it. Thanks for the catch.
>
> > + - Jee Heng Sia <jee.heng.sia@intel.com>
> >
> > description: |
> > Synopsys DesignWare AXI DMA Controller DT Binding @@ -16,14
> +17,18
> > @@ properties:
> > compatible:
> > enum:
> > - snps,axi-dma-1.01a
> > + - intel,kmb-axi-dma
> >
> > reg:
> > + minItems: 1
> > items:
> > - description: Address range of the DMAC registers
> > + - description: Address range of the DMAC APB registers
>
> Nevermind for my 'reg' comment on the first patch.
[>>] OK.
>
> >
> > reg-names:
> > items:
> > - const: axidma_ctrl_regs
> > + - const: axidma_apb_regs
> >
> > interrupts:
> > maxItems: 1
> > @@ -124,3 +129,25 @@ examples:
> > snps,priority = <0 1 2 3>;
> > snps,axi-max-burst-len = <16>;
> > };
> > +
> > + - |
>
> For what's just a new compatible and extra reg field, I don't think we
> need another example.
[>>] I would suggest to provide the below example if you don't see any harmful.
>
[>>] The reason is because those compatible and new reg help customer understand the setup
> > + #include <dt-bindings/interrupt-controller/arm-gic.h>
> > + #include <dt-bindings/interrupt-controller/irq.h>
> > + /* example with intel,kmb-axi-dma */
> > + #define KEEM_BAY_PSS_AXI_DMA
> > + #define KEEM_BAY_PSS_APB_AXI_DMA
> > + axi_dma: dma@28000000 {
> > + compatible = "intel,kmb-axi-dma";
> > + reg = <0x28000000 0x1000>, <0x20250000 0x24>;
> > + reg-names = "axidma_ctrl_regs", "axidma_apb_regs";
> > + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-names = "core-clk", "cfgr-clk";
> > + clocks = <&scmi_clk KEEM_BAY_PSS_AXI_DMA>, <&scmi_clk
> KEEM_BAY_PSS_APB_AXI_DMA>;
> > + #dma-cells = <1>;
> > + dma-channels = <8>;
> > + snps,dma-masters = <1>;
> > + snps,data-width = <4>;
> > + snps,priority = <0 0 0 0 0 0 0 0>;
> > + snps,block-size = <1024 1024 1024 1024 1024 1024 1024
> 1024>;
> > + snps,axi-max-burst-len = <16>;
> > + };
> > --
> > 2.18.0
> >
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v5 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (9 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 10/16] dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
` (4 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for Intel KeemBay DMA registers. These registers are required
to run data transfer between device to memory and memory to device on Intel
KeemBay SoC.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 46baf93de617..3a357f7fda02 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -63,6 +63,7 @@ struct axi_dma_chip {
struct device *dev;
int irq;
void __iomem *regs;
+ void __iomem *apb_regs;
struct clk *core_clk;
struct clk *cfgr_clk;
struct dw_axi_dma *dw;
@@ -169,6 +170,19 @@ static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
#define CH_INTSIGNAL_ENA 0x090 /* R/W Chan Interrupt Signal Enable */
#define CH_INTCLEAR 0x098 /* W Chan Interrupt Clear */
+/* These Apb registers are used by Intel KeemBay SoC */
+#define DMAC_APB_CFG 0x000 /* DMAC Apb Configuration Register */
+#define DMAC_APB_STAT 0x004 /* DMAC Apb Status Register */
+#define DMAC_APB_DEBUG_STAT_0 0x008 /* DMAC Apb Debug Status Register 0 */
+#define DMAC_APB_DEBUG_STAT_1 0x00C /* DMAC Apb Debug Status Register 1 */
+#define DMAC_APB_HW_HS_SEL_0 0x010 /* DMAC Apb HW HS register 0 */
+#define DMAC_APB_HW_HS_SEL_1 0x014 /* DMAC Apb HW HS register 1 */
+#define DMAC_APB_LPI 0x018 /* DMAC Apb Low Power Interface Reg */
+#define DMAC_APB_BYTE_WR_CH_EN 0x01C /* DMAC Apb Byte Write Enable */
+#define DMAC_APB_HALFWORD_WR_CH_EN 0x020 /* DMAC Halfword write enables */
+
+#define UNUSED_CHANNEL 0x3F /* Set unused DMA channel to 0x3F */
+#define MAX_BLOCK_SIZE 0x1000 /* 1024 blocks * 4 bytes data width */
/* DMAC_CFG */
#define DMAC_EN_POS 0
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (10 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 11/16] dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
` (3 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for Intel KeemBay AxiDMA to the .compatible field.
The AxiDMA Apb region will be accessible if the compatible string
matches the "intel,kmb-axi-dma".
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 29323e75bc44..8135b827b47a 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -1160,6 +1160,7 @@ static int parse_device_properties(struct axi_dma_chip *chip)
static int dw_probe(struct platform_device *pdev)
{
+ struct device_node *node = pdev->dev.of_node;
struct axi_dma_chip *chip;
struct resource *mem;
struct dw_axi_dma *dw;
@@ -1192,6 +1193,12 @@ static int dw_probe(struct platform_device *pdev)
if (IS_ERR(chip->regs))
return PTR_ERR(chip->regs);
+ if (of_device_is_compatible(node, "intel,kmb-axi-dma")) {
+ chip->apb_regs = devm_platform_ioremap_resource(pdev, 1);
+ if (IS_ERR(chip->apb_regs))
+ return PTR_ERR(chip->apb_regs);
+ }
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
@@ -1336,6 +1343,7 @@ static const struct dev_pm_ops dw_axi_dma_pm_ops = {
static const struct of_device_id dw_dma_of_id_table[] = {
{ .compatible = "snps,axi-dma-1.01a" },
+ { .compatible = "intel,kmb-axi-dma" },
{}
};
MODULE_DEVICE_TABLE(of, dw_dma_of_id_table);
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (11 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 12/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers Sia Jee Heng
` (2 subsequent siblings)
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for Intel KeemBay AxiDMA device handshake programming.
Device handshake number passed in to the AxiDMA shall be written to
the Intel KeemBay AxiDMA hardware handshake registers before DMA
operations are started.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 8135b827b47a..440f9a8b25da 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -445,6 +445,48 @@ static void dma_chan_free_chan_resources(struct dma_chan *dchan)
pm_runtime_put(chan->chip->dev);
}
+static int dw_axi_dma_set_hw_channel(struct axi_dma_chip *chip,
+ u32 handshake_num, bool set)
+{
+ unsigned long start = 0;
+ unsigned long reg_value;
+ unsigned long reg_mask;
+ unsigned long reg_set;
+ unsigned long mask;
+ unsigned long val;
+
+ if (!chip->apb_regs)
+ return -ENODEV;
+
+ /*
+ * An unused DMA channel has a default value of 0x3F.
+ * Lock the DMA channel by assign a handshake number to the channel.
+ * Unlock the DMA channel by assign 0x3F to the channel.
+ */
+ if (set) {
+ reg_set = UNUSED_CHANNEL;
+ val = handshake_num;
+ } else {
+ reg_set = handshake_num;
+ val = UNUSED_CHANNEL;
+ }
+
+ reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+
+ for_each_set_clump8(start, reg_mask, ®_value, 64) {
+ if (reg_mask == reg_set) {
+ mask = GENMASK_ULL(start + 7, start);
+ reg_value &= ~mask;
+ reg_value |= rol64(val, start);
+ lo_hi_writeq(reg_value,
+ chip->apb_regs + DMAC_APB_HW_HS_SEL_0);
+ break;
+ }
+ }
+
+ return 0;
+}
+
/*
* If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI
* as 1, it understands that the current block is the final block in the
@@ -626,6 +668,9 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
llp = hw_desc->llp;
} while (num_periods);
+ if (dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true))
+ goto err_desc_get;
+
return vchan_tx_prep(&chan->vc, &desc->vd, flags);
err_desc_get:
@@ -684,6 +729,9 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
llp = hw_desc->llp;
} while (sg_len);
+ if (dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true))
+ goto err_desc_get;
+
return vchan_tx_prep(&chan->vc, &desc->vd, flags);
err_desc_get:
@@ -959,6 +1007,10 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
+ if (chan->direction != DMA_MEM_TO_MEM)
+ dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+
spin_lock_irqsave(&chan->vc.lock, flags);
vchan_get_all_descriptors(&chan->vc, &head);
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (12 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 13/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list Sia Jee Heng
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for Intel KeemBay AxiDMA BYTE and HALFWORD registers
programming.
Intel KeemBay AxiDMA supports data transfer between device to memory
and memory to device operations.
This code is needed by I2C, I3C, I2S, SPI and UART which uses FIFO
size of 8bits and 16bits to perform memory to device data transfer
operation. 0-padding functionality is provided to avoid
pre-processing of data on CPU.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 44 ++++++++++++++++---
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 440f9a8b25da..dc7ddf98fd04 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -312,7 +312,7 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
struct axi_dma_desc *first)
{
u32 priority = chan->chip->dw->hdata->priority[chan->id];
- u32 reg, irq_mask;
+ u32 reg, irq_mask, reg_width, offset, val;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
if (unlikely(axi_chan_is_hw_enable(chan))) {
@@ -334,6 +334,25 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
DWAXIDMAC_HS_SEL_HW << CH_CFG_H_HS_SEL_SRC_POS);
switch (chan->direction) {
case DMA_MEM_TO_DEV:
+ if (chan->chip->apb_regs) {
+ reg_width = __ffs(chan->config.dst_addr_width);
+ /*
+ * Configure Byte and Halfword register
+ * for MEM_TO_DEV only.
+ */
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val |= BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val |= BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ }
+ }
+
reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
@@ -994,8 +1013,9 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
{
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT;
+ u32 reg_width = __ffs(chan->config.dst_addr_width);
unsigned long flags;
- u32 val;
+ u32 offset, val;
int ret;
LIST_HEAD(head);
@@ -1007,9 +1027,23 @@ static int dma_chan_terminate_all(struct dma_chan *dchan)
dev_warn(dchan2dev(dchan),
"%s failed to stop\n", axi_chan_name(chan));
- if (chan->direction != DMA_MEM_TO_MEM)
- dw_axi_dma_set_hw_channel(chan->chip,
- chan->hw_handshake_num, false);
+ if (chan->direction != DMA_MEM_TO_MEM) {
+ ret = dw_axi_dma_set_hw_channel(chan->chip,
+ chan->hw_handshake_num, false);
+ if (ret == 0 && chan->direction == DMA_MEM_TO_DEV) {
+ if (reg_width == DWAXIDMAC_TRANS_WIDTH_8) {
+ offset = DMAC_APB_BYTE_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val &= ~BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ } else if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) {
+ offset = DMAC_APB_HALFWORD_WR_CH_EN;
+ val = ioread32(chan->chip->apb_regs + offset);
+ val &= ~BIT(chan->id);
+ iowrite32(val, chan->chip->apb_regs + offset);
+ }
+ }
+ }
spin_lock_irqsave(&chan->vc.lock, flags);
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (13 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 14/16] dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD registers Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 2:34 ` [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list Sia Jee Heng
15 siblings, 0 replies; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
Add support for DMA Scatter-Gather (SG) constraint so that DMA clients can
handle the AxiDMA limitation.
Without supporting DMA constraint the default Max segment size reported by
dmaengine is 64KB, which is not supported by Intel KeemBay AxiDMA.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c | 8 ++++++++
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index dc7ddf98fd04..1a218fcdbb16 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -12,6 +12,7 @@
#include <linux/device.h>
#include <linux/dmaengine.h>
#include <linux/dmapool.h>
+#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
@@ -1350,6 +1351,13 @@ static int dw_probe(struct platform_device *pdev)
dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg;
dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic;
+ /*
+ * Synopsis DesignWare AxiDMA datasheet mentioned Maximum
+ * supported blocks is 1024. Device register width is 4 bytes.
+ * Therefore, set constraint to 1024 * 4.
+ */
+ dw->dma.dev->dma_parms = &dw->dma_parms;
+ dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE);
platform_set_drvdata(pdev, chip);
pm_runtime_enable(chip->dev);
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 3a357f7fda02..1e937ea2a96d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -54,6 +54,7 @@ struct axi_dma_chan {
struct dw_axi_dma {
struct dma_device dma;
struct dw_axi_dma_hcfg *hdata;
+ struct device_dma_parameters dma_parms;
/* channels */
struct axi_dma_chan *chan;
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
2020-11-23 2:34 [PATCH v5 00/16] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA Sia Jee Heng
` (14 preceding siblings ...)
2020-11-23 2:34 ` [PATCH v5 15/16] dmaengine: dw-axi-dmac: Set constraint to the Max segment size Sia Jee Heng
@ 2020-11-23 2:34 ` Sia Jee Heng
2020-11-23 10:22 ` Andy Shevchenko
15 siblings, 1 reply; 24+ messages in thread
From: Sia Jee Heng @ 2020-11-23 2:34 UTC (permalink / raw)
To: vkoul, Eugeniy.Paltsev, robh+dt
Cc: andriy.shevchenko, dmaengine, linux-kernel, devicetree
AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
It shall helps the DMA clients to create size-optimized linked-list
for the controller.
However, there are certain situations where DMA client might not be
abled to benefit from the dma_get_max_seg_size() if the segment size
can't meet the nature of the DMA client's operation.
In the case of ALSA operation, ALSA application and driver expecting
to run in a period of larger than 10ms regardless of the bit depth.
With this large period, there is a strong request to split the linked-list
in the AxiDMA driver.
Signed-off-by: Sia Jee Heng <jee.heng.sia@intel.com>
---
.../dma/dw-axi-dmac/dw-axi-dmac-platform.c | 111 ++++++++++++++----
drivers/dma/dw-axi-dmac/dw-axi-dmac.h | 1 +
2 files changed, 92 insertions(+), 20 deletions(-)
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
index 1a218fcdbb16..cfa7256f207d 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
@@ -576,6 +576,11 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+ if (!IS_ALIGNED(mem_addr, 4)) {
+ dev_err(chan->chip->dev, "invalid buffer alignment\n");
+ return -EINVAL;
+ }
+
switch (chan->direction) {
case DMA_MEM_TO_DEV:
reg_width = __ffs(chan->config.dst_addr_width);
@@ -637,6 +642,35 @@ static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan,
return 0;
}
+static size_t calculate_block_len(struct axi_dma_chan *chan,
+ dma_addr_t dma_addr, size_t buf_len,
+ enum dma_transfer_direction direction)
+{
+ u32 data_width, reg_width, mem_width;
+ size_t axi_block_ts, block_len;
+
+ axi_block_ts = chan->chip->dw->hdata->block_size[chan->id];
+
+ switch (direction) {
+ case DMA_MEM_TO_DEV:
+ data_width = BIT(chan->chip->dw->hdata->m_data_width);
+ mem_width = __ffs(data_width | dma_addr | buf_len);
+ if (mem_width > DWAXIDMAC_TRANS_WIDTH_32)
+ mem_width = DWAXIDMAC_TRANS_WIDTH_32;
+
+ block_len = axi_block_ts << mem_width;
+ break;
+ case DMA_DEV_TO_MEM:
+ reg_width = __ffs(chan->config.src_addr_width);
+ block_len = axi_block_ts << reg_width;
+ break;
+ default:
+ block_len = 0;
+ }
+
+ return block_len;
+}
+
static struct dma_async_tx_descriptor *
dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
size_t buf_len, size_t period_len,
@@ -647,13 +681,27 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
struct axi_dma_hw_desc *hw_desc = NULL;
struct axi_dma_desc *desc = NULL;
dma_addr_t src_addr = dma_addr;
- u32 num_periods = buf_len / period_len;
+ u32 num_periods, num_segments;
+ size_t axi_block_len;
+ u32 total_segments;
+ u32 segment_len;
unsigned int i;
int status;
u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
- desc = axi_desc_alloc(num_periods);
+ num_periods = buf_len / period_len;
+
+ axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction);
+ if (axi_block_len == 0)
+ return NULL;
+
+ num_segments = DIV_ROUND_UP(period_len, axi_block_len);
+ segment_len = DIV_ROUND_UP(period_len, num_segments);
+
+ total_segments = num_periods * num_segments;
+
+ desc = axi_desc_alloc(num_periods * num_segments);
if (unlikely(!desc))
goto err_desc_get;
@@ -661,12 +709,13 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
desc->chan = chan;
chan->cyclic = true;
desc->length = 0;
+ desc->period_len = period_len;
- for (i = 0; i < num_periods; i++) {
+ for (i = 0; i < total_segments; i++) {
hw_desc = &desc->hw_desc[i];
status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr,
- period_len);
+ segment_len);
if (status < 0)
goto err_desc_get;
@@ -676,17 +725,17 @@ dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr,
*/
set_desc_last(hw_desc);
- src_addr += period_len;
+ src_addr += segment_len;
}
llp = desc->hw_desc[0].llp;
/* Managed transfer list */
do {
- hw_desc = &desc->hw_desc[--num_periods];
+ hw_desc = &desc->hw_desc[--total_segments];
write_desc_llp(hw_desc, llp | lms);
llp = hw_desc->llp;
- } while (num_periods);
+ } while (total_segments);
if (dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true))
goto err_desc_get;
@@ -709,9 +758,13 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan);
struct axi_dma_hw_desc *hw_desc = NULL;
struct axi_dma_desc *desc = NULL;
+ u32 num_segments, segment_len;
+ unsigned int loop = 0;
struct scatterlist *sg;
+ size_t axi_block_len;
+ u32 len, num_sgs = 0;
unsigned int i;
- u32 mem, len;
+ dma_addr_t mem;
int status;
u64 llp = 0;
u8 lms = 0; /* Select AXI0 master for LLI fetching */
@@ -719,35 +772,51 @@ dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl,
if (unlikely(!is_slave_direction(direction) || !sg_len))
return NULL;
- chan->direction = direction;
+ mem = sg_dma_address(sgl);
+ len = sg_dma_len(sgl);
+
+ axi_block_len = calculate_block_len(chan, mem, len, direction);
+ if (axi_block_len == 0)
+ return NULL;
- desc = axi_desc_alloc(sg_len);
+ for_each_sg(sgl, sg, sg_len, i)
+ num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
+
+ desc = axi_desc_alloc(num_sgs);
if (unlikely(!desc))
goto err_desc_get;
desc->chan = chan;
desc->length = 0;
+ chan->direction = direction;
for_each_sg(sgl, sg, sg_len, i) {
mem = sg_dma_address(sg);
len = sg_dma_len(sg);
- hw_desc = &desc->hw_desc[i];
-
- status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, len);
- if (status < 0)
- goto err_desc_get;
- desc->length += hw_desc->len;
+ num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len);
+ segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments);
+
+ do {
+ hw_desc = &desc->hw_desc[loop++];
+ status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len);
+ if (status < 0)
+ goto err_desc_get;
+
+ desc->length += hw_desc->len;
+ len -= segment_len;
+ mem += segment_len;
+ } while (len >= segment_len);
}
/* Set end-of-link to the last link descriptor of list */
- set_desc_last(&desc->hw_desc[sg_len - 1]);
+ set_desc_last(&desc->hw_desc[num_sgs - 1]);
/* Managed transfer list */
do {
- hw_desc = &desc->hw_desc[--sg_len];
+ hw_desc = &desc->hw_desc[--num_sgs];
write_desc_llp(hw_desc, llp | lms);
llp = hw_desc->llp;
- } while (sg_len);
+ } while (num_sgs);
if (dw_axi_dma_set_hw_channel(chan->chip, chan->hw_handshake_num, true))
goto err_desc_get;
@@ -950,7 +1019,6 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
vd = vchan_next_desc(&chan->vc);
if (chan->cyclic) {
- vchan_cyclic_callback(vd);
desc = vd_to_axi_desc(vd);
if (desc) {
llp = lo_hi_readq(chan->chan_regs + CH_LLP);
@@ -960,6 +1028,9 @@ static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan)
axi_chan_irq_clear(chan, hw_desc->lli->status_lo);
hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID;
desc->completed_blocks = i;
+
+ if (((hw_desc->len * (i + 1)) % desc->period_len) == 0)
+ vchan_cyclic_callback(vd);
break;
}
}
diff --git a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
index 1e937ea2a96d..b69897887c76 100644
--- a/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
+++ b/drivers/dma/dw-axi-dmac/dw-axi-dmac.h
@@ -100,6 +100,7 @@ struct axi_dma_desc {
struct axi_dma_chan *chan;
u32 completed_blocks;
u32 length;
+ u32 period_len;
};
static inline struct device *dchan2dev(struct dma_chan *dchan)
--
2.18.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
2020-11-23 2:34 ` [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list Sia Jee Heng
@ 2020-11-23 10:22 ` Andy Shevchenko
2020-12-09 1:47 ` Sia, Jee Heng
0 siblings, 1 reply; 24+ messages in thread
From: Andy Shevchenko @ 2020-11-23 10:22 UTC (permalink / raw)
To: Sia Jee Heng
Cc: vkoul, Eugeniy.Paltsev, robh+dt, dmaengine, linux-kernel, devicetree
On Mon, Nov 23, 2020 at 10:34:52AM +0800, Sia Jee Heng wrote:
> AxiDMA driver exposed the dma_set_max_seg_size() to the DMAENGINE.
> It shall helps the DMA clients to create size-optimized linked-list
> for the controller.
>
> However, there are certain situations where DMA client might not be
> abled to benefit from the dma_get_max_seg_size() if the segment size
> can't meet the nature of the DMA client's operation.
>
> In the case of ALSA operation, ALSA application and driver expecting
> to run in a period of larger than 10ms regardless of the bit depth.
> With this large period, there is a strong request to split the linked-list
> in the AxiDMA driver.
I'm wondering why ASoC generic code can't use DMA channel and device
capabilities and prepare SG list with all limitations taken into account.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 24+ messages in thread
* RE: [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split the linked-list
2020-11-23 10:22 ` Andy Shevchenko
@ 2020-12-09 1:47 ` Sia, Jee Heng
0 siblings, 0 replies; 24+ messages in thread
From: Sia, Jee Heng @ 2020-12-09 1:47 UTC (permalink / raw)
To: Andy Shevchenko
Cc: vkoul, Eugeniy.Paltsev, robh+dt, dmaengine, linux-kernel, devicetree
> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: 23 November 2020 6:23 PM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: vkoul@kernel.org; Eugeniy.Paltsev@synopsys.com;
> robh+dt@kernel.org; dmaengine@vger.kernel.org; linux-
> kernel@vger.kernel.org; devicetree@vger.kernel.org
> Subject: Re: [PATCH v5 16/16] dmaengine: dw-axi-dmac: Virtually split
> the linked-list
>
> On Mon, Nov 23, 2020 at 10:34:52AM +0800, Sia Jee Heng wrote:
> > AxiDMA driver exposed the dma_set_max_seg_size() to the
> DMAENGINE.
> > It shall helps the DMA clients to create size-optimized linked-list
> > for the controller.
> >
> > However, there are certain situations where DMA client might not be
> > abled to benefit from the dma_get_max_seg_size() if the segment
> size
> > can't meet the nature of the DMA client's operation.
> >
> > In the case of ALSA operation, ALSA application and driver expecting
> > to run in a period of larger than 10ms regardless of the bit depth.
> > With this large period, there is a strong request to split the
> > linked-list in the AxiDMA driver.
>
> I'm wondering why ASoC generic code can't use DMA channel and
> device capabilities and prepare SG list with all limitations taken into
> account.
[>>] There is no further comment to split the linked-list in DMA, I assume we can proceed with this patch.
[>>] The RFC patch is submitted at below link and you are in the thread.
[>>] https://lore.kernel.org/alsa-devel/CO1PR11MB5026545F07968DBC5386CF45DACD0@CO1PR11MB5026.namprd11.prod.outlook.com/T/#u
>
>
> --
> With Best Regards,
> Andy Shevchenko
>
^ permalink raw reply [flat|nested] 24+ messages in thread