* [PATCH v5 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings
2021-02-10 9:19 [PATCH v5 0/3] Adding the Sparx5 Switch Reset Driver Steen Hegelund
@ 2021-02-10 9:19 ` Steen Hegelund
2021-02-15 17:32 ` Alexandre Belloni
2021-02-10 9:19 ` [PATCH v5 2/3] reset: mchp: sparx5: add switch reset driver Steen Hegelund
2021-02-10 9:19 ` [PATCH v5 3/3] arm64: dts: reset: add microchip sparx5 " Steen Hegelund
2 siblings, 1 reply; 6+ messages in thread
From: Steen Hegelund @ 2021-02-10 9:19 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring
Cc: Steen Hegelund, Andrew Lunn, Microchip Linux Driver Support,
Alexandre Belloni, Gregory Clement, linux-kernel,
linux-arm-kernel, devicetree
Document the Sparx5 reset device driver bindings
The driver uses two IO ranges on sparx5 for access to
the reset control and the reset status.
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
.../bindings/reset/microchip,rst.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/microchip,rst.yaml
diff --git a/Documentation/devicetree/bindings/reset/microchip,rst.yaml b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
new file mode 100644
index 000000000000..80046172c9f8
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/microchip,rst.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/microchip,rst.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microchip Sparx5 Switch Reset Controller
+
+maintainers:
+ - Steen Hegelund <steen.hegelund@microchip.com>
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+description: |
+ The Microchip Sparx5 Switch provides reset control and implements the following
+ functions
+ - One Time Switch Core Reset (Soft Reset)
+
+properties:
+ $nodename:
+ pattern: "^reset-controller@[0-9a-f]+$"
+
+ compatible:
+ const: microchip,sparx5-switch-reset
+
+ reg:
+ items:
+ - description: cpu block registers
+ - description: global control block registers
+
+ reg-names:
+ items:
+ - const: cpu
+ - const: gcb
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@0 {
+ compatible = "microchip,sparx5-switch-reset";
+ #reset-cells = <1>;
+ reg = <0x0 0xd0>,
+ <0x11010000 0x10000>;
+ reg-names = "cpu", "gcb";
+ };
+
--
2.30.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v5 2/3] reset: mchp: sparx5: add switch reset driver
2021-02-10 9:19 [PATCH v5 0/3] Adding the Sparx5 Switch Reset Driver Steen Hegelund
2021-02-10 9:19 ` [PATCH v5 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings Steen Hegelund
@ 2021-02-10 9:19 ` Steen Hegelund
2021-02-10 9:19 ` [PATCH v5 3/3] arm64: dts: reset: add microchip sparx5 " Steen Hegelund
2 siblings, 0 replies; 6+ messages in thread
From: Steen Hegelund @ 2021-02-10 9:19 UTC (permalink / raw)
To: Philipp Zabel
Cc: Steen Hegelund, Andrew Lunn, Microchip Linux Driver Support,
Alexandre Belloni, Gregory Clement, linux-kernel,
linux-arm-kernel
The Sparx5 Switch SoC has a number of components that can be reset
indiviually, but at least the Switch Core needs to be in a well defined
state at power on, when any of the Sparx5 drivers starts to access the
Switch Core, this reset driver is available.
The reset driver is loaded early via the postcore_initcall interface, and
will then be available for the other Sparx5 drivers (SGPIO, SwitchDev etc)
that are loaded next, and the first of them to be loaded can perform the
one-time Switch Core reset that is needed.
The driver has protection so that the system busses, DDR controller, PCI-E
and ARM A53 CPU and a few other subsystems are not touched by the reset.
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
drivers/reset/Kconfig | 8 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-microchip-sparx5.c | 130 +++++++++++++++++++++++++
3 files changed, 139 insertions(+)
create mode 100644 drivers/reset/reset-microchip-sparx5.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 71ab75a46491..05c240c47a8a 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -101,6 +101,14 @@ config RESET_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
+config RESET_MCHP_SPARX5
+ bool "Microchip Sparx5 reset driver"
+ depends on HAS_IOMEM || COMPILE_TEST
+ default y if SPARX5_SWITCH
+ select MFD_SYSCON
+ help
+ This driver supports switch core reset for the Microchip Sparx5 SoC.
+
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 1054123fd187..341fd9ab4bf6 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
+obj-$(CONFIG_RESET_MCHP_SPARX5) += reset-microchip-sparx5.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c
new file mode 100644
index 000000000000..b243a12af085
--- /dev/null
+++ b/drivers/reset/reset-microchip-sparx5.c
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip Sparx5 Switch Reset driver
+ *
+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
+ *
+ * The Sparx5 Chip Register Model can be browsed at this location:
+ * https://github.com/microchip-ung/sparx-5_reginfo
+ */
+#include <linux/mfd/syscon.h>
+#include <linux/of_device.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+#define PROTECT_REG 0x84
+#define PROTECT_BIT BIT(10)
+#define SOFT_RESET_REG 0x08
+#define SOFT_RESET_BIT BIT(1)
+
+struct mchp_reset_context {
+ struct regmap *cpu_ctrl;
+ struct regmap *gcb_ctrl;
+ struct reset_controller_dev rcdev;
+};
+
+static struct regmap_config sparx5_reset_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+
+static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct mchp_reset_context *ctx =
+ container_of(rcdev, struct mchp_reset_context, rcdev);
+ u32 val;
+
+ /* Make sure the core is PROTECTED from reset */
+ regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT);
+
+ /* Start soft reset */
+ regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
+
+ /* Wait for soft reset done */
+ return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
+ (val & SOFT_RESET_BIT) == 0,
+ 1, 100);
+}
+
+static const struct reset_control_ops sparx5_reset_ops = {
+ .reset = sparx5_switch_reset,
+};
+
+static int mchp_sparx5_map_io(struct platform_device *pdev, char *name,
+ struct regmap **target)
+{
+ struct resource *res;
+ void __iomem *mem;
+ struct regmap *map;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
+ if (!res) {
+ dev_err(&pdev->dev, "No '%s' resource\n", name);
+ return -ENODEV;
+ }
+ mem = devm_ioremap(&pdev->dev, res->start, res->end - res->start + 1);
+ if (!mem) {
+ dev_err(&pdev->dev, "Could not map '%s' resource\n", name);
+ return -ENXIO;
+ }
+ sparx5_reset_regmap_config.name = res->name;
+ map = devm_regmap_init_mmio(&pdev->dev, mem, &sparx5_reset_regmap_config);
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+ *target = map;
+ return 0;
+}
+
+static int mchp_sparx5_reset_probe(struct platform_device *pdev)
+{
+ struct device_node *dn = pdev->dev.of_node;
+ struct mchp_reset_context *ctx;
+ int err;
+
+ ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx)
+ return -ENOMEM;
+
+ err = mchp_sparx5_map_io(pdev, "cpu", &ctx->cpu_ctrl);
+ if (err)
+ return err;
+ err = mchp_sparx5_map_io(pdev, "gcb", &ctx->gcb_ctrl);
+ if (err)
+ return err;
+
+ ctx->rcdev.owner = THIS_MODULE;
+ ctx->rcdev.nr_resets = 1;
+ ctx->rcdev.ops = &sparx5_reset_ops;
+ ctx->rcdev.of_node = dn;
+
+ return devm_reset_controller_register(&pdev->dev, &ctx->rcdev);
+}
+
+static const struct of_device_id mchp_sparx5_reset_of_match[] = {
+ {
+ .compatible = "microchip,sparx5-switch-reset",
+ },
+ { /*sentinel*/ }
+};
+
+static struct platform_driver mchp_sparx5_reset_driver = {
+ .probe = mchp_sparx5_reset_probe,
+ .driver = {
+ .name = "sparx5-switch-reset",
+ .of_match_table = mchp_sparx5_reset_of_match,
+ },
+};
+
+static int __init mchp_sparx5_reset_init(void)
+{
+ return platform_driver_register(&mchp_sparx5_reset_driver);
+}
+
+postcore_initcall(mchp_sparx5_reset_init);
+
+MODULE_DESCRIPTION("Microchip Sparx5 switch reset driver");
+MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
+MODULE_LICENSE("Dual MIT/GPL");
--
2.30.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v5 3/3] arm64: dts: reset: add microchip sparx5 switch reset driver
2021-02-10 9:19 [PATCH v5 0/3] Adding the Sparx5 Switch Reset Driver Steen Hegelund
2021-02-10 9:19 ` [PATCH v5 1/3] dt-bindings: reset: microchip sparx5 reset driver bindings Steen Hegelund
2021-02-10 9:19 ` [PATCH v5 2/3] reset: mchp: sparx5: add switch reset driver Steen Hegelund
@ 2021-02-10 9:19 ` Steen Hegelund
2 siblings, 0 replies; 6+ messages in thread
From: Steen Hegelund @ 2021-02-10 9:19 UTC (permalink / raw)
To: Philipp Zabel, Rob Herring
Cc: Steen Hegelund, Andrew Lunn, Microchip Linux Driver Support,
Alexandre Belloni, Gregory Clement, linux-kernel,
linux-arm-kernel, devicetree
This provides reset driver support for the Microchip Sparx5 PCB134 and
PCB135 reference boards.
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 380281f312d8..06ecaa9ac8aa 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -132,9 +132,12 @@ mux: mux-controller {
};
};
- reset@611010008 {
- compatible = "microchip,sparx5-chip-reset";
- reg = <0x6 0x11010008 0x4>;
+ reset: reset-controller@0 {
+ compatible = "microchip,sparx5-switch-reset";
+ reg = <0x6 0x00000000 0xd0>,
+ <0x6 0x11010000 0x10000>;
+ reg-names = "cpu", "gcb";
+ #reset-cells = <1>;
};
uart0: serial@600100000 {
--
2.30.0
^ permalink raw reply related [flat|nested] 6+ messages in thread