From: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
To: mturquette@baylibre.com, sboyd@kernel.org, linux-clk@vger.kernel.org
Cc: narmstrong@baylibre.com, jbrunet@baylibre.com,
khilman@baylibre.com, linux-kernel@vger.kernel.org,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Subject: [PATCH v3 0/3] clk: meson: rounding for fast clocks on 32-bit SoCs
Date: Mon, 28 Jun 2021 00:39:56 +0200 [thread overview]
Message-ID: <20210627223959.188139-1-martin.blumenstingl@googlemail.com> (raw)
On the 32-bit Amlogic Meson8/8b/8m2 SoCs we run into a problem with the
fast HDMI PLL and it's OD (post-dividers). This clock tree can run at
up to approx. 3GHz.
This however causes a problem, because these rates require BIT(31) to
be usable. Unfortunately this is not the case with clk_ops.round_rate
on 32-bit systems. BIT(31) is reserved for the sign (+ or -).
clk_ops.determine_rate does not suffer from this limitation. It uses
an int to signal any errors and can then take all available 32 bits for
the clock rate.
Changes since v1 from [0]:
- reworked the first patch so the the existing
divider_{ro_}round_rate_parent implementations are using the new
divider_{ro_}determine_rate implementations to avoid code duplication
(thanks Jerome for the suggestion)
- added a patch to switch the default clk_divider_{ro_}ops to use
.determine_rate instead of .round_rate as suggested by Jerome
(thanks)
- dropped a patch for the Meson PLL ops as these are independent from
the divider patches and Jerome has applied that one directly (thanks)
- added Jerome's Reviewed-by to the meson clk-regmap patch (thanks!)
- dropped the RFC prefix
Changes since v2 from [1]:
- Added Jerome's Reviewed-by to patches 1 and 2 (thank you!)
- fixed typo in the cover letter (availble -> available)
[0] https://patchwork.kernel.org/project/linux-clk/cover/20210517203724.1006254-1-martin.blumenstingl@googlemail.com/
[1] https://patchwork.kernel.org/project/linux-clk/cover/20210524103733.554878-1-martin.blumenstingl@googlemail.com/
Martin Blumenstingl (3):
clk: divider: Add re-usable determine_rate implementations
clk: divider: Switch from .round_rate to .determine_rate by default
clk: meson: regmap: switch to determine_rate for the dividers
drivers/clk/clk-divider.c | 93 +++++++++++++++++++++++++---------
drivers/clk/meson/clk-regmap.c | 19 ++++---
include/linux/clk-provider.h | 6 +++
3 files changed, 85 insertions(+), 33 deletions(-)
--
2.32.0
next reply other threads:[~2021-06-27 22:40 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-27 22:39 Martin Blumenstingl [this message]
2021-06-27 22:39 ` [PATCH v3 1/3] clk: divider: Add re-usable determine_rate implementations Martin Blumenstingl
2021-06-30 18:39 ` Stephen Boyd
2021-06-27 22:39 ` [PATCH v3 2/3] clk: divider: Switch from .round_rate to .determine_rate by default Martin Blumenstingl
2021-06-30 18:39 ` Stephen Boyd
2021-07-01 20:25 ` Guenter Roeck
2021-07-01 20:57 ` Martin Blumenstingl
2021-07-01 21:43 ` Guenter Roeck
2021-07-02 0:53 ` Stephen Boyd
2021-07-02 1:02 ` Stephen Boyd
2021-07-02 9:19 ` Martin Blumenstingl
[not found] ` <CGME20210702124612eucas1p1762911deb37e4fb03adc9239bb715135@eucas1p1.samsung.com>
2021-07-02 12:46 ` Marek Szyprowski
2021-07-02 21:00 ` Stephen Boyd
2021-07-02 20:59 ` Stephen Boyd
2021-07-02 22:57 ` Martin Blumenstingl
2021-07-02 1:04 ` Stephen Boyd
2021-06-27 22:39 ` [PATCH v3 3/3] clk: meson: regmap: switch to determine_rate for the dividers Martin Blumenstingl
2021-06-30 18:39 ` Stephen Boyd
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