From: Dmitry Osipenko <digetx@gmail.com>
To: "Thierry Reding" <thierry.reding@gmail.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Ulf Hansson" <ulf.hansson@linaro.org>,
"Viresh Kumar" <vireshk@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Peter De Schrijver" <pdeschrijver@nvidia.com>,
"Mikko Perttunen" <mperttunen@nvidia.com>,
"Peter Chen" <peter.chen@kernel.org>,
"Lee Jones" <lee.jones@linaro.org>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Nishanth Menon" <nm@ti.com>,
"Adrian Hunter" <adrian.hunter@intel.com>,
"Michael Turquette" <mturquette@baylibre.com>
Cc: linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-pm@vger.kernel.org, linux-usb@vger.kernel.org,
linux-staging@lists.linux.dev, linux-pwm@vger.kernel.org,
linux-mmc@vger.kernel.org, dri-devel@lists.freedesktop.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
Mark Brown <broonie@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>,
Richard Weinberger <richard@nod.at>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Lucas Stach <dev@lynxeye.de>, Stefan Agner <stefan@agner.ch>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
David Heidelberg <david@ixit.cz>
Subject: [PATCH v13 11/35] drm/tegra: dc: Support OPP and SoC core voltage scaling
Date: Mon, 27 Sep 2021 01:40:34 +0300 [thread overview]
Message-ID: <20210926224058.1252-12-digetx@gmail.com> (raw)
In-Reply-To: <20210926224058.1252-1-digetx@gmail.com>
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Tested-by: Peter Geis <pgwipeout@gmail.com> # Ouya T30
Tested-by: Paul Fertser <fercerpav@gmail.com> # PAZ00 T20
Tested-by: Nicolas Chauvet <kwizart@gmail.com> # PAZ00 T20 and TK1 T124
Tested-by: Matt Merhar <mattmerhar@protonmail.com> # Ouya T30
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/gpu/drm/tegra/dc.c | 74 ++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/tegra/dc.h | 2 ++
2 files changed, 76 insertions(+)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index a29d64f87563..d4047a14e2b6 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -11,9 +11,12 @@
#include <linux/interconnect.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
+#include <soc/tegra/common.h>
#include <soc/tegra/pmc.h>
#include <drm/drm_atomic.h>
@@ -1762,6 +1765,47 @@ int tegra_dc_state_setup_clock(struct tegra_dc *dc,
return 0;
}
+static void tegra_dc_update_voltage_state(struct tegra_dc *dc,
+ struct tegra_dc_state *state)
+{
+ unsigned long rate, pstate;
+ struct dev_pm_opp *opp;
+ int err;
+
+ if (!dc->has_opp_table)
+ return;
+
+ /* calculate actual pixel clock rate which depends on internal divider */
+ rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2);
+
+ /* find suitable OPP for the rate */
+ opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate);
+
+ if (opp == ERR_PTR(-ERANGE))
+ opp = dev_pm_opp_find_freq_floor(dc->dev, &rate);
+
+ if (IS_ERR(opp)) {
+ dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n",
+ rate, opp);
+ return;
+ }
+
+ pstate = dev_pm_opp_get_required_pstate(opp, 0);
+ dev_pm_opp_put(opp);
+
+ /*
+ * The minimum core voltage depends on the pixel clock rate (which
+ * depends on internal clock divider of the CRTC) and not on the
+ * rate of the display controller clock. This is why we're not using
+ * dev_pm_opp_set_rate() API and instead controlling the power domain
+ * directly.
+ */
+ err = dev_pm_genpd_set_performance_state(dc->dev, pstate);
+ if (err)
+ dev_err(dc->dev, "failed to set power domain state to %lu: %d\n",
+ pstate, err);
+}
+
static void tegra_dc_commit_state(struct tegra_dc *dc,
struct tegra_dc_state *state)
{
@@ -1801,6 +1845,8 @@ static void tegra_dc_commit_state(struct tegra_dc *dc,
value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1;
tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
}
+
+ tegra_dc_update_voltage_state(dc, state);
}
static void tegra_dc_stop(struct tegra_dc *dc)
@@ -1991,6 +2037,13 @@ static void tegra_crtc_atomic_disable(struct drm_crtc *crtc,
err = host1x_client_suspend(&dc->client);
if (err < 0)
dev_err(dc->dev, "failed to suspend: %d\n", err);
+
+ if (dc->has_opp_table) {
+ err = dev_pm_genpd_set_performance_state(dc->dev, 0);
+ if (err)
+ dev_err(dc->dev,
+ "failed to clear power domain state: %d\n", err);
+ }
}
static void tegra_crtc_atomic_enable(struct drm_crtc *crtc,
@@ -2973,6 +3026,23 @@ static int tegra_dc_couple(struct tegra_dc *dc)
return 0;
}
+static int tegra_dc_init_opp_table(struct tegra_dc *dc)
+{
+ struct tegra_core_opp_params opp_params = {};
+ int err;
+
+ err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params);
+ if (err && err != -ENODEV)
+ return err;
+
+ if (err)
+ dc->has_opp_table = false;
+ else
+ dc->has_opp_table = true;
+
+ return 0;
+}
+
static int tegra_dc_probe(struct platform_device *pdev)
{
u64 dma_mask = dma_get_mask(pdev->dev.parent);
@@ -3038,6 +3108,10 @@ static int tegra_dc_probe(struct platform_device *pdev)
tegra_powergate_power_off(dc->powergate);
}
+ err = tegra_dc_init_opp_table(dc);
+ if (err < 0)
+ return err;
+
dc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(dc->regs))
return PTR_ERR(dc->regs);
diff --git a/drivers/gpu/drm/tegra/dc.h b/drivers/gpu/drm/tegra/dc.h
index 40378308d527..871cfb0cd31c 100644
--- a/drivers/gpu/drm/tegra/dc.h
+++ b/drivers/gpu/drm/tegra/dc.h
@@ -100,6 +100,8 @@ struct tegra_dc {
struct drm_info_list *debugfs_files;
const struct tegra_dc_soc_info *soc;
+
+ bool has_opp_table;
};
static inline struct tegra_dc *
--
2.32.0
next prev parent reply other threads:[~2021-09-26 22:44 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-26 22:40 [PATCH v13 00/35] NVIDIA Tegra power management patches for 5.16 Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 01/35] opp: Change type of dev_pm_opp_attach_genpd(names) argument Dmitry Osipenko
2021-10-04 9:11 ` Viresh Kumar
2021-09-26 22:40 ` [PATCH v13 02/35] soc/tegra: Add devm_tegra_core_dev_init_opp_table_common() Dmitry Osipenko
2021-10-01 12:50 ` Ulf Hansson
2021-10-01 19:15 ` Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 03/35] soc/tegra: pmc: Disable PMC state syncing Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 04/35] soc/tegra: Don't print error message when OPPs not available Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 05/35] dt-bindings: clock: tegra-car: Document new clock sub-nodes Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 06/35] clk: tegra: Support runtime PM and power domain Dmitry Osipenko
2021-10-01 12:32 ` Ulf Hansson
2021-10-01 19:50 ` Dmitry Osipenko
2021-10-02 20:44 ` Dmitry Osipenko
2021-10-05 13:10 ` Ulf Hansson
2021-10-05 22:19 ` Dmitry Osipenko
2021-10-05 22:43 ` Dmitry Osipenko
2021-10-06 2:40 ` Dmitry Osipenko
2021-10-06 12:43 ` Ulf Hansson
2021-10-06 21:14 ` Dmitry Osipenko
2021-10-06 22:01 ` Dmitry Osipenko
2021-10-06 23:21 ` Dmitry Osipenko
2021-10-07 9:18 ` Ulf Hansson
2021-10-07 10:36 ` Dmitry Osipenko
2021-10-06 12:38 ` Ulf Hansson
2021-10-06 21:20 ` Dmitry Osipenko
2021-10-06 21:25 ` Dmitry Osipenko
2021-10-06 22:03 ` Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 07/35] dt-bindings: host1x: Document OPP and power domain properties Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 08/35] dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 09/35] gpu: host1x: Add runtime PM and OPP support Dmitry Osipenko
2021-10-01 13:24 ` Ulf Hansson
2021-09-26 22:40 ` [PATCH v13 10/35] gpu: host1x: Add host1x_channel_stop() Dmitry Osipenko
2021-09-26 22:40 ` Dmitry Osipenko [this message]
2021-10-01 13:27 ` [PATCH v13 11/35] drm/tegra: dc: Support OPP and SoC core voltage scaling Ulf Hansson
2021-10-16 15:36 ` Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 12/35] drm/tegra: hdmi: Add OPP support Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 13/35] drm/tegra: gr2d: Support generic power domain and runtime PM Dmitry Osipenko
2021-10-01 13:39 ` Ulf Hansson
2021-10-01 14:29 ` Dmitry Osipenko
2021-10-01 14:55 ` Ulf Hansson
2021-10-01 19:00 ` Dmitry Osipenko
2021-10-04 11:01 ` Ulf Hansson
2021-10-04 15:57 ` Dmitry Osipenko
2021-10-05 8:45 ` Ulf Hansson
2021-10-05 17:16 ` Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 14/35] drm/tegra: gr3d: " Dmitry Osipenko
2021-10-01 14:06 ` Ulf Hansson
2021-10-01 21:25 ` Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 15/35] drm/tegra: vic: Support system suspend Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 16/35] usb: chipidea: tegra: Add runtime PM and OPP support Dmitry Osipenko
2021-09-30 0:40 ` Dmitry Osipenko
2021-09-30 14:06 ` Peter Chen
2021-09-30 14:08 ` Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 17/35] bus: tegra-gmi: " Dmitry Osipenko
2021-10-01 14:18 ` Ulf Hansson
2021-09-26 22:40 ` [PATCH v13 18/35] pwm: tegra: " Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 19/35] mmc: sdhci-tegra: " Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 20/35] mtd: rawnand: tegra: " Dmitry Osipenko
2021-10-01 14:24 ` Ulf Hansson
2021-10-01 14:35 ` Dmitry Osipenko
2021-10-01 15:01 ` Ulf Hansson
2021-10-17 8:38 ` Dmitry Osipenko
2021-10-19 11:40 ` Ulf Hansson
2021-09-26 22:40 ` [PATCH v13 21/35] spi: tegra20-slink: Add " Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 22/35] media: dt: bindings: tegra-vde: Convert to schema Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 23/35] media: dt: bindings: tegra-vde: Document OPP and power domain Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 24/35] media: staging: tegra-vde: Support generic " Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 25/35] soc/tegra: fuse: Reset hardware Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 26/35] soc/tegra: fuse: Use resource-managed helpers Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 27/35] soc/tegra: regulators: Prepare for suspend Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 28/35] soc/tegra: pmc: Rename 3d power domains Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 29/35] soc/tegra: pmc: Rename core power domain Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 30/35] soc/tegra: pmc: Enable core domain support for Tegra20 and Tegra30 Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 31/35] ARM: tegra: Add OPP tables and power domains to Tegra20 device-trees Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 32/35] ARM: tegra: Add OPP tables and power domains to Tegra30 device-trees Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 33/35] ARM: tegra: Add Memory Client resets to Tegra20 GR2D, GR3D and Host1x Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 34/35] ARM: tegra: Add Memory Client resets to Tegra30 " Dmitry Osipenko
2021-09-26 22:40 ` [PATCH v13 35/35] ARM: tegra20/30: Disable unused host1x hardware Dmitry Osipenko
2021-10-01 14:36 ` [PATCH v13 00/35] NVIDIA Tegra power management patches for 5.16 Ulf Hansson
2021-10-01 14:40 ` Dmitry Osipenko
2021-10-01 15:02 ` Ulf Hansson
2021-10-04 9:11 ` Viresh Kumar
2021-10-04 14:52 ` Dmitry Osipenko
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