From: matthew.gerlach@linux.intel.com
To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
andriy.shevchenko@linux.intel.com,
niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de
Cc: Matthew Gerlach <matthew.gerlach@intel.com>
Subject: [PATCH v2 0/6] Enhance definition of DFH and use enhancements for uart driver
Date: Fri, 23 Sep 2022 05:17:39 -0700 [thread overview]
Message-ID: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> (raw)
From: Matthew Gerlach <matthew.gerlach@intel.com>
This patchset enhances the definition of the Device Feature Header (DFH) used by
the Device Feature List (DFL) bus and then uses the new enhancements in a uart
driver.
Patch 1 updates the DFL documentation to provide the motivation behind the
enhancements to the definition of the DFH.
Patch 2 moves some of the DFH definitions to include/linux/dfl.h so that
they can be accessed by drivers outside of drivers/fpga.
Patch 3 adds the definitions for DFHv1.
Patch 4 defines and uses a DFHv1 parameter to provide a generic mechanism for
describing MSIX interrupts used by a particular feature instance.
Patch 5 gets the location and size of the feature's register set from DFHv1.
Patch 6 adds a DFL uart driver that makes use of the new features of DFHv1.
Basheer Ahmed Muddebihal (2):
fpga: dfl: Move the DFH definitions
fpga: dfl: Add DFHv1 Register Definitions
Matthew Gerlach (4):
Documentation: fpga: dfl: Add documentation for DFHv1
fpga: dfl: add generic support for MSIX interrupts
fpga: dfl: parse the location of the feature's registers from DFHv1
tty: serial: 8250: add DFL bus driver for Altera 16550.
Documentation/fpga/dfl.rst | 49 ++++++++
drivers/fpga/dfl-afu-main.c | 4 +-
drivers/fpga/dfl.c | 88 ++++++++++++--
drivers/fpga/dfl.h | 24 +---
drivers/tty/serial/8250/8250_dfl.c | 177 +++++++++++++++++++++++++++++
drivers/tty/serial/8250/Kconfig | 9 ++
drivers/tty/serial/8250/Makefile | 1 +
include/linux/dfl.h | 79 ++++++++++++-
8 files changed, 402 insertions(+), 29 deletions(-)
create mode 100644 drivers/tty/serial/8250/8250_dfl.c
--
2.25.1
next reply other threads:[~2022-09-23 12:22 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 12:17 matthew.gerlach [this message]
2022-09-23 12:17 ` [PATCH v2 1/6] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-09-23 14:34 ` Ilpo Järvinen
2022-09-23 14:40 ` Ilpo Järvinen
2022-09-27 12:38 ` matthew.gerlach
2022-09-27 12:54 ` Ilpo Järvinen
2022-09-24 8:29 ` Bagas Sanjaya
2022-09-23 12:17 ` [PATCH v2 2/6] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-24 13:00 ` Tom Rix
2022-09-30 5:01 ` Xu Yilun
2022-09-30 14:09 ` matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 3/6] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 4/6] fpga: dfl: add generic support for MSIX interrupts matthew.gerlach
2022-09-23 14:16 ` Ilpo Järvinen
2022-09-26 14:47 ` matthew.gerlach
2022-09-27 6:46 ` Ilpo Järvinen
2022-09-27 12:17 ` matthew.gerlach
2022-09-23 15:21 ` Andy Shevchenko
2022-09-26 15:13 ` matthew.gerlach
2022-09-30 3:28 ` Xu Yilun
2022-10-01 14:50 ` matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 5/6] fpga: dfl: parse the location of the feature's registers from DFHv1 matthew.gerlach
2022-09-23 14:55 ` Ilpo Järvinen
2022-09-23 17:06 ` Muddebihal, Basheer Ahmed
2022-09-30 5:57 ` Xu Yilun
2022-09-23 12:17 ` [PATCH v2 6/6] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-23 15:22 ` Andy Shevchenko
2022-09-23 15:34 ` Ilpo Järvinen
2022-09-30 6:07 ` Xu Yilun
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