From: matthew.gerlach@linux.intel.com
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
tianfei.zhang@intel.com, corbet@lwn.net,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
jirislaby@kernel.org, geert+renesas@glider.be,
niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de
Subject: Re: [PATCH v2 4/6] fpga: dfl: add generic support for MSIX interrupts
Date: Mon, 26 Sep 2022 08:13:10 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.22.394.2209260804500.363733@rhweight-WRK1> (raw)
In-Reply-To: <Yy3O5OeDjJ99g/M2@smile.fi.intel.com>
On Fri, 23 Sep 2022, Andy Shevchenko wrote:
> On Fri, Sep 23, 2022 at 05:17:43AM -0700, matthew.gerlach@linux.intel.com wrote:
>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>
>> Define and use a DFHv1 parameter to add generic support for MSIX
>> interrupts for DFL devices.
>
> ...
>
>> + if (fid != FEATURE_ID_AFU && fid != PORT_FEATURE_ID_ERROR &&
>> + fid != PORT_FEATURE_ID_UINT && fid != FME_FEATURE_ID_GLOBAL_ERR) {
>
>> +
>
> Unneeded blank line.
I will remove the blank line.
>
>> + v = FIELD_GET(DFH_VERSION, readq(base));
>> + switch (v) {
>
> This v...
>
>> + case 0:
>> + break;
>> +
>> + case 1:
>> + v = readq(base + DFHv1_CSR_SIZE_GRP);
>
> Extra space.
>
> ...and this v are semantically different. It's quite hard to deduce their
> semantics.
I was trying to be consistent with the existing code where the read was
stored in a temporary variable, v, and the FIELD_GET would be used for the
specific field. Will it be sufficiently clear if the v used above is
changed to dfl_ver, and this use of v followed by FIELD_GET remains as is?
>
>> + if (FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, v)) {
>> + off = dfl_find_param(base + DFHv1_PARAM_HDR, ofst,
>> + DFHv1_PARAM_ID_MSIX);
>
> I guess I have suggested to use temporary variable(s) here.
>
> void __iomem *dfhv1 = base + DFHv1...;
> void __iomem *nth;
>
>> + if (off >= 0) {
>
> nth = dfhv1 + off;
>
>> + ibase = readl(base + DFHv1_PARAM_HDR +
>> + off + DFHv1_PARAM_MSIX_STARTV);
>> + inr = readl(base + DFHv1_PARAM_HDR +
>> + off + DFHv1_PARAM_MSIX_NUMV);
>
> ibase = readl(nth + DFHv1_PARAM_MSIX_STARTV);
> inr = readl(nth + DFHv1_PARAM_MSIX_NUMV);
>
>> + dev_dbg(binfo->dev, "start %d num %d fid 0x%x\n",
>> + ibase, inr, fid);
>> + }
>> + }
>> + break;
>> +
>> + default:
>> + dev_warn(binfo->dev, "unexpected DFH version %lld\n", v);
>> + break;
>> + }
>> + }
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
>
next prev parent reply other threads:[~2022-09-26 16:24 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 12:17 [PATCH v2 0/6] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 1/6] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-09-23 14:34 ` Ilpo Järvinen
2022-09-23 14:40 ` Ilpo Järvinen
2022-09-27 12:38 ` matthew.gerlach
2022-09-27 12:54 ` Ilpo Järvinen
2022-09-24 8:29 ` Bagas Sanjaya
2022-09-23 12:17 ` [PATCH v2 2/6] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-24 13:00 ` Tom Rix
2022-09-30 5:01 ` Xu Yilun
2022-09-30 14:09 ` matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 3/6] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 4/6] fpga: dfl: add generic support for MSIX interrupts matthew.gerlach
2022-09-23 14:16 ` Ilpo Järvinen
2022-09-26 14:47 ` matthew.gerlach
2022-09-27 6:46 ` Ilpo Järvinen
2022-09-27 12:17 ` matthew.gerlach
2022-09-23 15:21 ` Andy Shevchenko
2022-09-26 15:13 ` matthew.gerlach [this message]
2022-09-30 3:28 ` Xu Yilun
2022-10-01 14:50 ` matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 5/6] fpga: dfl: parse the location of the feature's registers from DFHv1 matthew.gerlach
2022-09-23 14:55 ` Ilpo Järvinen
2022-09-23 17:06 ` Muddebihal, Basheer Ahmed
2022-09-30 5:57 ` Xu Yilun
2022-09-23 12:17 ` [PATCH v2 6/6] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-23 15:22 ` Andy Shevchenko
2022-09-23 15:34 ` Ilpo Järvinen
2022-09-30 6:07 ` Xu Yilun
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