From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
tianfei.zhang@intel.com, corbet@lwn.net,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-serial <linux-serial@vger.kernel.org>,
Jiri Slaby <jirislaby@kernel.org>,
geert+renesas@glider.be,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
macro@orcam.me.uk, johan@kernel.org,
Lukas Wunner <lukas@wunner.de>,
Matthew Gerlach <matthew.gerlach@intel.com>
Subject: Re: [PATCH v2 5/6] fpga: dfl: parse the location of the feature's registers from DFHv1
Date: Fri, 23 Sep 2022 17:55:51 +0300 (EEST) [thread overview]
Message-ID: <5ce7d953-9289-bb2d-79c-2e5669373a35@linux.intel.com> (raw)
In-Reply-To: <20220923121745.129167-6-matthew.gerlach@linux.intel.com>
On Fri, 23 Sep 2022, matthew.gerlach@linux.intel.com wrote:
> From: Matthew Gerlach <matthew.gerlach@intel.com>
>
> The location of a feature's registers is explicitly
> described in DFHv1 and can be relative to the base of the DFHv1
> or an absolute address. Parse the location and pass the information
> to DFL driver.
>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> ---
> v2: Introduced in v2.
> ---
> drivers/fpga/dfl.c | 26 +++++++++++++++++++++++++-
> drivers/fpga/dfl.h | 4 ++++
> include/linux/dfl.h | 4 ++++
> 3 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index dfd3f563c92d..6fb4f30f93cf 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -381,6 +381,8 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata,
> ddev->feature_id = feature->id;
> ddev->revision = feature->revision;
> ddev->cdev = pdata->dfl_cdev;
> + ddev->csr_start = feature->csr_start;
> + ddev->csr_size = feature->csr_size;
>
> /* add mmio resource */
> parent_res = &pdev->resource[feature->resource_index];
> @@ -708,18 +710,25 @@ struct build_feature_devs_info {
> * struct dfl_feature_info - sub feature info collected during feature dev build
> *
> * @fid: id of this sub feature.
> + * @revision: revision of this sub feature
> + * @dfh_version: version of Device Feature Header (DFH)
> * @mmio_res: mmio resource of this sub feature.
> * @ioaddr: mapped base address of mmio resource.
> * @node: node in sub_features linked list.
> + * @csr_start: DFHv1 start of feature registers
> + * @csr_size: DFHv1 size of feature registers
> * @irq_base: start of irq index in this sub feature.
> * @nr_irqs: number of irqs of this sub feature.
> */
> struct dfl_feature_info {
> u16 fid;
> u8 revision;
> + u8 dfh_version;
> struct resource mmio_res;
> void __iomem *ioaddr;
> struct list_head node;
> + resource_size_t csr_start;
> + resource_size_t csr_size;
> unsigned int irq_base;
> unsigned int nr_irqs;
> };
> @@ -797,6 +806,8 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
> feature->dev = fdev;
> feature->id = finfo->fid;
> feature->revision = finfo->revision;
> + feature->csr_start = finfo->csr_start;
> + feature->csr_size = finfo->csr_size;
>
> /*
> * the FIU header feature has some fundamental functions (sriov
> @@ -1054,6 +1065,7 @@ create_feature_instance(struct build_feature_devs_info *binfo,
> {
> unsigned int irq_base, nr_irqs;
> struct dfl_feature_info *finfo;
> + u8 dfh_version = 0;
> u8 revision = 0;
> int ret;
> u64 v;
> @@ -1061,7 +1073,7 @@ create_feature_instance(struct build_feature_devs_info *binfo,
> if (fid != FEATURE_ID_AFU) {
> v = readq(binfo->ioaddr + ofst);
> revision = FIELD_GET(DFH_REVISION, v);
> -
> + dfh_version = FIELD_GET(DFH_VERSION, v);
> /* read feature size and id if inputs are invalid */
> size = size ? size : feature_size(v);
> fid = fid ? fid : feature_id(v);
> @@ -1080,12 +1092,24 @@ create_feature_instance(struct build_feature_devs_info *binfo,
>
> finfo->fid = fid;
> finfo->revision = revision;
> + finfo->dfh_version = dfh_version;
> finfo->mmio_res.start = binfo->start + ofst;
> finfo->mmio_res.end = finfo->mmio_res.start + size - 1;
> finfo->mmio_res.flags = IORESOURCE_MEM;
> finfo->irq_base = irq_base;
> finfo->nr_irqs = nr_irqs;
Ordering here seems slightly odd. If finfo would be built before calling
parse_feature_irqs(), it could be passed into there and there would be no
need to:
- read version for second time
- pass irq_base & nr_irqs as pointer parameters
--
i.
next prev parent reply other threads:[~2022-09-23 14:56 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 12:17 [PATCH v2 0/6] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 1/6] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-09-23 14:34 ` Ilpo Järvinen
2022-09-23 14:40 ` Ilpo Järvinen
2022-09-27 12:38 ` matthew.gerlach
2022-09-27 12:54 ` Ilpo Järvinen
2022-09-24 8:29 ` Bagas Sanjaya
2022-09-23 12:17 ` [PATCH v2 2/6] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-24 13:00 ` Tom Rix
2022-09-30 5:01 ` Xu Yilun
2022-09-30 14:09 ` matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 3/6] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 4/6] fpga: dfl: add generic support for MSIX interrupts matthew.gerlach
2022-09-23 14:16 ` Ilpo Järvinen
2022-09-26 14:47 ` matthew.gerlach
2022-09-27 6:46 ` Ilpo Järvinen
2022-09-27 12:17 ` matthew.gerlach
2022-09-23 15:21 ` Andy Shevchenko
2022-09-26 15:13 ` matthew.gerlach
2022-09-30 3:28 ` Xu Yilun
2022-10-01 14:50 ` matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 5/6] fpga: dfl: parse the location of the feature's registers from DFHv1 matthew.gerlach
2022-09-23 14:55 ` Ilpo Järvinen [this message]
2022-09-23 17:06 ` Muddebihal, Basheer Ahmed
2022-09-30 5:57 ` Xu Yilun
2022-09-23 12:17 ` [PATCH v2 6/6] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-23 15:22 ` Andy Shevchenko
2022-09-23 15:34 ` Ilpo Järvinen
2022-09-30 6:07 ` Xu Yilun
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