From: matthew.gerlach@linux.intel.com
To: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Cc: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com,
basheer.ahmed.muddebihal@intel.com, trix@redhat.com,
mdf@kernel.org, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, LKML <linux-kernel@vger.kernel.org>,
tianfei.zhang@intel.com, corbet@lwn.net,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-serial <linux-serial@vger.kernel.org>,
Jiri Slaby <jirislaby@kernel.org>,
geert+renesas@glider.be,
Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com,
macro@orcam.me.uk, johan@kernel.org,
Lukas Wunner <lukas@wunner.de>
Subject: Re: [PATCH v2 4/6] fpga: dfl: add generic support for MSIX interrupts
Date: Tue, 27 Sep 2022 05:17:14 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.22.394.2209270516220.2164321@rhweight-WRK1> (raw)
In-Reply-To: <609e122-f6a0-c0c2-4168-4025dd96a1ac@linux.intel.com>
[-- Attachment #1: Type: text/plain, Size: 4261 bytes --]
On Tue, 27 Sep 2022, Ilpo Järvinen wrote:
> On Mon, 26 Sep 2022, matthew.gerlach@linux.intel.com wrote:
>
>>
>>
>> On Fri, 23 Sep 2022, Ilpo Järvinen wrote:
>>
>>> On Fri, 23 Sep 2022, matthew.gerlach@linux.intel.com wrote:
>>>
>>>> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>>>
>>>> Define and use a DFHv1 parameter to add generic support for MSIX
>>>> interrupts for DFL devices.
>>>>
>>>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>>> ---
>>>> v2: fix kernel doc
>>>> clarify use of DFH_VERSION field
>>>> ---
>>>> drivers/fpga/dfl.c | 60 +++++++++++++++++++++++++++++++++++++++++----
>>>> include/linux/dfl.h | 14 +++++++++++
>>>> 2 files changed, 69 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
>>>> index 1132f3c10440..dfd3f563c92d 100644
>>>> --- a/drivers/fpga/dfl.c
>>>> +++ b/drivers/fpga/dfl.c
>>>> @@ -941,23 +941,22 @@ static int parse_feature_irqs(struct
>>>> build_feature_devs_info *binfo,
>>>> void __iomem *base = binfo->ioaddr + ofst;
>>>> unsigned int i, ibase, inr = 0;
>>>> enum dfl_id_type type;
>>>> - int virq;
>>>> + int virq, off;
>>>> u64 v;
>>>>
>>>> type = feature_dev_id_type(binfo->feature_dev);
>>>>
>>>> /*
>>>> * Ideally DFL framework should only read info from DFL header, but
>>>> - * current version DFL only provides mmio resources information for
>>>> + * current version, DFHv0, only provides mmio resources information
>>>> for
>>>> * each feature in DFL Header, no field for interrupt resources.
>>>> * Interrupt resource information is provided by specific mmio
>>>> * registers of each private feature which supports interrupt. So in
>>>> * order to parse and assign irq resources, DFL framework has to look
>>>> * into specific capability registers of these private features.
>>>> *
>>>> - * Once future DFL version supports generic interrupt resource
>>>> - * information in common DFL headers, the generic interrupt parsing
>>>> - * code will be added. But in order to be compatible to old version
>>>> + * DFHv1 supports generic interrupt resource information in DFHv1
>>>> + * parameter blocks. But in order to be compatible to old version
>>>> * DFL, the driver may still fall back to these quirks.
>>>> */
>>>> if (type == PORT_ID) {
>>>> @@ -981,6 +980,36 @@ static int parse_feature_irqs(struct
>>>> build_feature_devs_info *binfo,
>>>> }
>>>> }
>>>>
>>>> + if (fid != FEATURE_ID_AFU && fid != PORT_FEATURE_ID_ERROR &&
>>>> + fid != PORT_FEATURE_ID_UINT && fid != FME_FEATURE_ID_GLOBAL_ERR) {
>>>> +
>>>> + v = FIELD_GET(DFH_VERSION, readq(base));
>>>
>>> I'd call this variable version (or ver) if you want to store it but it
>>> would also fit to switch () line so that no extra variable is needed.
>>
>> I will change the v to dfh_ver to be clearer. I want to store the value
>> because it is used in the default case in the error message. The error
>> message helps to debug broken FPGA images.
>
> Right, I missed that (or didn't think it too much and all being called
> "v" didn't help either :-)).
>
>>>> + if (FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, v)) {
>>>> + off = dfl_find_param(base + DFHv1_PARAM_HDR,
>>>> ofst,
>>>> + DFHv1_PARAM_ID_MSIX);
>>>> + if (off >= 0) {
>>>
>>> I'd reverse these 2 conditions and break when there's nothing to do.
>>
>> I'm not sure what you mean by reversing these conditions because a DFHv1 may
>> or may not have parameters (the first condition), and a DFHv1 may have
>> parameters but may not have a MSI-X parameter (the second condition).
>
> This is what I meant:
>
> if (!FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, v))
> break;
>
> off = dfl_find_param(...);
> if (off < 0)
> break;
>
> ibase = ...
I understand now. This is a good suggestion because the resulting
indentation is better.
Thanks,
Matthew
>
>
> --
> i.
>
>
>>>> + ibase = readl(base + DFHv1_PARAM_HDR +
>>>> + off +
>>>> DFHv1_PARAM_MSIX_STARTV);
>>>> + inr = readl(base + DFHv1_PARAM_HDR +
>>>> + off +
>>>> DFHv1_PARAM_MSIX_NUMV);
>>>> + dev_dbg(binfo->dev, "start %d num %d
>>>> fid 0x%x\n",
>>>> + ibase, inr, fid);
>>>> + }
>>>> + }
>>>> + break;
>
next prev parent reply other threads:[~2022-09-27 12:17 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-23 12:17 [PATCH v2 0/6] Enhance definition of DFH and use enhancements for uart driver matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 1/6] Documentation: fpga: dfl: Add documentation for DFHv1 matthew.gerlach
2022-09-23 14:34 ` Ilpo Järvinen
2022-09-23 14:40 ` Ilpo Järvinen
2022-09-27 12:38 ` matthew.gerlach
2022-09-27 12:54 ` Ilpo Järvinen
2022-09-24 8:29 ` Bagas Sanjaya
2022-09-23 12:17 ` [PATCH v2 2/6] fpga: dfl: Move the DFH definitions matthew.gerlach
2022-09-24 13:00 ` Tom Rix
2022-09-30 5:01 ` Xu Yilun
2022-09-30 14:09 ` matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 3/6] fpga: dfl: Add DFHv1 Register Definitions matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 4/6] fpga: dfl: add generic support for MSIX interrupts matthew.gerlach
2022-09-23 14:16 ` Ilpo Järvinen
2022-09-26 14:47 ` matthew.gerlach
2022-09-27 6:46 ` Ilpo Järvinen
2022-09-27 12:17 ` matthew.gerlach [this message]
2022-09-23 15:21 ` Andy Shevchenko
2022-09-26 15:13 ` matthew.gerlach
2022-09-30 3:28 ` Xu Yilun
2022-10-01 14:50 ` matthew.gerlach
2022-09-23 12:17 ` [PATCH v2 5/6] fpga: dfl: parse the location of the feature's registers from DFHv1 matthew.gerlach
2022-09-23 14:55 ` Ilpo Järvinen
2022-09-23 17:06 ` Muddebihal, Basheer Ahmed
2022-09-30 5:57 ` Xu Yilun
2022-09-23 12:17 ` [PATCH v2 6/6] tty: serial: 8250: add DFL bus driver for Altera 16550 matthew.gerlach
2022-09-23 15:22 ` Andy Shevchenko
2022-09-23 15:34 ` Ilpo Järvinen
2022-09-30 6:07 ` Xu Yilun
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