From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Paul Burton <paulburton@kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
linux-mips@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: "Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
"Tawfik Bayouk" <tawfik.bayouk@mobileye.com>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
"Théo Lebrun" <theo.lebrun@bootlin.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>
Subject: [PATCH v5 09/22] MIPS: traps: Handle CPU with non standard vint offset
Date: Tue, 12 Dec 2023 17:34:41 +0100 [thread overview]
Message-ID: <20231212163459.1923041-10-gregory.clement@bootlin.com> (raw)
In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com>
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Some BMIPS cpus has none standard start offset for vector interrupts.
Handle those CPUs in vector size calculation and handler setup process.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++---------
1 file changed, 23 insertions(+), 9 deletions(-)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index ea59d321f713e..7e6e6df59e6d7 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -74,7 +74,6 @@
#include "access-helper.h"
-#define MAX(a, b) ((a) >= (b) ? (a) : (b))
extern void check_wait(void);
extern asmlinkage void rollback_handle_int(void);
@@ -2005,6 +2004,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs)
unsigned long ebase;
EXPORT_SYMBOL_GPL(ebase);
unsigned long exception_handlers[32];
+static unsigned long vi_vecbase;
unsigned long vi_handlers[64];
void reserve_exception_space(phys_addr_t addr, unsigned long size)
@@ -2074,7 +2074,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
handler = (unsigned long) addr;
vi_handlers[n] = handler;
- b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
+ b = (unsigned char *)(vi_vecbase + n * VECTORSPACING);
if (srs >= srssets)
panic("Shadow register set %d not supported", srs);
@@ -2370,20 +2370,33 @@ void __init trap_init(void)
extern char except_vec3_generic;
extern char except_vec4;
extern char except_vec3_r4000;
- unsigned long i, vec_size;
+ unsigned long i, vec_size, vi_vec_offset;
phys_addr_t ebase_pa;
check_wait();
+ if (cpu_has_veic || cpu_has_vint) {
+ switch (current_cpu_type()) {
+ case CPU_BMIPS3300:
+ case CPU_BMIPS4380:
+ vi_vec_offset = 0x400;
+ break;
+ case CPU_BMIPS5000:
+ vi_vec_offset = 0x1000;
+ break;
+ default:
+ vi_vec_offset = 0x200;
+ break;
+ }
+ vec_size = vi_vec_offset + VECTORSPACING * 64;
+ } else {
+ vec_size = 0x400;
+ }
+
if (!cpu_has_mips_r2_r6) {
ebase = CAC_BASE;
- vec_size = 0x400;
} else {
- if (cpu_has_veic || cpu_has_vint)
- vec_size = 0x200 + VECTORSPACING*64;
- else
- vec_size = PAGE_SIZE;
-
+ vec_size = max(vec_size, PAGE_SIZE);
ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
if (!ebase_pa)
panic("%s: Failed to allocate %lu bytes align=0x%x\n",
@@ -2450,6 +2463,7 @@ void __init trap_init(void)
* Initialise interrupt handlers
*/
if (cpu_has_veic || cpu_has_vint) {
+ vi_vecbase = ebase + vi_vec_offset;
int nvec = cpu_has_veic ? 64 : 8;
for (i = 0; i < nvec; i++)
set_vi_handler(i, NULL);
--
2.42.0
next prev parent reply other threads:[~2023-12-12 16:36 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 16:34 [PATCH v5 00/22] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 01/22] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
2023-12-21 14:38 ` Thomas Bogendoerfer
2023-12-12 16:34 ` [PATCH v5 02/22] MIPS: Export higher/highest relocation functions in uasm Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 03/22] MIPS: spaces: Define a couple of handy macros Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 04/22] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 05/22] MIPS: Fix set_uncached_handler for ebase " Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 06/22] MIPS: Refactor mips_cps_core_entry implementation Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 07/22] MIPS: Fix cache issue with mips_cps_core_entry Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 08/22] MIPS: Allow kernel base to be set from Kconfig for all platforms Gregory CLEMENT
2023-12-12 16:34 ` Gregory CLEMENT [this message]
2023-12-12 16:34 ` [PATCH v5 10/22] MIPS: Avoid unnecessary reservation of exception space Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 11/22] MIPS: traps: Enhance memblock ebase allocation process Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 12/22] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 13/22] MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0 Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 14/22] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 15/22] dt-bindings: mips: cpus: Sort the entries Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 16/22] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 17/22] dt-bindings: mips: Add bindings for Mobileye SoCs Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 18/22] dt-bindings: mfd: syscon: Document EyeQ5 OLB Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 19/22] MIPS: mobileye: Add EyeQ5 dtsi Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 20/22] MIPS: mobileye: Add EPM5 device tree Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 21/22] MIPS: generic: Add support for Mobileye EyeQ5 Gregory CLEMENT
2023-12-14 9:46 ` Jiaxun Yang
2023-12-15 16:52 ` Gregory CLEMENT
2023-12-15 20:29 ` Jiaxun Yang
2023-12-12 16:34 ` [PATCH v5 22/22] MAINTAINERS: Add entry for Mobileye MIPS SoCs Gregory CLEMENT
2023-12-15 16:39 ` [PATCH v5 00/22] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-12-20 21:49 ` Thomas Bogendoerfer
2023-12-21 1:57 ` Jiaxun Yang
2023-12-21 7:57 ` Gregory CLEMENT
2023-12-21 9:13 ` Gregory CLEMENT
2023-12-21 14:40 ` Thomas Bogendoerfer
2023-12-21 14:55 ` Thomas Bogendoerfer
2023-12-21 15:26 ` Gregory CLEMENT
2023-12-21 16:55 ` Thomas Bogendoerfer
2023-12-21 22:25 ` Jiaxun Yang
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