From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Paul Burton <paulburton@kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
linux-mips@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: "Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
"Tawfik Bayouk" <tawfik.bayouk@mobileye.com>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
"Théo Lebrun" <theo.lebrun@bootlin.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Vladimir Kondratiev" <vladimir.kondratiev@intel.com>,
"Gregory CLEMENT" <gregory.clement@bootlin.com>
Subject: [PATCH v5 04/22] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS
Date: Tue, 12 Dec 2023 17:34:36 +0100 [thread overview]
Message-ID: <20231212163459.1923041-5-gregory.clement@bootlin.com> (raw)
In-Reply-To: <20231212163459.1923041-1-gregory.clement@bootlin.com>
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Use {highest, higher, hi, lo} immediate loading sequence
to load 64 bit jump address for handler when kernel is
loaded to XKPHYS.
Co-developed-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@intel.com>
Co-developed-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
arch/mips/kernel/genex.S | 19 +++++++++++++++----
arch/mips/kernel/traps.c | 34 ++++++++++++++++++++++++----------
2 files changed, 39 insertions(+), 14 deletions(-)
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index b6de8e88c1bd4..fd765ad9ecac0 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -272,11 +272,22 @@ NESTED(except_vec_vi, 0, sp)
.set push
.set noreorder
PTR_LA v1, except_vec_vi_handler
-FEXPORT(except_vec_vi_lui)
- lui v0, 0 /* Patched */
+#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
+FEXPORT(except_vec_vi_hi)
+ lui v0, 0 /* Patched */
+#else
+FEXPORT(except_vec_vi_highest)
+ lui v0, 0 /* Patched */
+FEXPORT(except_vec_vi_higher)
+ daddiu v0, 0 /* Patched */
+ dsll v0, 16
+FEXPORT(except_vec_vi_hi)
+ daddiu v0, 0 /* Patched */
+ dsll v0, 16
+#endif
jr v1
-FEXPORT(except_vec_vi_ori)
- ori v0, 0 /* Patched */
+FEXPORT(except_vec_vi_lo)
+ PTR_ADDIU v0, 0 /* Patched */
.set pop
END(except_vec_vi)
EXPORT(except_vec_vi_end)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 246c6a6b02614..60c513c51684f 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2091,18 +2091,26 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
* If no shadow set is selected then use the default handler
* that does normal register saving and standard interrupt exit
*/
- extern const u8 except_vec_vi[], except_vec_vi_lui[];
- extern const u8 except_vec_vi_ori[], except_vec_vi_end[];
+ extern const u8 except_vec_vi[], except_vec_vi_hi[];
+ extern const u8 except_vec_vi_lo[], except_vec_vi_end[];
+#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32)
+ extern const u8 except_vec_vi_highest[], except_vec_vi_higher[];
+#endif
extern const u8 rollback_except_vec_vi[];
const u8 *vec_start = using_rollback_handler() ?
rollback_except_vec_vi : except_vec_vi;
#if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN)
- const int lui_offset = except_vec_vi_lui - vec_start + 2;
- const int ori_offset = except_vec_vi_ori - vec_start + 2;
+ const int imm_offset = 2;
#else
- const int lui_offset = except_vec_vi_lui - vec_start;
- const int ori_offset = except_vec_vi_ori - vec_start;
+ const int imm_offset = 0;
+#endif
+#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32)
+ const int highest_offset = except_vec_vi_highest - vec_start + imm_offset;
+ const int higher_offset = except_vec_vi_higher - vec_start + imm_offset;
#endif
+ const int hi_offset = except_vec_vi_hi - vec_start + imm_offset;
+ const int lo_offset = except_vec_vi_lo - vec_start + imm_offset;
+
const int handler_len = except_vec_vi_end - vec_start;
if (handler_len > VECTORSPACING) {
@@ -2119,10 +2127,16 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
#else
handler_len);
#endif
- h = (u16 *)(b + lui_offset);
- *h = (handler >> 16) & 0xffff;
- h = (u16 *)(b + ori_offset);
- *h = (handler & 0xffff);
+#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32)
+ h = (u16 *)(b + highest_offset);
+ *h = uasm_rel_highest(handler);
+ h = (u16 *)(b + higher_offset);
+ *h = uasm_rel_higher(handler);
+#endif
+ h = (u16 *)(b + hi_offset);
+ *h = uasm_rel_hi(handler);
+ h = (u16 *)(b + lo_offset);
+ *h = uasm_rel_lo(handler);
local_flush_icache_range((unsigned long)b,
(unsigned long)(b+handler_len));
}
--
2.42.0
next prev parent reply other threads:[~2023-12-12 16:35 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 16:34 [PATCH v5 00/22] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 01/22] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
2023-12-21 14:38 ` Thomas Bogendoerfer
2023-12-12 16:34 ` [PATCH v5 02/22] MIPS: Export higher/highest relocation functions in uasm Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 03/22] MIPS: spaces: Define a couple of handy macros Gregory CLEMENT
2023-12-12 16:34 ` Gregory CLEMENT [this message]
2023-12-12 16:34 ` [PATCH v5 05/22] MIPS: Fix set_uncached_handler for ebase in XKPHYS Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 06/22] MIPS: Refactor mips_cps_core_entry implementation Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 07/22] MIPS: Fix cache issue with mips_cps_core_entry Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 08/22] MIPS: Allow kernel base to be set from Kconfig for all platforms Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 09/22] MIPS: traps: Handle CPU with non standard vint offset Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 10/22] MIPS: Avoid unnecessary reservation of exception space Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 11/22] MIPS: traps: Enhance memblock ebase allocation process Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 12/22] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 13/22] MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0 Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 14/22] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 15/22] dt-bindings: mips: cpus: Sort the entries Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 16/22] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 17/22] dt-bindings: mips: Add bindings for Mobileye SoCs Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 18/22] dt-bindings: mfd: syscon: Document EyeQ5 OLB Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 19/22] MIPS: mobileye: Add EyeQ5 dtsi Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 20/22] MIPS: mobileye: Add EPM5 device tree Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 21/22] MIPS: generic: Add support for Mobileye EyeQ5 Gregory CLEMENT
2023-12-14 9:46 ` Jiaxun Yang
2023-12-15 16:52 ` Gregory CLEMENT
2023-12-15 20:29 ` Jiaxun Yang
2023-12-12 16:34 ` [PATCH v5 22/22] MAINTAINERS: Add entry for Mobileye MIPS SoCs Gregory CLEMENT
2023-12-15 16:39 ` [PATCH v5 00/22] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-12-20 21:49 ` Thomas Bogendoerfer
2023-12-21 1:57 ` Jiaxun Yang
2023-12-21 7:57 ` Gregory CLEMENT
2023-12-21 9:13 ` Gregory CLEMENT
2023-12-21 14:40 ` Thomas Bogendoerfer
2023-12-21 14:55 ` Thomas Bogendoerfer
2023-12-21 15:26 ` Gregory CLEMENT
2023-12-21 16:55 ` Thomas Bogendoerfer
2023-12-21 22:25 ` Jiaxun Yang
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