From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Gregory CLEMENT <gregory.clement@bootlin.com>
Cc: "Paul Burton" <paulburton@kernel.org>,
linux-mips@vger.kernel.org,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
"Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
"Tawfik Bayouk" <tawfik.bayouk@mobileye.com>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
"Théo Lebrun" <theo.lebrun@bootlin.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>,
"Florian Fainelli" <florian.fainelli@broadcom.com>
Subject: Re: [PATCH v5 01/22] MIPS: compressed: Use correct instruction for 64 bit code
Date: Thu, 21 Dec 2023 15:38:20 +0100 [thread overview]
Message-ID: <ZYRN3FMH4od3QX+i@alpha.franken.de> (raw)
In-Reply-To: <20231212163459.1923041-2-gregory.clement@bootlin.com>
On Tue, Dec 12, 2023 at 05:34:33PM +0100, Gregory CLEMENT wrote:
> The code clearing BSS already use macro or use correct instruction
> depending if the CPU is 32 bits or 64 bits. However, a few
> instructions remained 32 bits only.
>
> By using the accurate MACRO, it is now possible to deal with memory
> address beyond 32 bits. As a side effect, when using 64bits processor,
> it also divides the loop number needed to clear the BSS by 2.
>
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> arch/mips/boot/compressed/head.S | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
> index 5795d0af1e1b2..d237a834b85ee 100644
> --- a/arch/mips/boot/compressed/head.S
> +++ b/arch/mips/boot/compressed/head.S
> @@ -25,8 +25,8 @@
> /* Clear BSS */
> PTR_LA a0, _edata
> PTR_LA a2, _end
> -1: sw zero, 0(a0)
> - addiu a0, a0, 4
> +1: PTR_S zero, 0(a0)
> + PTR_ADDIU a0, a0, PTRSIZE
> bne a2, a0, 1b
>
> PTR_LA a0, (.heap) /* heap address */
> --
> 2.42.0
applied to mips-next.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
next prev parent reply other threads:[~2023-12-21 14:55 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 16:34 [PATCH v5 00/22] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 01/22] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
2023-12-21 14:38 ` Thomas Bogendoerfer [this message]
2023-12-12 16:34 ` [PATCH v5 02/22] MIPS: Export higher/highest relocation functions in uasm Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 03/22] MIPS: spaces: Define a couple of handy macros Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 04/22] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 05/22] MIPS: Fix set_uncached_handler for ebase " Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 06/22] MIPS: Refactor mips_cps_core_entry implementation Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 07/22] MIPS: Fix cache issue with mips_cps_core_entry Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 08/22] MIPS: Allow kernel base to be set from Kconfig for all platforms Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 09/22] MIPS: traps: Handle CPU with non standard vint offset Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 10/22] MIPS: Avoid unnecessary reservation of exception space Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 11/22] MIPS: traps: Enhance memblock ebase allocation process Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 12/22] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 13/22] MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0 Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 14/22] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 15/22] dt-bindings: mips: cpus: Sort the entries Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 16/22] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 17/22] dt-bindings: mips: Add bindings for Mobileye SoCs Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 18/22] dt-bindings: mfd: syscon: Document EyeQ5 OLB Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 19/22] MIPS: mobileye: Add EyeQ5 dtsi Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 20/22] MIPS: mobileye: Add EPM5 device tree Gregory CLEMENT
2023-12-12 16:34 ` [PATCH v5 21/22] MIPS: generic: Add support for Mobileye EyeQ5 Gregory CLEMENT
2023-12-14 9:46 ` Jiaxun Yang
2023-12-15 16:52 ` Gregory CLEMENT
2023-12-15 20:29 ` Jiaxun Yang
2023-12-12 16:34 ` [PATCH v5 22/22] MAINTAINERS: Add entry for Mobileye MIPS SoCs Gregory CLEMENT
2023-12-15 16:39 ` [PATCH v5 00/22] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-12-20 21:49 ` Thomas Bogendoerfer
2023-12-21 1:57 ` Jiaxun Yang
2023-12-21 7:57 ` Gregory CLEMENT
2023-12-21 9:13 ` Gregory CLEMENT
2023-12-21 14:40 ` Thomas Bogendoerfer
2023-12-21 14:55 ` Thomas Bogendoerfer
2023-12-21 15:26 ` Gregory CLEMENT
2023-12-21 16:55 ` Thomas Bogendoerfer
2023-12-21 22:25 ` Jiaxun Yang
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