* [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
@ 2023-02-21 2:46 Hal Feng
2023-02-21 2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
` (21 more replies)
0 siblings, 22 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
This patch series adds basic clock, reset & DT support for StarFive
JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
of VisionFive 2 board and JH7110 SoC.
You can simply review or test the patches at the link [3].
[1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/
[2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/
[3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
Changes since v3:
- Suggested by Conor, Merged clock & reset series and DT series together
so that they could go via the same tree as the dt-binding headers are
required by both driver & devicetree.
- Rebased on tag v6.2.
[Clock & reset]
Patch 2:
- Split patch 2 into two. One for renaming file and one for renaming
variables. (by Conor)
Patch 4:
- Split patch 4 into two. One for code movement and one for
extraction. (by Conor)
Patch 5 & 9 & 10 & 11:
- Fixed the issues reported by kernel test robot.
Patch 9:
- Set (&priv->base) as driver data instead of (priv->base).
- Set the frequency of clock PLL0 as 1000MHz for Synchronizing with the
lastest u-boot setting from StarFive. (by Emil)
- Used devm_kzalloc() instead of kzalloc() when registering aux device.
Patch 10:
- Set (&priv->base) as driver data instead of (priv->base).
Patch 11:
- Used (*base) to get the register base address instead of (base).
[Device tree]
- Dropped patch 1, 4, 5 because they were accepted.
- Added a new patch to add SiFive S7 compatible. (by Conor)
- Added a new patch to add JH7110 pin function definitions.
Patch 6:
- Changed the label "S76_0" to "S7_0" and used compatible "sifive,s7"
for core 0.
- Updated ISA of each cores. (by Conor)
- Made the node names generic. (by Krzysztof)
- Added clock-output-names for all external clocks.
- Added i2c0~6 nodes.
- Changed the node name "gpio" to "pinctrl". Changed the label "gpio"
and "gpioa" to "sysgpio" and "aongpio". (by Conor)
Patch 7:
- Separated the long lines into more lines in Makefile. (by Conor)
- Renamed jh7110-starfive-visionfive-2-va.dts and
jh7110-starfive-visionfive-2-vb.dts to
jh7110-starfive-visionfive-2-v1.2a.dts and
jh7110-starfive-visionfive-2-v1.3b.dts.
Changed the model and compatible to match v1.2A and v1.3B which
are printed on the silkscreen of VisionFive 2 board. (by Emil)
- Configured pins for i2c0/2/5/6 and enabled them.
clock & reset v3: https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/
DT v3: https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
Changes since v2:
[Clock & reset]
- Rebased on tag v6.1.
- Added "JH71X0" to the StarFive driver headers in MAINTAINERS.
- Removed Co-developed-by tag of Hal in patch 1 and patch 4.
- Changed the commit author from Hal to Emil in patch 2 and patch 5.
Removed Co-developed-by tag of Emil in patch 2 and patch 5. (by Emil)
- Improved the coding style of patch 11, 12 and 13.
- Dropped patch 14. (by Emil)
Patch 4:
- Passed the "owner" member of reset_controller_dev structure
directly in reset_starfive_jh7100_register(). (by Emil)
- Added MAINTAINERS changes.
Patch 7:
- Split patch 7 into sys part and aon part. Merged them into patch 9 and
patch 10 respectively. (by Krzysztof)
- Renamed include/dt-bindings/clock/starfive-jh7110.h to
include/dt-bindings/clock/starfive,jh7110-crg.h. (by Krzysztof)
- Synchronized the definitions with the latest changes from Emil.
Patch 8:
- Split patch 8 into sys part and aon part. Merged them into patch 9 and
patch 10 respectively. (by Krzysztof)
- Renamed include/dt-bindings/reset/starfive-jh7110.h to
include/dt-bindings/reset/starfive,jh7110-crg.h. (by Krzysztof)
- Fixed the date of Copyright. (by Emil)
- Dropped weird indentations. (by Krzysztof)
- Synchronized the definitions with the latest changes from Emil.
Patch 9:
- Improved the description of clocks. (by Emil and Krzysztof)
- Added MAINTAINERS changes.
Patch 10:
- Improved the description of clocks. (by Emil and Krzysztof)
- Changed the clock-name "clk_rtc" to "rtc_osc" and "apb_bus_func" to
"apb_bus".
Patch 11:
- Removed the flags of trace/debug clocks and set the flags of core clocks
as CLK_IS_CRITICAL. (by Emil)
- Deleted the extra 1-1 clocks and synchronized the clock tree with the
latest changes from Emil. (by Emil)
- Selected RESET_STARFIVE_JH7110 in Kconfig option CLK_STARFIVE_JH7110_SYS.
Patch 12:
- Changed the macro JH7110_AONCLK_RTC to JH7110_AONCLK_RTC_OSC and
JH7110_AONCLK_APB_BUS_FUNC to JH7110_AONCLK_APB_BUS.
- Synchronized the clock tree with the latest changes from Emil.
- Set the MODULE_LICENSE as "GPL" according to commit bf7fbeeae6db.
Patch 13:
- Removed the "asserted" member in reset_info structure and always pass
NULL when calling reset_starfive_jh71x0_register(). (by Emil)
[Device tree]
- Rebased on tag v6.1.
- Dropped patch 8 because it was merged.
Patch 1:
- Made the links into "Link:" tags. (by Conor)
- Corrected the board name to "VisionFive 2" instead of
"VisionFive V2" and added compatibles for version A and
version B of VisionFive 2. (by Emil)
Patch 4:
- Used "sifive,ccache0" compatible string to match. (by Conor)
Patch 5:
- Dropped "select SIFIVE_CCACHE" in config SOC_STARFIVE. (by Conor)
- Dropped "starfive,jh7110-ccache" compatible in
drivers/soc/sifive/sifive_ccache.c.
Patch 6:
- Removed all "clock-frequency = <0>". (by Conor)
- Sorted the nodes after their addresses. (by Emil)
- Renamed "clk_rtc" to "rtc_osc".
- Added "sifive,ccache0" compatible in the cache-controller node.
- Renamed "JH7110_SYSCLK_APB_BUS_FUNC" to "JH7110_SYSCLK_APB_BUS" and
renamed "apb_bus_func" to "apb_bus".
Renamed "JH7110_SYSCLK_IOMUX" to "JH7110_SYSCLK_IOMUX_APB".
Renamed "JH7110_SYSRST_IOMUX" to "JH7110_SYSRST_IOMUX_APB".
Renamed "JH7110_AONRST_AON_IOMUX" to "JH7110_AONRST_IOMUX".
- Removed "reg-names" in gpio nodes.
Patch 7:
- Corrected the board name to "VisionFive 2" instead of "VisionFive V2".
- Renamed jh7110-starfive-visionfive-v2.dts to
jh7110-starfive-visionfive-2.dtsi.
- Added dts for VisionFive 2 version A and version B boards.
- In the chosen node, deleted "linux,initrd-start" and "linux,initrd-end"
and changed the value of "stdout-path" to "serial0:115200n8".
- Changed the bias of uart0 "rx-pins" to
"bias-disable; /* external pull-up */".
- Renamed "clk_rtc" to "rtc_osc".
- Moved the gpio node behind the uart0 node.
clock & reset v2: https://lore.kernel.org/all/20221118010627.70576-1-hal.feng@starfivetech.com/
DT v2: https://lore.kernel.org/all/20221118011714.70877-1-hal.feng@starfivetech.com/
Changes since v1:
[Clock & reset]
- Rebased on tag v6.1-rc5.
- Rewrote the clock and reset drivers using auxiliary bus framework, so
patch 8, 9, 15 were dropped and all patches changed a lot. (by Stephen)
- Split Patch 14 into two patches. One is for factoring out the common
JH71X0 code, the another one is for renaming. (by Stephen)
- Created a subdirectory for StarFive reset drivers.
- Factored out common JH71X0 reset code.
- Renamed the common clock and reset code from "*starfive*" or
"*STARFIVE*" to "*jh71x0*" or "*JH71X0*".
- Combined JH7110 system and always-on clock DT binding headers in one
file named "include/dt-bindings/clock/starfive-jh7110.h".
- Renamed clock definitions "JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK" and
"JH7110_SYSCLK_U2_PCLK_MUX_PCLK" to "JH7110_SYSCLK_PCLK2_MUX_FUNC" and
"JH7110_SYSCLK_PCLK2_MUX".
- Rewrote the DT bindings of clock and reset for using auxiliary bus.
- Registered an auxiliary device for reset controller in clock drivers.
- Changed clock names "CODAJ*" and "WAVE*" to "codaj*" and "wave*".
Changed clock names "u2_pclk_mux_func_pclk" and "u2_pclk_mux_pclk" to
"pclk2_mux_func" and "pclk2_mux".
- Changed the flags of clock apb0 and noc_bus_isp_axi to CLK_IS_CRITICAL
as suggested by StarFive SDK group.
- Registered clock gmac0_gtxc as a gate clock instead of a div clock
as suggested by StarFive SDK group.
- Changed the frequency of clock pll2_out to 1188MHz as suggested by
StarFive SDK group.
- Fixed the bug that the clock JH7110_AONCLK_GMAC0_GTXCLK was not handled
in JH7110 always-on clock driver.
- Registered the reset driver as an auxiliary driver.
- Reworded the commit messages.
[Device tree]
- Rebased on tag v6.1-rc5.
- Added blank line in patch 1. (by Krzysztof)
- Rebased patch 4 and 6 on the newest code. (by Conor)
- Dropped patch 5. (by Conor)
- Removed the quirk of JH7100 in patch 6, considering this patch series
should only add support for JH7110.
- For patch 27, added Co-developed-by tag for Jianlong and me. Renamed
cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style
of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts.
Rewrote clock-controller nodes and deleted reset-controller nodes for
using auxiliary bus. Rewrote gpio nodes following generic pinctrl
bindings. Removed the redundant second reset entry of uart nodes.
- For patch 28, added Co-developed-by tag for Jianlong and me. Added a
chosen node. Removed reserved-memory node. Added fixed frequency clock
nodes for overriding the "clock-frequency" properties. Rewrote the gpio
nodes following generic pinctrl bindings.
- Dropped patch 30. (by Conor)
- Reworded the commit messages.
v1: https://lore.kernel.org/all/20220929143225.17907-1-hal.feng@linux.starfivetech.com/
Emil Renner Berthing (16):
clk: starfive: Factor out common JH7100 and JH7110 code
clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
clk: starfive: Rename "jh7100" to "jh71x0" for the common code
reset: Create subdirectory for StarFive drivers
reset: starfive: Factor out common JH71X0 reset code
reset: starfive: Extract the common JH71X0 reset code
reset: starfive: Rename "jh7100" to "jh71x0" for the common code
reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
dt-bindings: clock: Add StarFive JH7110 system clock and reset
generator
dt-bindings: clock: Add StarFive JH7110 always-on clock and reset
generator
clk: starfive: Add StarFive JH7110 system clock driver
clk: starfive: Add StarFive JH7110 always-on clock driver
dt-bindings: timer: Add StarFive JH7110 clint
dt-bindings: interrupt-controller: Add StarFive JH7110 plic
riscv: dts: starfive: Add initial StarFive JH7110 device tree
riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
tree
Hal Feng (2):
reset: starfive: Add StarFive JH7110 reset driver
dt-bindings: riscv: Add SiFive S7 compatible
Jianlong Huang (1):
riscv: dts: starfive: Add StarFive JH7110 pin function definitions
.../clock/starfive,jh7110-aoncrg.yaml | 76 ++
.../clock/starfive,jh7110-syscrg.yaml | 80 ++
.../sifive,plic-1.0.0.yaml | 1 +
.../devicetree/bindings/riscv/cpus.yaml | 1 +
.../bindings/timer/sifive,clint.yaml | 1 +
MAINTAINERS | 16 +-
arch/riscv/boot/dts/starfive/Makefile | 6 +-
arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++++
.../jh7110-starfive-visionfive-2-v1.2a.dts | 13 +
.../jh7110-starfive-visionfive-2-v1.3b.dts | 13 +
.../jh7110-starfive-visionfive-2.dtsi | 215 ++++++
arch/riscv/boot/dts/starfive/jh7110.dtsi | 507 +++++++++++++
drivers/clk/starfive/Kconfig | 27 +
drivers/clk/starfive/Makefile | 6 +-
.../clk/starfive/clk-starfive-jh7100-audio.c | 74 +-
drivers/clk/starfive/clk-starfive-jh7100.c | 713 +++++-------------
drivers/clk/starfive/clk-starfive-jh7100.h | 112 ---
.../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++
.../clk/starfive/clk-starfive-jh7110-sys.c | 448 +++++++++++
drivers/clk/starfive/clk-starfive-jh71x0.c | 383 ++++++++++
drivers/clk/starfive/clk-starfive-jh71x0.h | 122 +++
drivers/reset/Kconfig | 8 +-
drivers/reset/Makefile | 2 +-
drivers/reset/reset-starfive-jh7100.c | 173 -----
drivers/reset/starfive/Kconfig | 20 +
drivers/reset/starfive/Makefile | 5 +
.../reset/starfive/reset-starfive-jh7100.c | 74 ++
.../reset/starfive/reset-starfive-jh7110.c | 64 ++
.../reset/starfive/reset-starfive-jh71x0.c | 131 ++++
.../reset/starfive/reset-starfive-jh71x0.h | 20 +
.../dt-bindings/clock/starfive,jh7110-crg.h | 225 ++++++
.../dt-bindings/reset/starfive,jh7110-crg.h | 154 ++++
32 files changed, 3296 insertions(+), 858 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
delete mode 100644 drivers/reset/reset-starfive-jh7100.c
create mode 100644 drivers/reset/starfive/Kconfig
create mode 100644 drivers/reset/starfive/Makefile
create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.c
create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c
create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
base-commit: c9c3395d5e3dcc6daee66c6908354d47bf98cb0c
--
2.38.1
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
` (20 subsequent siblings)
21 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
The clock control registers on the StarFive JH7100 and JH7110 work
identically, so factor out the code then drivers for the two SoCs
can share it without depending on each other. No functional change.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
MAINTAINERS | 4 +-
drivers/clk/starfive/Kconfig | 5 +
drivers/clk/starfive/Makefile | 3 +-
drivers/clk/starfive/clk-starfive-jh7100.c | 325 --------------------
drivers/clk/starfive/clk-starfive-jh7100.h | 2 +
drivers/clk/starfive/clk-starfive-jh71x0.c | 333 +++++++++++++++++++++
6 files changed, 344 insertions(+), 328 deletions(-)
create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 135d93368d36..0b3246ca0f48 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19911,11 +19911,11 @@ M: Emil Renner Berthing <kernel@esmil.dk>
S: Maintained
F: arch/riscv/boot/dts/starfive/
-STARFIVE JH7100 CLOCK DRIVERS
+STARFIVE JH71X0 CLOCK DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
S: Maintained
F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
-F: drivers/clk/starfive/clk-starfive-jh7100*
+F: drivers/clk/starfive/clk-starfive-jh71*
F: include/dt-bindings/clock/starfive-jh7100*.h
STARFIVE JH7100 PINCTRL DRIVER
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 003bd2d56ce7..594d516dcb38 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -1,8 +1,12 @@
# SPDX-License-Identifier: GPL-2.0
+config CLK_STARFIVE_JH71X0
+ bool
+
config CLK_STARFIVE_JH7100
bool "StarFive JH7100 clock support"
depends on SOC_STARFIVE || COMPILE_TEST
+ select CLK_STARFIVE_JH71X0
default SOC_STARFIVE
help
Say yes here to support the clock controller on the StarFive JH7100
@@ -11,6 +15,7 @@ config CLK_STARFIVE_JH7100
config CLK_STARFIVE_JH7100_AUDIO
tristate "StarFive JH7100 audio clock support"
depends on CLK_STARFIVE_JH7100
+ select CLK_STARFIVE_JH71X0
default m if SOC_STARFIVE
help
Say Y or M here to support the audio clocks on the StarFive JH7100
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 0fa8ecb9ec1c..82edfa9f9cb8 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
-# StarFive Clock
+obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
+
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index 691aeebc7092..eea52f16af0d 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -7,15 +7,10 @@
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
-#include <linux/bits.h>
#include <linux/clk-provider.h>
-#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
-#include <linux/module.h>
#include <linux/platform_device.h>
#include <dt-bindings/clock/starfive-jh7100.h>
@@ -269,326 +264,6 @@ static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
};
-static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
-{
- return container_of(hw, struct jh7100_clk, hw);
-}
-
-static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
-{
- return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
-}
-
-static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
-{
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
- void __iomem *reg = priv->base + 4 * clk->idx;
-
- return readl_relaxed(reg);
-}
-
-static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
-{
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
- void __iomem *reg = priv->base + 4 * clk->idx;
- unsigned long flags;
-
- spin_lock_irqsave(&priv->rmw_lock, flags);
- value |= readl_relaxed(reg) & ~mask;
- writel_relaxed(value, reg);
- spin_unlock_irqrestore(&priv->rmw_lock, flags);
-}
-
-static int jh7100_clk_enable(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
- return 0;
-}
-
-static void jh7100_clk_disable(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
-}
-
-static int jh7100_clk_is_enabled(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
-
- return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
-}
-
-static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
-
- return div ? parent_rate / div : 0;
-}
-
-static int jh7100_clk_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- unsigned long parent = req->best_parent_rate;
- unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
- unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
- unsigned long result = parent / div;
-
- /*
- * we want the result clamped by min_rate and max_rate if possible:
- * case 1: div hits the max divider value, which means it's less than
- * parent / rate, so the result is greater than rate and min_rate in
- * particular. we can't do anything about result > max_rate because the
- * divider doesn't go any further.
- * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
- * always lower or equal to rate and max_rate. however the result may
- * turn out lower than min_rate, but then the next higher rate is fine:
- * div - 1 = ceil(parent / rate) - 1 < parent / rate
- * and thus
- * min_rate <= rate < parent / (div - 1)
- */
- if (result < req->min_rate && div > 1)
- result = parent / (div - 1);
-
- req->rate = result;
- return 0;
-}
-
-static int jh7100_clk_set_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long parent_rate)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
- 1UL, (unsigned long)clk->max_div);
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
- return 0;
-}
-
-static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 reg = jh7100_clk_reg_get(clk);
- unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
- ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
-
- return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
-}
-
-static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- unsigned long parent100 = 100 * req->best_parent_rate;
- unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
- unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
- unsigned long result = parent100 / div100;
-
- /* clamp the result as in jh7100_clk_determine_rate() above */
- if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
- result = parent100 / (div100 + 1);
- if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
- result = parent100 / (div100 - 1);
-
- req->rate = result;
- return 0;
-}
-
-static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long parent_rate)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
- u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
- return 0;
-}
-
-static u8 jh7100_clk_get_parent(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = jh7100_clk_reg_get(clk);
-
- return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
-}
-
-static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
- return 0;
-}
-
-static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- return clk_mux_determine_rate_flags(hw, req, 0);
-}
-
-static int jh7100_clk_get_phase(struct clk_hw *hw)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = jh7100_clk_reg_get(clk);
-
- return (value & JH7100_CLK_INVERT) ? 180 : 0;
-}
-
-static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
-{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value;
-
- if (degrees == 0)
- value = 0;
- else if (degrees == 180)
- value = JH7100_CLK_INVERT;
- else
- return -EINVAL;
-
- jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
- return 0;
-}
-
-#ifdef CONFIG_DEBUG_FS
-static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
-{
- static const struct debugfs_reg32 jh7100_clk_reg = {
- .name = "CTRL",
- .offset = 0,
- };
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
- struct debugfs_regset32 *regset;
-
- regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
- if (!regset)
- return;
-
- regset->regs = &jh7100_clk_reg;
- regset->nregs = 1;
- regset->base = priv->base + 4 * clk->idx;
-
- debugfs_create_regset32("registers", 0400, dentry, regset);
-}
-#else
-#define jh7100_clk_debug_init NULL
-#endif
-
-static const struct clk_ops jh7100_clk_gate_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_div_ops = {
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_fdiv_ops = {
- .recalc_rate = jh7100_clk_frac_recalc_rate,
- .determine_rate = jh7100_clk_frac_determine_rate,
- .set_rate = jh7100_clk_frac_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gdiv_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_mux_ops = {
- .determine_rate = jh7100_clk_mux_determine_rate,
- .set_parent = jh7100_clk_set_parent,
- .get_parent = jh7100_clk_get_parent,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gmux_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .determine_rate = jh7100_clk_mux_determine_rate,
- .set_parent = jh7100_clk_set_parent,
- .get_parent = jh7100_clk_get_parent,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_mdiv_ops = {
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .get_parent = jh7100_clk_get_parent,
- .set_parent = jh7100_clk_set_parent,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_gmd_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .get_parent = jh7100_clk_get_parent,
- .set_parent = jh7100_clk_set_parent,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
-};
-
-static const struct clk_ops jh7100_clk_inv_ops = {
- .get_phase = jh7100_clk_get_phase,
- .set_phase = jh7100_clk_set_phase,
- .debug_init = jh7100_clk_debug_init,
-};
-
-const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
-{
- if (max & JH7100_CLK_DIV_MASK) {
- if (max & JH7100_CLK_MUX_MASK) {
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gmd_ops;
- return &jh7100_clk_mdiv_ops;
- }
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gdiv_ops;
- if (max == JH7100_CLK_FRAC_MAX)
- return &jh7100_clk_fdiv_ops;
- return &jh7100_clk_div_ops;
- }
-
- if (max & JH7100_CLK_MUX_MASK) {
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gmux_ops;
- return &jh7100_clk_mux_ops;
- }
-
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gate_ops;
-
- return &jh7100_clk_inv_ops;
-}
-EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
-
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
{
struct jh7100_clk_priv *priv = data;
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh7100.h
index f116be5740a5..a8ba6e25b5ce 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.h
+++ b/drivers/clk/starfive/clk-starfive-jh7100.h
@@ -4,6 +4,8 @@
#include <linux/bits.h>
#include <linux/clk-provider.h>
+#include <linux/device.h>
+#include <linux/spinlock.h>
/* register fields */
#define JH7100_CLK_ENABLE BIT(31)
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c
new file mode 100644
index 000000000000..6c07b61b4a32
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7100 Clock Generator Driver
+ *
+ * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/io.h>
+
+#include "clk-starfive-jh7100.h"
+
+static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
+{
+ return container_of(hw, struct jh7100_clk, hw);
+}
+
+static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
+{
+ return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
+}
+
+static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
+{
+ struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
+ void __iomem *reg = priv->base + 4 * clk->idx;
+
+ return readl_relaxed(reg);
+}
+
+static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
+{
+ struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
+ void __iomem *reg = priv->base + 4 * clk->idx;
+ unsigned long flags;
+
+ spin_lock_irqsave(&priv->rmw_lock, flags);
+ value |= readl_relaxed(reg) & ~mask;
+ writel_relaxed(value, reg);
+ spin_unlock_irqrestore(&priv->rmw_lock, flags);
+}
+
+static int jh7100_clk_enable(struct clk_hw *hw)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+
+ jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
+ return 0;
+}
+
+static void jh7100_clk_disable(struct clk_hw *hw)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+
+ jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
+}
+
+static int jh7100_clk_is_enabled(struct clk_hw *hw)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+
+ return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
+}
+
+static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
+
+ return div ? parent_rate / div : 0;
+}
+
+static int jh7100_clk_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ unsigned long parent = req->best_parent_rate;
+ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+ unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
+ unsigned long result = parent / div;
+
+ /*
+ * we want the result clamped by min_rate and max_rate if possible:
+ * case 1: div hits the max divider value, which means it's less than
+ * parent / rate, so the result is greater than rate and min_rate in
+ * particular. we can't do anything about result > max_rate because the
+ * divider doesn't go any further.
+ * case 2: div = DIV_ROUND_UP(parent, rate) which means the result is
+ * always lower or equal to rate and max_rate. however the result may
+ * turn out lower than min_rate, but then the next higher rate is fine:
+ * div - 1 = ceil(parent / rate) - 1 < parent / rate
+ * and thus
+ * min_rate <= rate < parent / (div - 1)
+ */
+ if (result < req->min_rate && div > 1)
+ result = parent / (div - 1);
+
+ req->rate = result;
+ return 0;
+}
+
+static int jh7100_clk_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
+ 1UL, (unsigned long)clk->max_div);
+
+ jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
+ return 0;
+}
+
+static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ u32 reg = jh7100_clk_reg_get(clk);
+ unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
+ ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
+
+ return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
+}
+
+static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ unsigned long parent100 = 100 * req->best_parent_rate;
+ unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
+ unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
+ JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
+ unsigned long result = parent100 / div100;
+
+ /* clamp the result as in jh7100_clk_determine_rate() above */
+ if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
+ result = parent100 / (div100 + 1);
+ if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
+ result = parent100 / (div100 - 1);
+
+ req->rate = result;
+ return 0;
+}
+
+static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
+ JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
+ u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
+
+ jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
+ return 0;
+}
+
+static u8 jh7100_clk_get_parent(struct clk_hw *hw)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ u32 value = jh7100_clk_reg_get(clk);
+
+ return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
+}
+
+static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
+
+ jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
+ return 0;
+}
+
+static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ return clk_mux_determine_rate_flags(hw, req, 0);
+}
+
+static int jh7100_clk_get_phase(struct clk_hw *hw)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ u32 value = jh7100_clk_reg_get(clk);
+
+ return (value & JH7100_CLK_INVERT) ? 180 : 0;
+}
+
+static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
+{
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ u32 value;
+
+ if (degrees == 0)
+ value = 0;
+ else if (degrees == 180)
+ value = JH7100_CLK_INVERT;
+ else
+ return -EINVAL;
+
+ jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ static const struct debugfs_reg32 jh7100_clk_reg = {
+ .name = "CTRL",
+ .offset = 0,
+ };
+ struct jh7100_clk *clk = jh7100_clk_from(hw);
+ struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
+ struct debugfs_regset32 *regset;
+
+ regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
+ if (!regset)
+ return;
+
+ regset->regs = &jh7100_clk_reg;
+ regset->nregs = 1;
+ regset->base = priv->base + 4 * clk->idx;
+
+ debugfs_create_regset32("registers", 0400, dentry, regset);
+}
+#else
+#define jh7100_clk_debug_init NULL
+#endif
+
+static const struct clk_ops jh7100_clk_gate_ops = {
+ .enable = jh7100_clk_enable,
+ .disable = jh7100_clk_disable,
+ .is_enabled = jh7100_clk_is_enabled,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_div_ops = {
+ .recalc_rate = jh7100_clk_recalc_rate,
+ .determine_rate = jh7100_clk_determine_rate,
+ .set_rate = jh7100_clk_set_rate,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_fdiv_ops = {
+ .recalc_rate = jh7100_clk_frac_recalc_rate,
+ .determine_rate = jh7100_clk_frac_determine_rate,
+ .set_rate = jh7100_clk_frac_set_rate,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_gdiv_ops = {
+ .enable = jh7100_clk_enable,
+ .disable = jh7100_clk_disable,
+ .is_enabled = jh7100_clk_is_enabled,
+ .recalc_rate = jh7100_clk_recalc_rate,
+ .determine_rate = jh7100_clk_determine_rate,
+ .set_rate = jh7100_clk_set_rate,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_mux_ops = {
+ .determine_rate = jh7100_clk_mux_determine_rate,
+ .set_parent = jh7100_clk_set_parent,
+ .get_parent = jh7100_clk_get_parent,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_gmux_ops = {
+ .enable = jh7100_clk_enable,
+ .disable = jh7100_clk_disable,
+ .is_enabled = jh7100_clk_is_enabled,
+ .determine_rate = jh7100_clk_mux_determine_rate,
+ .set_parent = jh7100_clk_set_parent,
+ .get_parent = jh7100_clk_get_parent,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_mdiv_ops = {
+ .recalc_rate = jh7100_clk_recalc_rate,
+ .determine_rate = jh7100_clk_determine_rate,
+ .get_parent = jh7100_clk_get_parent,
+ .set_parent = jh7100_clk_set_parent,
+ .set_rate = jh7100_clk_set_rate,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_gmd_ops = {
+ .enable = jh7100_clk_enable,
+ .disable = jh7100_clk_disable,
+ .is_enabled = jh7100_clk_is_enabled,
+ .recalc_rate = jh7100_clk_recalc_rate,
+ .determine_rate = jh7100_clk_determine_rate,
+ .get_parent = jh7100_clk_get_parent,
+ .set_parent = jh7100_clk_set_parent,
+ .set_rate = jh7100_clk_set_rate,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+static const struct clk_ops jh7100_clk_inv_ops = {
+ .get_phase = jh7100_clk_get_phase,
+ .set_phase = jh7100_clk_set_phase,
+ .debug_init = jh7100_clk_debug_init,
+};
+
+const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
+{
+ if (max & JH7100_CLK_DIV_MASK) {
+ if (max & JH7100_CLK_MUX_MASK) {
+ if (max & JH7100_CLK_ENABLE)
+ return &jh7100_clk_gmd_ops;
+ return &jh7100_clk_mdiv_ops;
+ }
+ if (max & JH7100_CLK_ENABLE)
+ return &jh7100_clk_gdiv_ops;
+ if (max == JH7100_CLK_FRAC_MAX)
+ return &jh7100_clk_fdiv_ops;
+ return &jh7100_clk_div_ops;
+ }
+
+ if (max & JH7100_CLK_MUX_MASK) {
+ if (max & JH7100_CLK_ENABLE)
+ return &jh7100_clk_gmux_ops;
+ return &jh7100_clk_mux_ops;
+ }
+
+ if (max & JH7100_CLK_ENABLE)
+ return &jh7100_clk_gate_ops;
+
+ return &jh7100_clk_inv_ops;
+}
+EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-02-21 2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
` (19 subsequent siblings)
21 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making
the code to be common.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../clk/starfive/{clk-starfive-jh7100.h => clk-starfive-jh71x0.h} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename drivers/clk/starfive/{clk-starfive-jh7100.h => clk-starfive-jh71x0.h} (100%)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
similarity index 100%
rename from drivers/clk/starfive/clk-starfive-jh7100.h
rename to drivers/clk/starfive/clk-starfive-jh71x0.h
--
2.38.1
^ permalink raw reply [flat|nested] 71+ messages in thread
* [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-02-21 2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-02-21 2:46 ` [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers Hal Feng
` (18 subsequent siblings)
21 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Rename some variables from "jh7100" or "JH7100" to "jh71x0"
or "JH71X0".
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../clk/starfive/clk-starfive-jh7100-audio.c | 74 ++--
drivers/clk/starfive/clk-starfive-jh7100.c | 388 +++++++++---------
drivers/clk/starfive/clk-starfive-jh71x0.c | 284 ++++++-------
drivers/clk/starfive/clk-starfive-jh71x0.h | 72 ++--
4 files changed, 409 insertions(+), 409 deletions(-)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100-audio.c b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
index 8473a65e219b..02aefb7264f8 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100-audio.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100-audio.c
@@ -16,7 +16,7 @@
#include <dt-bindings/clock/starfive-jh7100-audio.h>
-#include "clk-starfive-jh7100.h"
+#include "clk-starfive-jh71x0.h"
/* external clocks */
#define JH7100_AUDCLK_AUDIO_SRC (JH7100_AUDCLK_END + 0)
@@ -28,66 +28,66 @@
#define JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD (JH7100_AUDCLK_END + 6)
#define JH7100_AUDCLK_VAD_INTMEM (JH7100_AUDCLK_END + 7)
-static const struct jh7100_clk_data jh7100_audclk_data[] = {
- JH7100__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
+static const struct jh71x0_clk_data jh7100_audclk_data[] = {
+ JH71X0__GMD(JH7100_AUDCLK_ADC_MCLK, "adc_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
- JH7100__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
+ JH71X0__GMD(JH7100_AUDCLK_I2S1_MCLK, "i2s1_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
- JH7100_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
+ JH71X0_GATE(JH7100_AUDCLK_I2SADC_APB, "i2sadc_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH71X0_MDIV(JH7100_AUDCLK_I2SADC_BCLK, "i2sadc_bclk", 31, 2,
JH7100_AUDCLK_ADC_MCLK,
JH7100_AUDCLK_I2SADC_BCLK_IOPAD),
- JH7100__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
- JH7100_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
+ JH71X0__INV(JH7100_AUDCLK_I2SADC_BCLK_N, "i2sadc_bclk_n", JH7100_AUDCLK_I2SADC_BCLK),
+ JH71X0_MDIV(JH7100_AUDCLK_I2SADC_LRCLK, "i2sadc_lrclk", 63, 3,
JH7100_AUDCLK_I2SADC_BCLK_N,
JH7100_AUDCLK_I2SADC_LRCLK_IOPAD,
JH7100_AUDCLK_I2SADC_BCLK),
- JH7100_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
+ JH71X0_GATE(JH7100_AUDCLK_PDM_APB, "pdm_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH71X0__GMD(JH7100_AUDCLK_PDM_MCLK, "pdm_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
- JH7100_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
+ JH71X0_GATE(JH7100_AUDCLK_I2SVAD_APB, "i2svad_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH71X0__GMD(JH7100_AUDCLK_SPDIF, "spdif", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
- JH7100_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
+ JH71X0_GATE(JH7100_AUDCLK_SPDIF_APB, "spdif_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH71X0_GATE(JH7100_AUDCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH71X0__GMD(JH7100_AUDCLK_DAC_MCLK, "dac_mclk", 0, 15, 2,
JH7100_AUDCLK_AUDIO_SRC,
JH7100_AUDCLK_AUDIO_12288),
- JH7100_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
+ JH71X0_GATE(JH7100_AUDCLK_I2SDAC_APB, "i2sdac_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_BCLK, "i2sdac_bclk", 31, 2,
JH7100_AUDCLK_DAC_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH7100__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
- JH7100_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
+ JH71X0__INV(JH7100_AUDCLK_I2SDAC_BCLK_N, "i2sdac_bclk_n", JH7100_AUDCLK_I2SDAC_BCLK),
+ JH71X0_MDIV(JH7100_AUDCLK_I2SDAC_LRCLK, "i2sdac_lrclk", 31, 2,
JH7100_AUDCLK_I2S1_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH7100_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
+ JH71X0_GATE(JH7100_AUDCLK_I2S1_APB, "i2s1_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH71X0_MDIV(JH7100_AUDCLK_I2S1_BCLK, "i2s1_bclk", 31, 2,
JH7100_AUDCLK_I2S1_MCLK,
JH7100_AUDCLK_I2SDAC_BCLK_IOPAD),
- JH7100__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
- JH7100_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
+ JH71X0__INV(JH7100_AUDCLK_I2S1_BCLK_N, "i2s1_bclk_n", JH7100_AUDCLK_I2S1_BCLK),
+ JH71X0_MDIV(JH7100_AUDCLK_I2S1_LRCLK, "i2s1_lrclk", 63, 3,
JH7100_AUDCLK_I2S1_BCLK_N,
JH7100_AUDCLK_I2SDAC_LRCLK_IOPAD),
- JH7100_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
- JH7100__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
- JH7100_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
- JH7100_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
- JH7100_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
- JH7100_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
- JH7100__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
- JH7100__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
+ JH71X0_GATE(JH7100_AUDCLK_I2SDAC16K_APB, "i2s1dac16k_apb", 0, JH7100_AUDCLK_APB0_BUS),
+ JH71X0__DIV(JH7100_AUDCLK_APB0_BUS, "apb0_bus", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+ JH71X0_GATE(JH7100_AUDCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7100_AUDCLK_DOM7AHB_BUS),
+ JH71X0_GATE(JH7100_AUDCLK_USB_APB, "usb_apb", CLK_IGNORE_UNUSED, JH7100_AUDCLK_APB_EN),
+ JH71X0_GDIV(JH7100_AUDCLK_USB_LPM, "usb_lpm", CLK_IGNORE_UNUSED, 4, JH7100_AUDCLK_USB_APB),
+ JH71X0_GDIV(JH7100_AUDCLK_USB_STB, "usb_stb", CLK_IGNORE_UNUSED, 3, JH7100_AUDCLK_USB_APB),
+ JH71X0__DIV(JH7100_AUDCLK_APB_EN, "apb_en", 8, JH7100_AUDCLK_DOM7AHB_BUS),
+ JH71X0__MUX(JH7100_AUDCLK_VAD_MEM, "vad_mem", 2,
JH7100_AUDCLK_VAD_INTMEM,
JH7100_AUDCLK_AUDIO_12288),
};
static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh7100_clk_priv *priv = data;
+ struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7100_AUDCLK_END)
@@ -98,7 +98,7 @@ static struct clk_hw *jh7100_audclk_get(struct of_phandle_args *clkspec, void *d
static int jh7100_audclk_probe(struct platform_device *pdev)
{
- struct jh7100_clk_priv *priv;
+ struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
@@ -117,12 +117,12 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_audclk_data[idx].name,
- .ops = starfive_jh7100_clk_ops(max),
+ .ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7100_audclk_data[idx].flags,
};
- struct jh7100_clk *clk = &priv->reg[idx];
+ struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
@@ -140,7 +140,7 @@ static int jh7100_audclk_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH7100_CLK_DIV_MASK;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh7100.c b/drivers/clk/starfive/clk-starfive-jh7100.c
index eea52f16af0d..bcc9acdd5936 100644
--- a/drivers/clk/starfive/clk-starfive-jh7100.c
+++ b/drivers/clk/starfive/clk-starfive-jh7100.c
@@ -15,7 +15,7 @@
#include <dt-bindings/clock/starfive-jh7100.h>
-#include "clk-starfive-jh7100.h"
+#include "clk-starfive-jh71x0.h"
/* external clocks */
#define JH7100_CLK_OSC_SYS (JH7100_CLK_END + 0)
@@ -23,250 +23,250 @@
#define JH7100_CLK_GMAC_RMII_REF (JH7100_CLK_END + 2)
#define JH7100_CLK_GMAC_GR_MII_RX (JH7100_CLK_END + 3)
-static const struct jh7100_clk_data jh7100_clk_data[] __initconst = {
- JH7100__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
+static const struct jh71x0_clk_data jh7100_clk_data[] __initconst = {
+ JH71X0__MUX(JH7100_CLK_CPUNDBUS_ROOT, "cpundbus_root", 4,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
+ JH71X0__MUX(JH7100_CLK_DLA_ROOT, "dla_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
+ JH71X0__MUX(JH7100_CLK_DSP_ROOT, "dsp_root", 4,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
+ JH71X0__MUX(JH7100_CLK_GMACUSB_ROOT, "gmacusb_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
+ JH71X0__MUX(JH7100_CLK_PERH0_ROOT, "perh0_root", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT),
- JH7100__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
+ JH71X0__MUX(JH7100_CLK_PERH1_ROOT, "perh1_root", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
+ JH71X0__MUX(JH7100_CLK_VIN_ROOT, "vin_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
+ JH71X0__MUX(JH7100_CLK_VOUT_ROOT, "vout_root", 3,
JH7100_CLK_OSC_AUD,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL2_OUT),
- JH7100_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
- JH7100__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
+ JH71X0_GDIV(JH7100_CLK_AUDIO_ROOT, "audio_root", 0, 8, JH7100_CLK_PLL0_OUT),
+ JH71X0__MUX(JH7100_CLK_CDECHIFI4_ROOT, "cdechifi4_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL1_OUT,
JH7100_CLK_PLL2_OUT),
- JH7100__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
+ JH71X0__MUX(JH7100_CLK_CDEC_ROOT, "cdec_root", 3,
JH7100_CLK_OSC_SYS,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL1_OUT),
- JH7100__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
+ JH71X0__MUX(JH7100_CLK_VOUTBUS_ROOT, "voutbus_root", 3,
JH7100_CLK_OSC_AUD,
JH7100_CLK_PLL0_OUT,
JH7100_CLK_PLL2_OUT),
- JH7100__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
- JH7100__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
- JH7100__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
- JH7100__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
- JH7100_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
- JH7100_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
- JH7100__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
+ JH71X0__DIV(JH7100_CLK_CPUNBUS_ROOT_DIV, "cpunbus_root_div", 2, JH7100_CLK_CPUNDBUS_ROOT),
+ JH71X0__DIV(JH7100_CLK_DSP_ROOT_DIV, "dsp_root_div", 4, JH7100_CLK_DSP_ROOT),
+ JH71X0__DIV(JH7100_CLK_PERH0_SRC, "perh0_src", 4, JH7100_CLK_PERH0_ROOT),
+ JH71X0__DIV(JH7100_CLK_PERH1_SRC, "perh1_src", 4, JH7100_CLK_PERH1_ROOT),
+ JH71X0_GDIV(JH7100_CLK_PLL0_TESTOUT, "pll0_testout", 0, 31, JH7100_CLK_PERH0_SRC),
+ JH71X0_GDIV(JH7100_CLK_PLL1_TESTOUT, "pll1_testout", 0, 31, JH7100_CLK_DLA_ROOT),
+ JH71X0_GDIV(JH7100_CLK_PLL2_TESTOUT, "pll2_testout", 0, 31, JH7100_CLK_PERH1_SRC),
+ JH71X0__MUX(JH7100_CLK_PLL2_REF, "pll2_refclk", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_OSC_AUD),
- JH7100__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
- JH7100__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
- JH7100_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
- JH7100_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
- JH7100_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
- JH7100_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
- JH7100_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
- JH7100_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
- JH7100_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
- JH7100_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
- JH7100_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
- JH7100_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
- JH7100__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
- JH7100__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
- JH7100_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
- JH7100_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
- JH7100_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
- JH7100_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
- JH7100_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
- JH7100__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
- JH7100_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
- JH7100_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
- JH7100_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
- JH7100_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
- JH7100_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
- JH7100_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
- JH7100_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
+ JH71X0__DIV(JH7100_CLK_CPU_CORE, "cpu_core", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ JH71X0__DIV(JH7100_CLK_CPU_AXI, "cpu_axi", 8, JH7100_CLK_CPU_CORE),
+ JH71X0__DIV(JH7100_CLK_AHB_BUS, "ahb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ JH71X0__DIV(JH7100_CLK_APB1_BUS, "apb1_bus", 8, JH7100_CLK_AHB_BUS),
+ JH71X0__DIV(JH7100_CLK_APB2_BUS, "apb2_bus", 8, JH7100_CLK_AHB_BUS),
+ JH71X0_GATE(JH7100_CLK_DOM3AHB_BUS, "dom3ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
+ JH71X0_GATE(JH7100_CLK_DOM7AHB_BUS, "dom7ahb_bus", CLK_IS_CRITICAL, JH7100_CLK_AHB_BUS),
+ JH71X0_GATE(JH7100_CLK_U74_CORE0, "u74_core0", CLK_IS_CRITICAL, JH7100_CLK_CPU_CORE),
+ JH71X0_GDIV(JH7100_CLK_U74_CORE1, "u74_core1", CLK_IS_CRITICAL, 8, JH7100_CLK_CPU_CORE),
+ JH71X0_GATE(JH7100_CLK_U74_AXI, "u74_axi", CLK_IS_CRITICAL, JH7100_CLK_CPU_AXI),
+ JH71X0_GATE(JH7100_CLK_U74RTC_TOGGLE, "u74rtc_toggle", CLK_IS_CRITICAL, JH7100_CLK_OSC_SYS),
+ JH71X0_GATE(JH7100_CLK_SGDMA2P_AXI, "sgdma2p_axi", 0, JH7100_CLK_CPU_AXI),
+ JH71X0_GATE(JH7100_CLK_DMA2PNOC_AXI, "dma2pnoc_axi", 0, JH7100_CLK_CPU_AXI),
+ JH71X0_GATE(JH7100_CLK_SGDMA2P_AHB, "sgdma2p_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0__DIV(JH7100_CLK_DLA_BUS, "dla_bus", 4, JH7100_CLK_DLA_ROOT),
+ JH71X0_GATE(JH7100_CLK_DLA_AXI, "dla_axi", 0, JH7100_CLK_DLA_BUS),
+ JH71X0_GATE(JH7100_CLK_DLANOC_AXI, "dlanoc_axi", 0, JH7100_CLK_DLA_BUS),
+ JH71X0_GATE(JH7100_CLK_DLA_APB, "dla_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_VP6_CORE, "vp6_core", 0, 4, JH7100_CLK_DSP_ROOT_DIV),
+ JH71X0__DIV(JH7100_CLK_VP6BUS_SRC, "vp6bus_src", 4, JH7100_CLK_DSP_ROOT),
+ JH71X0_GDIV(JH7100_CLK_VP6_AXI, "vp6_axi", 0, 4, JH7100_CLK_VP6BUS_SRC),
+ JH71X0__DIV(JH7100_CLK_VCDECBUS_SRC, "vcdecbus_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
+ JH71X0__DIV(JH7100_CLK_VDEC_BUS, "vdec_bus", 8, JH7100_CLK_VCDECBUS_SRC),
+ JH71X0_GATE(JH7100_CLK_VDEC_AXI, "vdec_axi", 0, JH7100_CLK_VDEC_BUS),
+ JH71X0_GATE(JH7100_CLK_VDECBRG_MAIN, "vdecbrg_mainclk", 0, JH7100_CLK_VDEC_BUS),
+ JH71X0_GDIV(JH7100_CLK_VDEC_BCLK, "vdec_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
+ JH71X0_GDIV(JH7100_CLK_VDEC_CCLK, "vdec_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
+ JH71X0_GATE(JH7100_CLK_VDEC_APB, "vdec_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_JPEG_AXI, "jpeg_axi", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ JH71X0_GDIV(JH7100_CLK_JPEG_CCLK, "jpeg_cclk", 0, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ JH71X0_GATE(JH7100_CLK_JPEG_APB, "jpeg_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_GC300_2X, "gc300_2x", 0, 8, JH7100_CLK_CDECHIFI4_ROOT),
+ JH71X0_GATE(JH7100_CLK_GC300_AHB, "gc300_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0__DIV(JH7100_CLK_JPCGC300_AXIBUS, "jpcgc300_axibus", 8, JH7100_CLK_VCDECBUS_SRC),
+ JH71X0_GATE(JH7100_CLK_GC300_AXI, "gc300_axi", 0, JH7100_CLK_JPCGC300_AXIBUS),
+ JH71X0_GATE(JH7100_CLK_JPCGC300_MAIN, "jpcgc300_mainclk", 0, JH7100_CLK_JPCGC300_AXIBUS),
+ JH71X0__DIV(JH7100_CLK_VENC_BUS, "venc_bus", 8, JH7100_CLK_VCDECBUS_SRC),
+ JH71X0_GATE(JH7100_CLK_VENC_AXI, "venc_axi", 0, JH7100_CLK_VENC_BUS),
+ JH71X0_GATE(JH7100_CLK_VENCBRG_MAIN, "vencbrg_mainclk", 0, JH7100_CLK_VENC_BUS),
+ JH71X0_GDIV(JH7100_CLK_VENC_BCLK, "venc_bclk", 0, 8, JH7100_CLK_VCDECBUS_SRC),
+ JH71X0_GDIV(JH7100_CLK_VENC_CCLK, "venc_cclk", 0, 8, JH7100_CLK_CDEC_ROOT),
+ JH71X0_GATE(JH7100_CLK_VENC_APB, "venc_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV2, "ddrpll_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_PLL1_OUT),
+ JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV4, "ddrpll_div4", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV2),
+ JH71X0_GDIV(JH7100_CLK_DDRPLL_DIV8, "ddrpll_div8", CLK_IS_CRITICAL, 2, JH7100_CLK_DDRPLL_DIV4),
+ JH71X0_GDIV(JH7100_CLK_DDROSC_DIV2, "ddrosc_div2", CLK_IS_CRITICAL, 2, JH7100_CLK_OSC_SYS),
+ JH71X0_GMUX(JH7100_CLK_DDRC0, "ddrc0", CLK_IS_CRITICAL, 4,
JH7100_CLK_DDROSC_DIV2,
JH7100_CLK_DDRPLL_DIV2,
JH7100_CLK_DDRPLL_DIV4,
JH7100_CLK_DDRPLL_DIV8),
- JH7100_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
+ JH71X0_GMUX(JH7100_CLK_DDRC1, "ddrc1", CLK_IS_CRITICAL, 4,
JH7100_CLK_DDROSC_DIV2,
JH7100_CLK_DDRPLL_DIV2,
JH7100_CLK_DDRPLL_DIV4,
JH7100_CLK_DDRPLL_DIV8),
- JH7100_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
- JH7100_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
- JH7100__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
+ JH71X0_GATE(JH7100_CLK_DDRPHY_APB, "ddrphy_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0__DIV(JH7100_CLK_NOC_ROB, "noc_rob", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ JH71X0__DIV(JH7100_CLK_NOC_COG, "noc_cog", 8, JH7100_CLK_DLA_ROOT),
+ JH71X0_GATE(JH7100_CLK_NNE_AHB, "nne_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0__DIV(JH7100_CLK_NNEBUS_SRC1, "nnebus_src1", 4, JH7100_CLK_DSP_ROOT),
+ JH71X0__MUX(JH7100_CLK_NNE_BUS, "nne_bus", 2,
JH7100_CLK_CPU_AXI,
JH7100_CLK_NNEBUS_SRC1),
- JH7100_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
- JH7100_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
- JH7100_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
- JH7100_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
- JH7100__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
- JH7100__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
- JH7100_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
- JH7100__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
- JH7100_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
- JH7100_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
- JH7100__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
- JH7100_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
- JH7100_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
- JH7100_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
- JH7100_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
- JH7100__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
- JH7100_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
- JH7100_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
- JH7100__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
+ JH71X0_GATE(JH7100_CLK_NNE_AXI, "nne_axi", 0, JH7100_CLK_NNE_BUS),
+ JH71X0_GATE(JH7100_CLK_NNENOC_AXI, "nnenoc_axi", 0, JH7100_CLK_NNE_BUS),
+ JH71X0_GATE(JH7100_CLK_DLASLV_AXI, "dlaslv_axi", 0, JH7100_CLK_NNE_BUS),
+ JH71X0_GATE(JH7100_CLK_DSPX2C_AXI, "dspx2c_axi", CLK_IS_CRITICAL, JH7100_CLK_NNE_BUS),
+ JH71X0__DIV(JH7100_CLK_HIFI4_SRC, "hifi4_src", 4, JH7100_CLK_CDECHIFI4_ROOT),
+ JH71X0__DIV(JH7100_CLK_HIFI4_COREFREE, "hifi4_corefree", 8, JH7100_CLK_HIFI4_SRC),
+ JH71X0_GATE(JH7100_CLK_HIFI4_CORE, "hifi4_core", 0, JH7100_CLK_HIFI4_COREFREE),
+ JH71X0__DIV(JH7100_CLK_HIFI4_BUS, "hifi4_bus", 8, JH7100_CLK_HIFI4_COREFREE),
+ JH71X0_GATE(JH7100_CLK_HIFI4_AXI, "hifi4_axi", 0, JH7100_CLK_HIFI4_BUS),
+ JH71X0_GATE(JH7100_CLK_HIFI4NOC_AXI, "hifi4noc_axi", 0, JH7100_CLK_HIFI4_BUS),
+ JH71X0__DIV(JH7100_CLK_SGDMA1P_BUS, "sgdma1p_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ JH71X0_GATE(JH7100_CLK_SGDMA1P_AXI, "sgdma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+ JH71X0_GATE(JH7100_CLK_DMA1P_AXI, "dma1p_axi", 0, JH7100_CLK_SGDMA1P_BUS),
+ JH71X0_GDIV(JH7100_CLK_X2C_AXI, "x2c_axi", CLK_IS_CRITICAL, 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ JH71X0__DIV(JH7100_CLK_USB_BUS, "usb_bus", 8, JH7100_CLK_CPUNBUS_ROOT_DIV),
+ JH71X0_GATE(JH7100_CLK_USB_AXI, "usb_axi", 0, JH7100_CLK_USB_BUS),
+ JH71X0_GATE(JH7100_CLK_USBNOC_AXI, "usbnoc_axi", 0, JH7100_CLK_USB_BUS),
+ JH71X0__DIV(JH7100_CLK_USBPHY_ROOTDIV, "usbphy_rootdiv", 4, JH7100_CLK_GMACUSB_ROOT),
+ JH71X0_GDIV(JH7100_CLK_USBPHY_125M, "usbphy_125m", 0, 8, JH7100_CLK_USBPHY_ROOTDIV),
+ JH71X0_GDIV(JH7100_CLK_USBPHY_PLLDIV25M, "usbphy_plldiv25m", 0, 32, JH7100_CLK_USBPHY_ROOTDIV),
+ JH71X0__MUX(JH7100_CLK_USBPHY_25M, "usbphy_25m", 2,
JH7100_CLK_OSC_SYS,
JH7100_CLK_USBPHY_PLLDIV25M),
- JH7100_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
- JH7100_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
- JH7100_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
- JH7100_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
- JH7100__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
- JH7100_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
- JH7100_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
- JH7100_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
- JH7100__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
- JH7100_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
- JH7100_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
- JH7100__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
- JH7100_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
- JH7100_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
- JH7100_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
- JH7100__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
- JH7100__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
- JH7100_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
- JH7100_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
- JH7100_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
- JH7100__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
- JH7100_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
- JH7100__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
- JH7100_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
- JH7100_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
- JH7100_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
- JH7100_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
- JH7100_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
- JH7100__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
+ JH71X0_FDIV(JH7100_CLK_AUDIO_DIV, "audio_div", JH7100_CLK_AUDIO_ROOT),
+ JH71X0_GATE(JH7100_CLK_AUDIO_SRC, "audio_src", 0, JH7100_CLK_AUDIO_DIV),
+ JH71X0_GATE(JH7100_CLK_AUDIO_12288, "audio_12288", 0, JH7100_CLK_OSC_AUD),
+ JH71X0_GDIV(JH7100_CLK_VIN_SRC, "vin_src", 0, 4, JH7100_CLK_VIN_ROOT),
+ JH71X0__DIV(JH7100_CLK_ISP0_BUS, "isp0_bus", 8, JH7100_CLK_VIN_SRC),
+ JH71X0_GATE(JH7100_CLK_ISP0_AXI, "isp0_axi", 0, JH7100_CLK_ISP0_BUS),
+ JH71X0_GATE(JH7100_CLK_ISP0NOC_AXI, "isp0noc_axi", 0, JH7100_CLK_ISP0_BUS),
+ JH71X0_GATE(JH7100_CLK_ISPSLV_AXI, "ispslv_axi", 0, JH7100_CLK_ISP0_BUS),
+ JH71X0__DIV(JH7100_CLK_ISP1_BUS, "isp1_bus", 8, JH7100_CLK_VIN_SRC),
+ JH71X0_GATE(JH7100_CLK_ISP1_AXI, "isp1_axi", 0, JH7100_CLK_ISP1_BUS),
+ JH71X0_GATE(JH7100_CLK_ISP1NOC_AXI, "isp1noc_axi", 0, JH7100_CLK_ISP1_BUS),
+ JH71X0__DIV(JH7100_CLK_VIN_BUS, "vin_bus", 8, JH7100_CLK_VIN_SRC),
+ JH71X0_GATE(JH7100_CLK_VIN_AXI, "vin_axi", 0, JH7100_CLK_VIN_BUS),
+ JH71X0_GATE(JH7100_CLK_VINNOC_AXI, "vinnoc_axi", 0, JH7100_CLK_VIN_BUS),
+ JH71X0_GDIV(JH7100_CLK_VOUT_SRC, "vout_src", 0, 4, JH7100_CLK_VOUT_ROOT),
+ JH71X0__DIV(JH7100_CLK_DISPBUS_SRC, "dispbus_src", 4, JH7100_CLK_VOUTBUS_ROOT),
+ JH71X0__DIV(JH7100_CLK_DISP_BUS, "disp_bus", 4, JH7100_CLK_DISPBUS_SRC),
+ JH71X0_GATE(JH7100_CLK_DISP_AXI, "disp_axi", 0, JH7100_CLK_DISP_BUS),
+ JH71X0_GATE(JH7100_CLK_DISPNOC_AXI, "dispnoc_axi", 0, JH7100_CLK_DISP_BUS),
+ JH71X0_GATE(JH7100_CLK_SDIO0_AHB, "sdio0_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0_GDIV(JH7100_CLK_SDIO0_CCLKINT, "sdio0_cclkint", 0, 24, JH7100_CLK_PERH0_SRC),
+ JH71X0__INV(JH7100_CLK_SDIO0_CCLKINT_INV, "sdio0_cclkint_inv", JH7100_CLK_SDIO0_CCLKINT),
+ JH71X0_GATE(JH7100_CLK_SDIO1_AHB, "sdio1_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0_GDIV(JH7100_CLK_SDIO1_CCLKINT, "sdio1_cclkint", 0, 24, JH7100_CLK_PERH1_SRC),
+ JH71X0__INV(JH7100_CLK_SDIO1_CCLKINT_INV, "sdio1_cclkint_inv", JH7100_CLK_SDIO1_CCLKINT),
+ JH71X0_GATE(JH7100_CLK_GMAC_AHB, "gmac_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0__DIV(JH7100_CLK_GMAC_ROOT_DIV, "gmac_root_div", 8, JH7100_CLK_GMACUSB_ROOT),
+ JH71X0_GDIV(JH7100_CLK_GMAC_PTP_REF, "gmac_ptp_refclk", 0, 31, JH7100_CLK_GMAC_ROOT_DIV),
+ JH71X0_GDIV(JH7100_CLK_GMAC_GTX, "gmac_gtxclk", 0, 255, JH7100_CLK_GMAC_ROOT_DIV),
+ JH71X0_GDIV(JH7100_CLK_GMAC_RMII_TX, "gmac_rmii_txclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+ JH71X0_GDIV(JH7100_CLK_GMAC_RMII_RX, "gmac_rmii_rxclk", 0, 8, JH7100_CLK_GMAC_RMII_REF),
+ JH71X0__MUX(JH7100_CLK_GMAC_TX, "gmac_tx", 3,
JH7100_CLK_GMAC_GTX,
JH7100_CLK_GMAC_TX_INV,
JH7100_CLK_GMAC_RMII_TX),
- JH7100__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
- JH7100__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
+ JH71X0__INV(JH7100_CLK_GMAC_TX_INV, "gmac_tx_inv", JH7100_CLK_GMAC_TX),
+ JH71X0__MUX(JH7100_CLK_GMAC_RX_PRE, "gmac_rx_pre", 2,
JH7100_CLK_GMAC_GR_MII_RX,
JH7100_CLK_GMAC_RMII_RX),
- JH7100__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
- JH7100_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
- JH7100_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
- JH7100_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
- JH7100_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
- JH7100_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
- JH7100_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
- JH7100_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
- JH7100_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
- JH7100_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
- JH7100_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
- JH7100_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
- JH7100_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
- JH7100_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0__INV(JH7100_CLK_GMAC_RX_INV, "gmac_rx_inv", JH7100_CLK_GMAC_RX_PRE),
+ JH71X0_GATE(JH7100_CLK_GMAC_RMII, "gmac_rmii", 0, JH7100_CLK_GMAC_RMII_REF),
+ JH71X0_GDIV(JH7100_CLK_GMAC_TOPHYREF, "gmac_tophyref", 0, 127, JH7100_CLK_GMAC_ROOT_DIV),
+ JH71X0_GATE(JH7100_CLK_SPI2AHB_AHB, "spi2ahb_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0_GDIV(JH7100_CLK_SPI2AHB_CORE, "spi2ahb_core", 0, 31, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_EZMASTER_AHB, "ezmaster_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0_GATE(JH7100_CLK_E24_AHB, "e24_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0_GATE(JH7100_CLK_E24RTC_TOGGLE, "e24rtc_toggle", 0, JH7100_CLK_OSC_SYS),
+ JH71X0_GATE(JH7100_CLK_QSPI_AHB, "qspi_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0_GATE(JH7100_CLK_QSPI_APB, "qspi_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_QSPI_REF, "qspi_refclk", 0, 31, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_SEC_AHB, "sec_ahb", 0, JH7100_CLK_AHB_BUS),
+ JH71X0_GATE(JH7100_CLK_AES, "aes_clk", 0, JH7100_CLK_SEC_AHB),
+ JH71X0_GATE(JH7100_CLK_SHA, "sha_clk", 0, JH7100_CLK_SEC_AHB),
+ JH71X0_GATE(JH7100_CLK_PKA, "pka_clk", 0, JH7100_CLK_SEC_AHB),
+ JH71X0_GATE(JH7100_CLK_TRNG_APB, "trng_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GATE(JH7100_CLK_OTP_APB, "otp_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GATE(JH7100_CLK_UART0_APB, "uart0_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_UART0_CORE, "uart0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ JH71X0_GATE(JH7100_CLK_UART1_APB, "uart1_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_UART1_CORE, "uart1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ JH71X0_GATE(JH7100_CLK_SPI0_APB, "spi0_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_SPI0_CORE, "spi0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ JH71X0_GATE(JH7100_CLK_SPI1_APB, "spi1_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_SPI1_CORE, "spi1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ JH71X0_GATE(JH7100_CLK_I2C0_APB, "i2c0_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_I2C0_CORE, "i2c0_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ JH71X0_GATE(JH7100_CLK_I2C1_APB, "i2c1_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GDIV(JH7100_CLK_I2C1_CORE, "i2c1_core", 0, 63, JH7100_CLK_PERH1_SRC),
+ JH71X0_GATE(JH7100_CLK_GPIO_APB, "gpio_apb", 0, JH7100_CLK_APB1_BUS),
+ JH71X0_GATE(JH7100_CLK_UART2_APB, "uart2_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GDIV(JH7100_CLK_UART2_CORE, "uart2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_UART3_APB, "uart3_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GDIV(JH7100_CLK_UART3_CORE, "uart3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_SPI2_APB, "spi2_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GDIV(JH7100_CLK_SPI2_CORE, "spi2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_SPI3_APB, "spi3_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GDIV(JH7100_CLK_SPI3_CORE, "spi3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_I2C2_APB, "i2c2_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GDIV(JH7100_CLK_I2C2_CORE, "i2c2_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_I2C3_APB, "i2c3_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GDIV(JH7100_CLK_I2C3_CORE, "i2c3_core", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_WDTIMER_APB, "wdtimer_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GDIV(JH7100_CLK_WDT_CORE, "wdt_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GDIV(JH7100_CLK_TIMER0_CORE, "timer0_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GDIV(JH7100_CLK_TIMER1_CORE, "timer1_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GDIV(JH7100_CLK_TIMER2_CORE, "timer2_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GDIV(JH7100_CLK_TIMER3_CORE, "timer3_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GDIV(JH7100_CLK_TIMER4_CORE, "timer4_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GDIV(JH7100_CLK_TIMER5_CORE, "timer5_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GDIV(JH7100_CLK_TIMER6_CORE, "timer6_coreclk", 0, 63, JH7100_CLK_PERH0_SRC),
+ JH71X0_GATE(JH7100_CLK_VP6INTC_APB, "vp6intc_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GATE(JH7100_CLK_PWM_APB, "pwm_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GATE(JH7100_CLK_MSI_APB, "msi_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GATE(JH7100_CLK_TEMP_APB, "temp_apb", 0, JH7100_CLK_APB2_BUS),
+ JH71X0_GDIV(JH7100_CLK_TEMP_SENSE, "temp_sense", 0, 31, JH7100_CLK_OSC_SYS),
+ JH71X0_GATE(JH7100_CLK_SYSERR_APB, "syserr_apb", 0, JH7100_CLK_APB2_BUS),
};
static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data)
{
- struct jh7100_clk_priv *priv = data;
+ struct jh71x0_clk_priv *priv = data;
unsigned int idx = clkspec->args[0];
if (idx < JH7100_CLK_PLL0_OUT)
@@ -280,7 +280,7 @@ static struct clk_hw *jh7100_clk_get(struct of_phandle_args *clkspec, void *data
static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
{
- struct jh7100_clk_priv *priv;
+ struct jh71x0_clk_priv *priv;
unsigned int idx;
int ret;
@@ -314,12 +314,12 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
struct clk_parent_data parents[4] = {};
struct clk_init_data init = {
.name = jh7100_clk_data[idx].name,
- .ops = starfive_jh7100_clk_ops(max),
+ .ops = starfive_jh71x0_clk_ops(max),
.parent_data = parents,
- .num_parents = ((max & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT) + 1,
+ .num_parents = ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
.flags = jh7100_clk_data[idx].flags,
};
- struct jh7100_clk *clk = &priv->reg[idx];
+ struct jh71x0_clk *clk = &priv->reg[idx];
unsigned int i;
for (i = 0; i < init.num_parents; i++) {
@@ -341,7 +341,7 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
clk->hw.init = &init;
clk->idx = idx;
- clk->max_div = max & JH7100_CLK_DIV_MASK;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
ret = devm_clk_hw_register(priv->dev, &clk->hw);
if (ret)
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c
index 6c07b61b4a32..b372083d11c3 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * StarFive JH7100 Clock Generator Driver
+ * StarFive JH71X0 Clock Generator Driver
*
* Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
*/
@@ -10,29 +10,29 @@
#include <linux/device.h>
#include <linux/io.h>
-#include "clk-starfive-jh7100.h"
+#include "clk-starfive-jh71x0.h"
-static struct jh7100_clk *jh7100_clk_from(struct clk_hw *hw)
+static struct jh71x0_clk *jh71x0_clk_from(struct clk_hw *hw)
{
- return container_of(hw, struct jh7100_clk, hw);
+ return container_of(hw, struct jh71x0_clk, hw);
}
-static struct jh7100_clk_priv *jh7100_priv_from(struct jh7100_clk *clk)
+static struct jh71x0_clk_priv *jh71x0_priv_from(struct jh71x0_clk *clk)
{
- return container_of(clk, struct jh7100_clk_priv, reg[clk->idx]);
+ return container_of(clk, struct jh71x0_clk_priv, reg[clk->idx]);
}
-static u32 jh7100_clk_reg_get(struct jh7100_clk *clk)
+static u32 jh71x0_clk_reg_get(struct jh71x0_clk *clk)
{
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
+ struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
void __iomem *reg = priv->base + 4 * clk->idx;
return readl_relaxed(reg);
}
-static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
+static void jh71x0_clk_reg_rmw(struct jh71x0_clk *clk, u32 mask, u32 value)
{
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
+ struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
void __iomem *reg = priv->base + 4 * clk->idx;
unsigned long flags;
@@ -42,41 +42,41 @@ static void jh7100_clk_reg_rmw(struct jh7100_clk *clk, u32 mask, u32 value)
spin_unlock_irqrestore(&priv->rmw_lock, flags);
}
-static int jh7100_clk_enable(struct clk_hw *hw)
+static int jh71x0_clk_enable(struct clk_hw *hw)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, JH7100_CLK_ENABLE);
+ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, JH71X0_CLK_ENABLE);
return 0;
}
-static void jh7100_clk_disable(struct clk_hw *hw)
+static void jh71x0_clk_disable(struct clk_hw *hw)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- jh7100_clk_reg_rmw(clk, JH7100_CLK_ENABLE, 0);
+ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_ENABLE, 0);
}
-static int jh7100_clk_is_enabled(struct clk_hw *hw)
+static int jh71x0_clk_is_enabled(struct clk_hw *hw)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
- return !!(jh7100_clk_reg_get(clk) & JH7100_CLK_ENABLE);
+ return !!(jh71x0_clk_reg_get(clk) & JH71X0_CLK_ENABLE);
}
-static unsigned long jh7100_clk_recalc_rate(struct clk_hw *hw,
+static unsigned long jh71x0_clk_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 div = jh7100_clk_reg_get(clk) & JH7100_CLK_DIV_MASK;
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ u32 div = jh71x0_clk_reg_get(clk) & JH71X0_CLK_DIV_MASK;
return div ? parent_rate / div : 0;
}
-static int jh7100_clk_determine_rate(struct clk_hw *hw,
+static int jh71x0_clk_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
unsigned long parent = req->best_parent_rate;
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
unsigned long div = min_t(unsigned long, DIV_ROUND_UP(parent, rate), clk->max_div);
@@ -102,232 +102,232 @@ static int jh7100_clk_determine_rate(struct clk_hw *hw,
return 0;
}
-static int jh7100_clk_set_rate(struct clk_hw *hw,
+static int jh71x0_clk_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
unsigned long div = clamp(DIV_ROUND_CLOSEST(parent_rate, rate),
1UL, (unsigned long)clk->max_div);
- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, div);
+ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, div);
return 0;
}
-static unsigned long jh7100_clk_frac_recalc_rate(struct clk_hw *hw,
+static unsigned long jh71x0_clk_frac_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 reg = jh7100_clk_reg_get(clk);
- unsigned long div100 = 100 * (reg & JH7100_CLK_INT_MASK) +
- ((reg & JH7100_CLK_FRAC_MASK) >> JH7100_CLK_FRAC_SHIFT);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ u32 reg = jh71x0_clk_reg_get(clk);
+ unsigned long div100 = 100 * (reg & JH71X0_CLK_INT_MASK) +
+ ((reg & JH71X0_CLK_FRAC_MASK) >> JH71X0_CLK_FRAC_SHIFT);
- return (div100 >= JH7100_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
+ return (div100 >= JH71X0_CLK_FRAC_MIN) ? 100 * parent_rate / div100 : 0;
}
-static int jh7100_clk_frac_determine_rate(struct clk_hw *hw,
+static int jh71x0_clk_frac_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
unsigned long parent100 = 100 * req->best_parent_rate;
unsigned long rate = clamp(req->rate, req->min_rate, req->max_rate);
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(parent100, rate),
- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
+ JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
unsigned long result = parent100 / div100;
- /* clamp the result as in jh7100_clk_determine_rate() above */
- if (result > req->max_rate && div100 < JH7100_CLK_FRAC_MAX)
+ /* clamp the result as in jh71x0_clk_determine_rate() above */
+ if (result > req->max_rate && div100 < JH71X0_CLK_FRAC_MAX)
result = parent100 / (div100 + 1);
- if (result < req->min_rate && div100 > JH7100_CLK_FRAC_MIN)
+ if (result < req->min_rate && div100 > JH71X0_CLK_FRAC_MIN)
result = parent100 / (div100 - 1);
req->rate = result;
return 0;
}
-static int jh7100_clk_frac_set_rate(struct clk_hw *hw,
+static int jh71x0_clk_frac_set_rate(struct clk_hw *hw,
unsigned long rate,
unsigned long parent_rate)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
unsigned long div100 = clamp(DIV_ROUND_CLOSEST(100 * parent_rate, rate),
- JH7100_CLK_FRAC_MIN, JH7100_CLK_FRAC_MAX);
- u32 value = ((div100 % 100) << JH7100_CLK_FRAC_SHIFT) | (div100 / 100);
+ JH71X0_CLK_FRAC_MIN, JH71X0_CLK_FRAC_MAX);
+ u32 value = ((div100 % 100) << JH71X0_CLK_FRAC_SHIFT) | (div100 / 100);
- jh7100_clk_reg_rmw(clk, JH7100_CLK_DIV_MASK, value);
+ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_DIV_MASK, value);
return 0;
}
-static u8 jh7100_clk_get_parent(struct clk_hw *hw)
+static u8 jh71x0_clk_get_parent(struct clk_hw *hw)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = jh7100_clk_reg_get(clk);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ u32 value = jh71x0_clk_reg_get(clk);
- return (value & JH7100_CLK_MUX_MASK) >> JH7100_CLK_MUX_SHIFT;
+ return (value & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT;
}
-static int jh7100_clk_set_parent(struct clk_hw *hw, u8 index)
+static int jh71x0_clk_set_parent(struct clk_hw *hw, u8 index)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = (u32)index << JH7100_CLK_MUX_SHIFT;
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ u32 value = (u32)index << JH71X0_CLK_MUX_SHIFT;
- jh7100_clk_reg_rmw(clk, JH7100_CLK_MUX_MASK, value);
+ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_MUX_MASK, value);
return 0;
}
-static int jh7100_clk_mux_determine_rate(struct clk_hw *hw,
+static int jh71x0_clk_mux_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
return clk_mux_determine_rate_flags(hw, req, 0);
}
-static int jh7100_clk_get_phase(struct clk_hw *hw)
+static int jh71x0_clk_get_phase(struct clk_hw *hw)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- u32 value = jh7100_clk_reg_get(clk);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ u32 value = jh71x0_clk_reg_get(clk);
- return (value & JH7100_CLK_INVERT) ? 180 : 0;
+ return (value & JH71X0_CLK_INVERT) ? 180 : 0;
}
-static int jh7100_clk_set_phase(struct clk_hw *hw, int degrees)
+static int jh71x0_clk_set_phase(struct clk_hw *hw, int degrees)
{
- struct jh7100_clk *clk = jh7100_clk_from(hw);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
u32 value;
if (degrees == 0)
value = 0;
else if (degrees == 180)
- value = JH7100_CLK_INVERT;
+ value = JH71X0_CLK_INVERT;
else
return -EINVAL;
- jh7100_clk_reg_rmw(clk, JH7100_CLK_INVERT, value);
+ jh71x0_clk_reg_rmw(clk, JH71X0_CLK_INVERT, value);
return 0;
}
#ifdef CONFIG_DEBUG_FS
-static void jh7100_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
+static void jh71x0_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
{
- static const struct debugfs_reg32 jh7100_clk_reg = {
+ static const struct debugfs_reg32 jh71x0_clk_reg = {
.name = "CTRL",
.offset = 0,
};
- struct jh7100_clk *clk = jh7100_clk_from(hw);
- struct jh7100_clk_priv *priv = jh7100_priv_from(clk);
+ struct jh71x0_clk *clk = jh71x0_clk_from(hw);
+ struct jh71x0_clk_priv *priv = jh71x0_priv_from(clk);
struct debugfs_regset32 *regset;
regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
if (!regset)
return;
- regset->regs = &jh7100_clk_reg;
+ regset->regs = &jh71x0_clk_reg;
regset->nregs = 1;
regset->base = priv->base + 4 * clk->idx;
debugfs_create_regset32("registers", 0400, dentry, regset);
}
#else
-#define jh7100_clk_debug_init NULL
+#define jh71x0_clk_debug_init NULL
#endif
-static const struct clk_ops jh7100_clk_gate_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_gate_ops = {
+ .enable = jh71x0_clk_enable,
+ .disable = jh71x0_clk_disable,
+ .is_enabled = jh71x0_clk_is_enabled,
+ .debug_init = jh71x0_clk_debug_init,
};
-static const struct clk_ops jh7100_clk_div_ops = {
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_div_ops = {
+ .recalc_rate = jh71x0_clk_recalc_rate,
+ .determine_rate = jh71x0_clk_determine_rate,
+ .set_rate = jh71x0_clk_set_rate,
+ .debug_init = jh71x0_clk_debug_init,
};
-static const struct clk_ops jh7100_clk_fdiv_ops = {
- .recalc_rate = jh7100_clk_frac_recalc_rate,
- .determine_rate = jh7100_clk_frac_determine_rate,
- .set_rate = jh7100_clk_frac_set_rate,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_fdiv_ops = {
+ .recalc_rate = jh71x0_clk_frac_recalc_rate,
+ .determine_rate = jh71x0_clk_frac_determine_rate,
+ .set_rate = jh71x0_clk_frac_set_rate,
+ .debug_init = jh71x0_clk_debug_init,
};
-static const struct clk_ops jh7100_clk_gdiv_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_gdiv_ops = {
+ .enable = jh71x0_clk_enable,
+ .disable = jh71x0_clk_disable,
+ .is_enabled = jh71x0_clk_is_enabled,
+ .recalc_rate = jh71x0_clk_recalc_rate,
+ .determine_rate = jh71x0_clk_determine_rate,
+ .set_rate = jh71x0_clk_set_rate,
+ .debug_init = jh71x0_clk_debug_init,
};
-static const struct clk_ops jh7100_clk_mux_ops = {
- .determine_rate = jh7100_clk_mux_determine_rate,
- .set_parent = jh7100_clk_set_parent,
- .get_parent = jh7100_clk_get_parent,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_mux_ops = {
+ .determine_rate = jh71x0_clk_mux_determine_rate,
+ .set_parent = jh71x0_clk_set_parent,
+ .get_parent = jh71x0_clk_get_parent,
+ .debug_init = jh71x0_clk_debug_init,
};
-static const struct clk_ops jh7100_clk_gmux_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .determine_rate = jh7100_clk_mux_determine_rate,
- .set_parent = jh7100_clk_set_parent,
- .get_parent = jh7100_clk_get_parent,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_gmux_ops = {
+ .enable = jh71x0_clk_enable,
+ .disable = jh71x0_clk_disable,
+ .is_enabled = jh71x0_clk_is_enabled,
+ .determine_rate = jh71x0_clk_mux_determine_rate,
+ .set_parent = jh71x0_clk_set_parent,
+ .get_parent = jh71x0_clk_get_parent,
+ .debug_init = jh71x0_clk_debug_init,
};
-static const struct clk_ops jh7100_clk_mdiv_ops = {
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .get_parent = jh7100_clk_get_parent,
- .set_parent = jh7100_clk_set_parent,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_mdiv_ops = {
+ .recalc_rate = jh71x0_clk_recalc_rate,
+ .determine_rate = jh71x0_clk_determine_rate,
+ .get_parent = jh71x0_clk_get_parent,
+ .set_parent = jh71x0_clk_set_parent,
+ .set_rate = jh71x0_clk_set_rate,
+ .debug_init = jh71x0_clk_debug_init,
};
-static const struct clk_ops jh7100_clk_gmd_ops = {
- .enable = jh7100_clk_enable,
- .disable = jh7100_clk_disable,
- .is_enabled = jh7100_clk_is_enabled,
- .recalc_rate = jh7100_clk_recalc_rate,
- .determine_rate = jh7100_clk_determine_rate,
- .get_parent = jh7100_clk_get_parent,
- .set_parent = jh7100_clk_set_parent,
- .set_rate = jh7100_clk_set_rate,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_gmd_ops = {
+ .enable = jh71x0_clk_enable,
+ .disable = jh71x0_clk_disable,
+ .is_enabled = jh71x0_clk_is_enabled,
+ .recalc_rate = jh71x0_clk_recalc_rate,
+ .determine_rate = jh71x0_clk_determine_rate,
+ .get_parent = jh71x0_clk_get_parent,
+ .set_parent = jh71x0_clk_set_parent,
+ .set_rate = jh71x0_clk_set_rate,
+ .debug_init = jh71x0_clk_debug_init,
};
-static const struct clk_ops jh7100_clk_inv_ops = {
- .get_phase = jh7100_clk_get_phase,
- .set_phase = jh7100_clk_set_phase,
- .debug_init = jh7100_clk_debug_init,
+static const struct clk_ops jh71x0_clk_inv_ops = {
+ .get_phase = jh71x0_clk_get_phase,
+ .set_phase = jh71x0_clk_set_phase,
+ .debug_init = jh71x0_clk_debug_init,
};
-const struct clk_ops *starfive_jh7100_clk_ops(u32 max)
+const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
{
- if (max & JH7100_CLK_DIV_MASK) {
- if (max & JH7100_CLK_MUX_MASK) {
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gmd_ops;
- return &jh7100_clk_mdiv_ops;
+ if (max & JH71X0_CLK_DIV_MASK) {
+ if (max & JH71X0_CLK_MUX_MASK) {
+ if (max & JH71X0_CLK_ENABLE)
+ return &jh71x0_clk_gmd_ops;
+ return &jh71x0_clk_mdiv_ops;
}
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gdiv_ops;
- if (max == JH7100_CLK_FRAC_MAX)
- return &jh7100_clk_fdiv_ops;
- return &jh7100_clk_div_ops;
+ if (max & JH71X0_CLK_ENABLE)
+ return &jh71x0_clk_gdiv_ops;
+ if (max == JH71X0_CLK_FRAC_MAX)
+ return &jh71x0_clk_fdiv_ops;
+ return &jh71x0_clk_div_ops;
}
- if (max & JH7100_CLK_MUX_MASK) {
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gmux_ops;
- return &jh7100_clk_mux_ops;
+ if (max & JH71X0_CLK_MUX_MASK) {
+ if (max & JH71X0_CLK_ENABLE)
+ return &jh71x0_clk_gmux_ops;
+ return &jh71x0_clk_mux_ops;
}
- if (max & JH7100_CLK_ENABLE)
- return &jh7100_clk_gate_ops;
+ if (max & JH71X0_CLK_ENABLE)
+ return &jh71x0_clk_gate_ops;
- return &jh7100_clk_inv_ops;
+ return &jh71x0_clk_inv_ops;
}
-EXPORT_SYMBOL_GPL(starfive_jh7100_clk_ops);
+EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
index a8ba6e25b5ce..baf4b5cb4b8a 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CLK_STARFIVE_JH7100_H
-#define __CLK_STARFIVE_JH7100_H
+#ifndef __CLK_STARFIVE_JH71X0_H
+#define __CLK_STARFIVE_JH71X0_H
#include <linux/bits.h>
#include <linux/clk-provider.h>
@@ -8,107 +8,107 @@
#include <linux/spinlock.h>
/* register fields */
-#define JH7100_CLK_ENABLE BIT(31)
-#define JH7100_CLK_INVERT BIT(30)
-#define JH7100_CLK_MUX_MASK GENMASK(27, 24)
-#define JH7100_CLK_MUX_SHIFT 24
-#define JH7100_CLK_DIV_MASK GENMASK(23, 0)
-#define JH7100_CLK_FRAC_MASK GENMASK(15, 8)
-#define JH7100_CLK_FRAC_SHIFT 8
-#define JH7100_CLK_INT_MASK GENMASK(7, 0)
+#define JH71X0_CLK_ENABLE BIT(31)
+#define JH71X0_CLK_INVERT BIT(30)
+#define JH71X0_CLK_MUX_MASK GENMASK(27, 24)
+#define JH71X0_CLK_MUX_SHIFT 24
+#define JH71X0_CLK_DIV_MASK GENMASK(23, 0)
+#define JH71X0_CLK_FRAC_MASK GENMASK(15, 8)
+#define JH71X0_CLK_FRAC_SHIFT 8
+#define JH71X0_CLK_INT_MASK GENMASK(7, 0)
/* fractional divider min/max */
-#define JH7100_CLK_FRAC_MIN 100UL
-#define JH7100_CLK_FRAC_MAX 25599UL
+#define JH71X0_CLK_FRAC_MIN 100UL
+#define JH71X0_CLK_FRAC_MAX 25599UL
/* clock data */
-struct jh7100_clk_data {
+struct jh71x0_clk_data {
const char *name;
unsigned long flags;
u32 max;
u8 parents[4];
};
-#define JH7100_GATE(_idx, _name, _flags, _parent) [_idx] = { \
+#define JH71X0_GATE(_idx, _name, _flags, _parent) [_idx] = { \
.name = _name, \
.flags = CLK_SET_RATE_PARENT | (_flags), \
- .max = JH7100_CLK_ENABLE, \
+ .max = JH71X0_CLK_ENABLE, \
.parents = { [0] = _parent }, \
}
-#define JH7100__DIV(_idx, _name, _max, _parent) [_idx] = { \
+#define JH71X0__DIV(_idx, _name, _max, _parent) [_idx] = { \
.name = _name, \
.flags = 0, \
.max = _max, \
.parents = { [0] = _parent }, \
}
-#define JH7100_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
+#define JH71X0_GDIV(_idx, _name, _flags, _max, _parent) [_idx] = { \
.name = _name, \
.flags = _flags, \
- .max = JH7100_CLK_ENABLE | (_max), \
+ .max = JH71X0_CLK_ENABLE | (_max), \
.parents = { [0] = _parent }, \
}
-#define JH7100_FDIV(_idx, _name, _parent) [_idx] = { \
+#define JH71X0_FDIV(_idx, _name, _parent) [_idx] = { \
.name = _name, \
.flags = 0, \
- .max = JH7100_CLK_FRAC_MAX, \
+ .max = JH71X0_CLK_FRAC_MAX, \
.parents = { [0] = _parent }, \
}
-#define JH7100__MUX(_idx, _name, _nparents, ...) [_idx] = { \
+#define JH71X0__MUX(_idx, _name, _nparents, ...) [_idx] = { \
.name = _name, \
.flags = 0, \
- .max = ((_nparents) - 1) << JH7100_CLK_MUX_SHIFT, \
+ .max = ((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT, \
.parents = { __VA_ARGS__ }, \
}
-#define JH7100_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
+#define JH71X0_GMUX(_idx, _name, _flags, _nparents, ...) [_idx] = { \
.name = _name, \
.flags = _flags, \
- .max = JH7100_CLK_ENABLE | \
- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT), \
+ .max = JH71X0_CLK_ENABLE | \
+ (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT), \
.parents = { __VA_ARGS__ }, \
}
-#define JH7100_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
+#define JH71X0_MDIV(_idx, _name, _max, _nparents, ...) [_idx] = { \
.name = _name, \
.flags = 0, \
- .max = (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
+ .max = (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
.parents = { __VA_ARGS__ }, \
}
-#define JH7100__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
+#define JH71X0__GMD(_idx, _name, _flags, _max, _nparents, ...) [_idx] = { \
.name = _name, \
.flags = _flags, \
- .max = JH7100_CLK_ENABLE | \
- (((_nparents) - 1) << JH7100_CLK_MUX_SHIFT) | (_max), \
+ .max = JH71X0_CLK_ENABLE | \
+ (((_nparents) - 1) << JH71X0_CLK_MUX_SHIFT) | (_max), \
.parents = { __VA_ARGS__ }, \
}
-#define JH7100__INV(_idx, _name, _parent) [_idx] = { \
+#define JH71X0__INV(_idx, _name, _parent) [_idx] = { \
.name = _name, \
.flags = CLK_SET_RATE_PARENT, \
- .max = JH7100_CLK_INVERT, \
+ .max = JH71X0_CLK_INVERT, \
.parents = { [0] = _parent }, \
}
-struct jh7100_clk {
+struct jh71x0_clk {
struct clk_hw hw;
unsigned int idx;
unsigned int max_div;
};
-struct jh7100_clk_priv {
+struct jh71x0_clk_priv {
/* protect clk enable and set rate/parent from happening at the same time */
spinlock_t rmw_lock;
struct device *dev;
void __iomem *base;
struct clk_hw *pll[3];
- struct jh7100_clk reg[];
+ struct jh71x0_clk reg[];
};
-const struct clk_ops *starfive_jh7100_clk_ops(u32 max);
+const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
#endif
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (2 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng
` (17 subsequent siblings)
21 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
MAINTAINERS | 2 +-
drivers/reset/Kconfig | 8 +-------
drivers/reset/Makefile | 2 +-
drivers/reset/starfive/Kconfig | 8 ++++++++
drivers/reset/starfive/Makefile | 2 ++
drivers/reset/{ => starfive}/reset-starfive-jh7100.c | 0
6 files changed, 13 insertions(+), 9 deletions(-)
create mode 100644 drivers/reset/starfive/Kconfig
create mode 100644 drivers/reset/starfive/Makefile
rename drivers/reset/{ => starfive}/reset-starfive-jh7100.c (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0b3246ca0f48..7026d96b7802 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19930,7 +19930,7 @@ STARFIVE JH7100 RESET CONTROLLER DRIVER
M: Emil Renner Berthing <kernel@esmil.dk>
S: Maintained
F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-F: drivers/reset/reset-starfive-jh7100.c
+F: drivers/reset/starfive/reset-starfive-jh7100.c
F: include/dt-bindings/reset/starfive-jh7100.h
STATIC BRANCH/CALL
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 2a52c990d4fe..6aa8f243b30c 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -232,13 +232,6 @@ config RESET_SOCFPGA
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
-config RESET_STARFIVE_JH7100
- bool "StarFive JH7100 Reset Driver"
- depends on SOC_STARFIVE || COMPILE_TEST
- default SOC_STARFIVE
- help
- This enables the reset controller driver for the StarFive JH7100 SoC.
-
config RESET_SUNPLUS
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
default ARCH_SUNPLUS
@@ -320,6 +313,7 @@ config RESET_ZYNQ
help
This enables the reset controller driver for Xilinx Zynq SoCs.
+source "drivers/reset/starfive/Kconfig"
source "drivers/reset/sti/Kconfig"
source "drivers/reset/hisilicon/Kconfig"
source "drivers/reset/tegra/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3e7e5fd633a8..fee17a0e3a16 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += core.o
obj-y += hisilicon/
+obj-$(CONFIG_SOC_STARFIVE) += starfive/
obj-$(CONFIG_ARCH_STI) += sti/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
@@ -30,7 +31,6 @@ obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) += reset-rzg2l-usbphy-ctrl.o
obj-$(CONFIG_RESET_SCMI) += reset-scmi.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
-obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_SUNPLUS) += reset-sunplus.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
new file mode 100644
index 000000000000..cddebdba7177
--- /dev/null
+++ b/drivers/reset/starfive/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config RESET_STARFIVE_JH7100
+ bool "StarFive JH7100 Reset Driver"
+ depends on SOC_STARFIVE || COMPILE_TEST
+ default SOC_STARFIVE
+ help
+ This enables the reset controller driver for the StarFive JH7100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
new file mode 100644
index 000000000000..670d049423f5
--- /dev/null
+++ b/drivers/reset/starfive/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
diff --git a/drivers/reset/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
similarity index 100%
rename from drivers/reset/reset-starfive-jh7100.c
rename to drivers/reset/starfive/reset-starfive-jh7100.c
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (3 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 17:10 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng
` (16 subsequent siblings)
21 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
The StarFive JH7100 SoC has additional reset controllers for audio and
video, but the registers follow the same structure. On the JH7110 the
reset registers don't get their own memory range, but instead follow the
clock control registers. The registers still follow the same structure
though, so let's factor out the common code to handle all these cases.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
MAINTAINERS | 4 +-
drivers/reset/starfive/Kconfig | 4 +
drivers/reset/starfive/Makefile | 2 +
.../reset/starfive/reset-starfive-jh7100.c | 150 +---------------
.../reset/starfive/reset-starfive-jh71x0.c | 162 ++++++++++++++++++
.../reset/starfive/reset-starfive-jh71x0.h | 11 ++
6 files changed, 182 insertions(+), 151 deletions(-)
create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c
create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 7026d96b7802..3fca3316b857 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19926,11 +19926,11 @@ F: Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
F: drivers/pinctrl/starfive/
F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
-STARFIVE JH7100 RESET CONTROLLER DRIVER
+STARFIVE JH71X0 RESET CONTROLLER DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
S: Maintained
F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
-F: drivers/reset/starfive/reset-starfive-jh7100.c
+F: drivers/reset/starfive/reset-starfive-jh71*
F: include/dt-bindings/reset/starfive-jh7100.h
STATIC BRANCH/CALL
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index cddebdba7177..9d15c4110e40 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -1,8 +1,12 @@
# SPDX-License-Identifier: GPL-2.0-only
+config RESET_STARFIVE_JH71X0
+ bool
+
config RESET_STARFIVE_JH7100
bool "StarFive JH7100 Reset Driver"
depends on SOC_STARFIVE || COMPILE_TEST
+ select RESET_STARFIVE_JH71X0
default SOC_STARFIVE
help
This enables the reset controller driver for the StarFive JH7100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 670d049423f5..f6aa12466fad 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -1,2 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
+
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index fc44b2fb3e03..5a68327c1f6a 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -5,158 +5,10 @@
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
-#include <linux/bitmap.h>
-#include <linux/io.h>
-#include <linux/io-64-nonatomic-lo-hi.h>
-#include <linux/iopoll.h>
#include <linux/mod_devicetable.h>
#include <linux/platform_device.h>
-#include <linux/reset-controller.h>
-#include <linux/spinlock.h>
-#include <dt-bindings/reset/starfive-jh7100.h>
-
-/* register offsets */
-#define JH7100_RESET_ASSERT0 0x00
-#define JH7100_RESET_ASSERT1 0x04
-#define JH7100_RESET_ASSERT2 0x08
-#define JH7100_RESET_ASSERT3 0x0c
-#define JH7100_RESET_STATUS0 0x10
-#define JH7100_RESET_STATUS1 0x14
-#define JH7100_RESET_STATUS2 0x18
-#define JH7100_RESET_STATUS3 0x1c
-
-/*
- * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
- * line 32m + n, and writing a 0 deasserts the same line.
- * Most reset lines have their status inverted so a 0 bit in the STATUS
- * register means the line is asserted and a 1 means it's deasserted. A few
- * lines don't though, so store the expected value of the status registers when
- * all lines are asserted.
- */
-static const u64 jh7100_reset_asserted[2] = {
- /* STATUS0 */
- BIT_ULL_MASK(JH7100_RST_U74) |
- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
- /* STATUS1 */
- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
- /* STATUS2 */
- BIT_ULL_MASK(JH7100_RST_E24) |
- /* STATUS3 */
- 0,
-};
-
-struct jh7100_reset {
- struct reset_controller_dev rcdev;
- /* protect registers against concurrent read-modify-write */
- spinlock_t lock;
- void __iomem *base;
-};
-
-static inline struct jh7100_reset *
-jh7100_reset_from(struct reset_controller_dev *rcdev)
-{
- return container_of(rcdev, struct jh7100_reset, rcdev);
-}
-
-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
- unsigned long id, bool assert)
-{
- struct jh7100_reset *data = jh7100_reset_from(rcdev);
- unsigned long offset = BIT_ULL_WORD(id);
- u64 mask = BIT_ULL_MASK(id);
- void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
- u64 done = jh7100_reset_asserted[offset] & mask;
- u64 value;
- unsigned long flags;
- int ret;
-
- if (!assert)
- done ^= mask;
-
- spin_lock_irqsave(&data->lock, flags);
-
- value = readq(reg_assert);
- if (assert)
- value |= mask;
- else
- value &= ~mask;
- writeq(value, reg_assert);
-
- /* if the associated clock is gated, deasserting might otherwise hang forever */
- ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
-
- spin_unlock_irqrestore(&data->lock, flags);
- return ret;
-}
-
-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- return jh7100_reset_update(rcdev, id, true);
-}
-
-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- return jh7100_reset_update(rcdev, id, false);
-}
-
-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- int ret;
-
- ret = jh7100_reset_assert(rcdev, id);
- if (ret)
- return ret;
-
- return jh7100_reset_deassert(rcdev, id);
-}
-
-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
- unsigned long id)
-{
- struct jh7100_reset *data = jh7100_reset_from(rcdev);
- unsigned long offset = BIT_ULL_WORD(id);
- u64 mask = BIT_ULL_MASK(id);
- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
- u64 value = readq(reg_status);
-
- return !((value ^ jh7100_reset_asserted[offset]) & mask);
-}
-
-static const struct reset_control_ops jh7100_reset_ops = {
- .assert = jh7100_reset_assert,
- .deassert = jh7100_reset_deassert,
- .reset = jh7100_reset_reset,
- .status = jh7100_reset_status,
-};
-
-static int __init jh7100_reset_probe(struct platform_device *pdev)
-{
- struct jh7100_reset *data;
-
- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
- if (!data)
- return -ENOMEM;
-
- data->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(data->base))
- return PTR_ERR(data->base);
-
- data->rcdev.ops = &jh7100_reset_ops;
- data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = JH7100_RSTN_END;
- data->rcdev.dev = &pdev->dev;
- data->rcdev.of_node = pdev->dev.of_node;
- spin_lock_init(&data->lock);
-
- return devm_reset_controller_register(&pdev->dev, &data->rcdev);
-}
+#include "reset-starfive-jh71x0.h"
static const struct of_device_id jh7100_reset_dt_ids[] = {
{ .compatible = "starfive,jh7100-reset" },
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
new file mode 100644
index 000000000000..114a13c4b8a6
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Reset driver for the StarFive JH7100 SoC
+ *
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#include <linux/bitmap.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/iopoll.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/spinlock.h>
+
+#include "reset-starfive-jh71x0.h"
+
+#include <dt-bindings/reset/starfive-jh7100.h>
+
+/* register offsets */
+#define JH7100_RESET_ASSERT0 0x00
+#define JH7100_RESET_ASSERT1 0x04
+#define JH7100_RESET_ASSERT2 0x08
+#define JH7100_RESET_ASSERT3 0x0c
+#define JH7100_RESET_STATUS0 0x10
+#define JH7100_RESET_STATUS1 0x14
+#define JH7100_RESET_STATUS2 0x18
+#define JH7100_RESET_STATUS3 0x1c
+
+/*
+ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
+ * line 32m + n, and writing a 0 deasserts the same line.
+ * Most reset lines have their status inverted so a 0 bit in the STATUS
+ * register means the line is asserted and a 1 means it's deasserted. A few
+ * lines don't though, so store the expected value of the status registers when
+ * all lines are asserted.
+ */
+static const u64 jh7100_reset_asserted[2] = {
+ /* STATUS0 */
+ BIT_ULL_MASK(JH7100_RST_U74) |
+ BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
+ BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
+ /* STATUS1 */
+ BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
+ BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
+ /* STATUS2 */
+ BIT_ULL_MASK(JH7100_RST_E24) |
+ /* STATUS3 */
+ 0,
+};
+
+struct jh7100_reset {
+ struct reset_controller_dev rcdev;
+ /* protect registers against concurrent read-modify-write */
+ spinlock_t lock;
+ void __iomem *base;
+};
+
+static inline struct jh7100_reset *
+jh7100_reset_from(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct jh7100_reset, rcdev);
+}
+
+static int jh7100_reset_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct jh7100_reset *data = jh7100_reset_from(rcdev);
+ unsigned long offset = BIT_ULL_WORD(id);
+ u64 mask = BIT_ULL_MASK(id);
+ void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
+ void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
+ u64 done = jh7100_reset_asserted[offset] & mask;
+ u64 value;
+ unsigned long flags;
+ int ret;
+
+ if (!assert)
+ done ^= mask;
+
+ spin_lock_irqsave(&data->lock, flags);
+
+ value = readq(reg_assert);
+ if (assert)
+ value |= mask;
+ else
+ value &= ~mask;
+ writeq(value, reg_assert);
+
+ /* if the associated clock is gated, deasserting might otherwise hang forever */
+ ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
+
+ spin_unlock_irqrestore(&data->lock, flags);
+ return ret;
+}
+
+static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return jh7100_reset_update(rcdev, id, true);
+}
+
+static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return jh7100_reset_update(rcdev, id, false);
+}
+
+static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ int ret;
+
+ ret = jh7100_reset_assert(rcdev, id);
+ if (ret)
+ return ret;
+
+ return jh7100_reset_deassert(rcdev, id);
+}
+
+static int jh7100_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct jh7100_reset *data = jh7100_reset_from(rcdev);
+ unsigned long offset = BIT_ULL_WORD(id);
+ u64 mask = BIT_ULL_MASK(id);
+ void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
+ u64 value = readq(reg_status);
+
+ return !((value ^ jh7100_reset_asserted[offset]) & mask);
+}
+
+static const struct reset_control_ops jh7100_reset_ops = {
+ .assert = jh7100_reset_assert,
+ .deassert = jh7100_reset_deassert,
+ .reset = jh7100_reset_reset,
+ .status = jh7100_reset_status,
+};
+
+int jh7100_reset_probe(struct platform_device *pdev)
+{
+ struct jh7100_reset *data;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(data->base))
+ return PTR_ERR(data->base);
+
+ data->rcdev.ops = &jh7100_reset_ops;
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.nr_resets = JH7100_RSTN_END;
+ data->rcdev.dev = &pdev->dev;
+ data->rcdev.of_node = pdev->dev.of_node;
+ spin_lock_init(&data->lock);
+
+ return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+}
+EXPORT_SYMBOL_GPL(jh7100_reset_probe);
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
new file mode 100644
index 000000000000..318d7a0e096a
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef __RESET_STARFIVE_JH71X0_H
+#define __RESET_STARFIVE_JH71X0_H
+
+int jh7100_reset_probe(struct platform_device *pdev);
+
+#endif /* __RESET_STARFIVE_JH71X0_H */
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 06/19] reset: starfive: Extract the common JH71X0 reset code
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (4 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 17:13 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
` (15 subsequent siblings)
21 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Extract the common JH71X0 reset code for reusing them to
support JH7110 SoC.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../reset/starfive/reset-starfive-jh7100.c | 49 ++++++++++++
.../reset/starfive/reset-starfive-jh71x0.c | 76 ++++++-------------
.../reset/starfive/reset-starfive-jh71x0.h | 5 +-
3 files changed, 76 insertions(+), 54 deletions(-)
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 5a68327c1f6a..9d7cb4ed8869 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -10,6 +10,55 @@
#include "reset-starfive-jh71x0.h"
+#include <dt-bindings/reset/starfive-jh7100.h>
+
+/* register offsets */
+#define JH7100_RESET_ASSERT0 0x00
+#define JH7100_RESET_ASSERT1 0x04
+#define JH7100_RESET_ASSERT2 0x08
+#define JH7100_RESET_ASSERT3 0x0c
+#define JH7100_RESET_STATUS0 0x10
+#define JH7100_RESET_STATUS1 0x14
+#define JH7100_RESET_STATUS2 0x18
+#define JH7100_RESET_STATUS3 0x1c
+
+/*
+ * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
+ * line 32m + n, and writing a 0 deasserts the same line.
+ * Most reset lines have their status inverted so a 0 bit in the STATUS
+ * register means the line is asserted and a 1 means it's deasserted. A few
+ * lines don't though, so store the expected value of the status registers when
+ * all lines are asserted.
+ */
+static const u64 jh7100_reset_asserted[2] = {
+ /* STATUS0 */
+ BIT_ULL_MASK(JH7100_RST_U74) |
+ BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
+ BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
+ /* STATUS1 */
+ BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
+ BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
+ /* STATUS2 */
+ BIT_ULL_MASK(JH7100_RST_E24) |
+ /* STATUS3 */
+ 0,
+};
+
+static int __init jh7100_reset_probe(struct platform_device *pdev)
+{
+ void __iomem *base = devm_platform_ioremap_resource(pdev, 0);
+
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
+ base + JH7100_RESET_ASSERT0,
+ base + JH7100_RESET_STATUS0,
+ jh7100_reset_asserted,
+ JH7100_RSTN_END,
+ THIS_MODULE);
+}
+
static const struct of_device_id jh7100_reset_dt_ids[] = {
{ .compatible = "starfive,jh7100-reset" },
{ /* sentinel */ }
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
index 114a13c4b8a6..3577444a89c6 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
@@ -10,51 +10,18 @@
#include <linux/io.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/iopoll.h>
-#include <linux/platform_device.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include "reset-starfive-jh71x0.h"
-#include <dt-bindings/reset/starfive-jh7100.h>
-
-/* register offsets */
-#define JH7100_RESET_ASSERT0 0x00
-#define JH7100_RESET_ASSERT1 0x04
-#define JH7100_RESET_ASSERT2 0x08
-#define JH7100_RESET_ASSERT3 0x0c
-#define JH7100_RESET_STATUS0 0x10
-#define JH7100_RESET_STATUS1 0x14
-#define JH7100_RESET_STATUS2 0x18
-#define JH7100_RESET_STATUS3 0x1c
-
-/*
- * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
- * line 32m + n, and writing a 0 deasserts the same line.
- * Most reset lines have their status inverted so a 0 bit in the STATUS
- * register means the line is asserted and a 1 means it's deasserted. A few
- * lines don't though, so store the expected value of the status registers when
- * all lines are asserted.
- */
-static const u64 jh7100_reset_asserted[2] = {
- /* STATUS0 */
- BIT_ULL_MASK(JH7100_RST_U74) |
- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
- /* STATUS1 */
- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
- /* STATUS2 */
- BIT_ULL_MASK(JH7100_RST_E24) |
- /* STATUS3 */
- 0,
-};
-
struct jh7100_reset {
struct reset_controller_dev rcdev;
/* protect registers against concurrent read-modify-write */
spinlock_t lock;
- void __iomem *base;
+ void __iomem *assert;
+ void __iomem *status;
+ const u64 *asserted;
};
static inline struct jh7100_reset *
@@ -69,9 +36,9 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
struct jh7100_reset *data = jh7100_reset_from(rcdev);
unsigned long offset = BIT_ULL_WORD(id);
u64 mask = BIT_ULL_MASK(id);
- void __iomem *reg_assert = data->base + JH7100_RESET_ASSERT0 + offset * sizeof(u64);
- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
- u64 done = jh7100_reset_asserted[offset] & mask;
+ void __iomem *reg_assert = data->assert + offset * sizeof(u64);
+ void __iomem *reg_status = data->status + offset * sizeof(u64);
+ u64 done = data->asserted ? data->asserted[offset] & mask : 0;
u64 value;
unsigned long flags;
int ret;
@@ -125,10 +92,10 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
struct jh7100_reset *data = jh7100_reset_from(rcdev);
unsigned long offset = BIT_ULL_WORD(id);
u64 mask = BIT_ULL_MASK(id);
- void __iomem *reg_status = data->base + JH7100_RESET_STATUS0 + offset * sizeof(u64);
+ void __iomem *reg_status = data->status + offset * sizeof(u64);
u64 value = readq(reg_status);
- return !((value ^ jh7100_reset_asserted[offset]) & mask);
+ return !((value ^ data->asserted[offset]) & mask);
}
static const struct reset_control_ops jh7100_reset_ops = {
@@ -138,25 +105,28 @@ static const struct reset_control_ops jh7100_reset_ops = {
.status = jh7100_reset_status,
};
-int jh7100_reset_probe(struct platform_device *pdev)
+int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
+ void __iomem *assert, void __iomem *status,
+ const u64 *asserted, unsigned int nr_resets,
+ struct module *owner)
{
struct jh7100_reset *data;
- data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
- data->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(data->base))
- return PTR_ERR(data->base);
-
data->rcdev.ops = &jh7100_reset_ops;
- data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = JH7100_RSTN_END;
- data->rcdev.dev = &pdev->dev;
- data->rcdev.of_node = pdev->dev.of_node;
+ data->rcdev.owner = owner;
+ data->rcdev.nr_resets = nr_resets;
+ data->rcdev.dev = dev;
+ data->rcdev.of_node = of_node;
+
spin_lock_init(&data->lock);
+ data->assert = assert;
+ data->status = status;
+ data->asserted = asserted;
- return devm_reset_controller_register(&pdev->dev, &data->rcdev);
+ return devm_reset_controller_register(dev, &data->rcdev);
}
-EXPORT_SYMBOL_GPL(jh7100_reset_probe);
+EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
index 318d7a0e096a..1fc5a648c8d8 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
@@ -6,6 +6,9 @@
#ifndef __RESET_STARFIVE_JH71X0_H
#define __RESET_STARFIVE_JH71X0_H
-int jh7100_reset_probe(struct platform_device *pdev);
+int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
+ void __iomem *assert, void __iomem *status,
+ const u64 *asserted, unsigned int nr_resets,
+ struct module *owner);
#endif /* __RESET_STARFIVE_JH71X0_H */
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (5 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 17:17 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
` (14 subsequent siblings)
21 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
For the common code will be shared with the StarFive JH7110 SoC.
Reported-by: kernel test robot <lkp@intel.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../reset/starfive/reset-starfive-jh7100.c | 2 +-
.../reset/starfive/reset-starfive-jh71x0.c | 50 +++++++++----------
.../reset/starfive/reset-starfive-jh71x0.h | 2 +-
3 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 9d7cb4ed8869..5f06e5ae3346 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -51,7 +51,7 @@ static int __init jh7100_reset_probe(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- return reset_starfive_jh7100_register(&pdev->dev, pdev->dev.of_node,
+ return reset_starfive_jh71x0_register(&pdev->dev, pdev->dev.of_node,
base + JH7100_RESET_ASSERT0,
base + JH7100_RESET_STATUS0,
jh7100_reset_asserted,
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
index 3577444a89c6..a689f4730ed7 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/*
- * Reset driver for the StarFive JH7100 SoC
+ * Reset driver for the StarFive JH71X0 SoCs
*
* Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
*/
@@ -15,7 +15,7 @@
#include "reset-starfive-jh71x0.h"
-struct jh7100_reset {
+struct jh71x0_reset {
struct reset_controller_dev rcdev;
/* protect registers against concurrent read-modify-write */
spinlock_t lock;
@@ -24,16 +24,16 @@ struct jh7100_reset {
const u64 *asserted;
};
-static inline struct jh7100_reset *
-jh7100_reset_from(struct reset_controller_dev *rcdev)
+static inline struct jh71x0_reset *
+jh71x0_reset_from(struct reset_controller_dev *rcdev)
{
- return container_of(rcdev, struct jh7100_reset, rcdev);
+ return container_of(rcdev, struct jh71x0_reset, rcdev);
}
-static int jh7100_reset_update(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
- struct jh7100_reset *data = jh7100_reset_from(rcdev);
+ struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
unsigned long offset = BIT_ULL_WORD(id);
u64 mask = BIT_ULL_MASK(id);
void __iomem *reg_assert = data->assert + offset * sizeof(u64);
@@ -62,34 +62,34 @@ static int jh7100_reset_update(struct reset_controller_dev *rcdev,
return ret;
}
-static int jh7100_reset_assert(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_assert(struct reset_controller_dev *rcdev,
unsigned long id)
{
- return jh7100_reset_update(rcdev, id, true);
+ return jh71x0_reset_update(rcdev, id, true);
}
-static int jh7100_reset_deassert(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_deassert(struct reset_controller_dev *rcdev,
unsigned long id)
{
- return jh7100_reset_update(rcdev, id, false);
+ return jh71x0_reset_update(rcdev, id, false);
}
-static int jh7100_reset_reset(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_reset(struct reset_controller_dev *rcdev,
unsigned long id)
{
int ret;
- ret = jh7100_reset_assert(rcdev, id);
+ ret = jh71x0_reset_assert(rcdev, id);
if (ret)
return ret;
- return jh7100_reset_deassert(rcdev, id);
+ return jh71x0_reset_deassert(rcdev, id);
}
-static int jh7100_reset_status(struct reset_controller_dev *rcdev,
+static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
- struct jh7100_reset *data = jh7100_reset_from(rcdev);
+ struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
unsigned long offset = BIT_ULL_WORD(id);
u64 mask = BIT_ULL_MASK(id);
void __iomem *reg_status = data->status + offset * sizeof(u64);
@@ -98,25 +98,25 @@ static int jh7100_reset_status(struct reset_controller_dev *rcdev,
return !((value ^ data->asserted[offset]) & mask);
}
-static const struct reset_control_ops jh7100_reset_ops = {
- .assert = jh7100_reset_assert,
- .deassert = jh7100_reset_deassert,
- .reset = jh7100_reset_reset,
- .status = jh7100_reset_status,
+static const struct reset_control_ops jh71x0_reset_ops = {
+ .assert = jh71x0_reset_assert,
+ .deassert = jh71x0_reset_deassert,
+ .reset = jh71x0_reset_reset,
+ .status = jh71x0_reset_status,
};
-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
const u64 *asserted, unsigned int nr_resets,
struct module *owner)
{
- struct jh7100_reset *data;
+ struct jh71x0_reset *data;
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
- data->rcdev.ops = &jh7100_reset_ops;
+ data->rcdev.ops = &jh71x0_reset_ops;
data->rcdev.owner = owner;
data->rcdev.nr_resets = nr_resets;
data->rcdev.dev = dev;
@@ -129,4 +129,4 @@ int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_no
return devm_reset_controller_register(dev, &data->rcdev);
}
-EXPORT_SYMBOL_GPL(reset_starfive_jh7100_register);
+EXPORT_SYMBOL_GPL(reset_starfive_jh71x0_register);
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
index 1fc5a648c8d8..ac9e80dd3f59 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
@@ -6,7 +6,7 @@
#ifndef __RESET_STARFIVE_JH71X0_H
#define __RESET_STARFIVE_JH71X0_H
-int reset_starfive_jh7100_register(struct device *dev, struct device_node *of_node,
+int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
const u64 *asserted, unsigned int nr_resets,
struct module *owner);
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (6 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
` (13 subsequent siblings)
21 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
We currently use 64bit I/O on the 32bit registers. This works because
there are an even number of assert and status registers, so they're only
ever accessed in pairs on 64bit boundaries.
There are however other reset controllers for audio and video on the
JH7100 SoC with only one status register that isn't 64bit aligned so
64bit I/O results in an unaligned access exception.
Switch to 32bit I/O in preparation for supporting these resets too.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../reset/starfive/reset-starfive-jh7100.c | 14 ++++-----
.../reset/starfive/reset-starfive-jh71x0.c | 31 +++++++++----------
.../reset/starfive/reset-starfive-jh71x0.h | 2 +-
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/reset/starfive/reset-starfive-jh7100.c b/drivers/reset/starfive/reset-starfive-jh7100.c
index 5f06e5ae3346..2a56f7fd4ba7 100644
--- a/drivers/reset/starfive/reset-starfive-jh7100.c
+++ b/drivers/reset/starfive/reset-starfive-jh7100.c
@@ -30,16 +30,16 @@
* lines don't though, so store the expected value of the status registers when
* all lines are asserted.
*/
-static const u64 jh7100_reset_asserted[2] = {
+static const u32 jh7100_reset_asserted[4] = {
/* STATUS0 */
- BIT_ULL_MASK(JH7100_RST_U74) |
- BIT_ULL_MASK(JH7100_RST_VP6_DRESET) |
- BIT_ULL_MASK(JH7100_RST_VP6_BRESET) |
+ BIT(JH7100_RST_U74 % 32) |
+ BIT(JH7100_RST_VP6_DRESET % 32) |
+ BIT(JH7100_RST_VP6_BRESET % 32),
/* STATUS1 */
- BIT_ULL_MASK(JH7100_RST_HIFI4_DRESET) |
- BIT_ULL_MASK(JH7100_RST_HIFI4_BRESET),
+ BIT(JH7100_RST_HIFI4_DRESET % 32) |
+ BIT(JH7100_RST_HIFI4_BRESET % 32),
/* STATUS2 */
- BIT_ULL_MASK(JH7100_RST_E24) |
+ BIT(JH7100_RST_E24 % 32),
/* STATUS3 */
0,
};
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.c b/drivers/reset/starfive/reset-starfive-jh71x0.c
index a689f4730ed7..55bbbd2de52c 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.c
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.c
@@ -8,7 +8,6 @@
#include <linux/bitmap.h>
#include <linux/device.h>
#include <linux/io.h>
-#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/iopoll.h>
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
@@ -21,7 +20,7 @@ struct jh71x0_reset {
spinlock_t lock;
void __iomem *assert;
void __iomem *status;
- const u64 *asserted;
+ const u32 *asserted;
};
static inline struct jh71x0_reset *
@@ -34,12 +33,12 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
- unsigned long offset = BIT_ULL_WORD(id);
- u64 mask = BIT_ULL_MASK(id);
- void __iomem *reg_assert = data->assert + offset * sizeof(u64);
- void __iomem *reg_status = data->status + offset * sizeof(u64);
- u64 done = data->asserted ? data->asserted[offset] & mask : 0;
- u64 value;
+ unsigned long offset = id / 32;
+ u32 mask = BIT(id % 32);
+ void __iomem *reg_assert = data->assert + offset * sizeof(u32);
+ void __iomem *reg_status = data->status + offset * sizeof(u32);
+ u32 done = data->asserted ? data->asserted[offset] & mask : 0;
+ u32 value;
unsigned long flags;
int ret;
@@ -48,15 +47,15 @@ static int jh71x0_reset_update(struct reset_controller_dev *rcdev,
spin_lock_irqsave(&data->lock, flags);
- value = readq(reg_assert);
+ value = readl(reg_assert);
if (assert)
value |= mask;
else
value &= ~mask;
- writeq(value, reg_assert);
+ writel(value, reg_assert);
/* if the associated clock is gated, deasserting might otherwise hang forever */
- ret = readq_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
+ ret = readl_poll_timeout_atomic(reg_status, value, (value & mask) == done, 0, 1000);
spin_unlock_irqrestore(&data->lock, flags);
return ret;
@@ -90,10 +89,10 @@ static int jh71x0_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct jh71x0_reset *data = jh71x0_reset_from(rcdev);
- unsigned long offset = BIT_ULL_WORD(id);
- u64 mask = BIT_ULL_MASK(id);
- void __iomem *reg_status = data->status + offset * sizeof(u64);
- u64 value = readq(reg_status);
+ unsigned long offset = id / 32;
+ u32 mask = BIT(id % 32);
+ void __iomem *reg_status = data->status + offset * sizeof(u32);
+ u32 value = readl(reg_status);
return !((value ^ data->asserted[offset]) & mask);
}
@@ -107,7 +106,7 @@ static const struct reset_control_ops jh71x0_reset_ops = {
int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
- const u64 *asserted, unsigned int nr_resets,
+ const u32 *asserted, unsigned int nr_resets,
struct module *owner)
{
struct jh71x0_reset *data;
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
index ac9e80dd3f59..db7d39a87f87 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
@@ -8,7 +8,7 @@
int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
- const u64 *asserted, unsigned int nr_resets,
+ const u32 *asserted, unsigned int nr_resets,
struct module *owner);
#endif /* __RESET_STARFIVE_JH71X0_H */
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (7 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 17:23 ` Conor Dooley
2023-02-22 9:13 ` Krzysztof Kozlowski
2023-02-21 2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
` (12 subsequent siblings)
21 siblings, 2 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../clock/starfive,jh7110-syscrg.yaml | 80 +++++++
MAINTAINERS | 8 +-
.../dt-bindings/clock/starfive,jh7110-crg.h | 207 ++++++++++++++++++
.../dt-bindings/reset/starfive,jh7110-crg.h | 142 ++++++++++++
4 files changed, 434 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
new file mode 100644
index 000000000000..ec81504dcb27
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 System Clock and Reset Generator
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+ compatible:
+ const: starfive,jh7110-syscrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC1 RMII reference
+ - description: GMAC1 RGMII RX
+ - description: External I2S TX bit clock
+ - description: External I2S TX left/right channel clock
+ - description: External I2S RX bit clock
+ - description: External I2S RX left/right channel clock
+ - description: External TDM clock
+ - description: External audio master clock
+
+ clock-names:
+ items:
+ - const: osc
+ - const: gmac1_rmii_refin
+ - const: gmac1_rgmii_rxin
+ - const: i2stx_bclk_ext
+ - const: i2stx_lrck_ext
+ - const: i2srx_bclk_ext
+ - const: i2srx_lrck_ext
+ - const: tdm_ext
+ - const: mclk_ext
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@13020000 {
+ compatible = "starfive,jh7110-syscrg";
+ reg = <0x13020000 0x10000>;
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 3fca3316b857..f37708e638a7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19913,10 +19913,11 @@ F: arch/riscv/boot/dts/starfive/
STARFIVE JH71X0 CLOCK DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
+M: Hal Feng <hal.feng@starfivetech.com>
S: Maintained
-F: Documentation/devicetree/bindings/clock/starfive,jh7100-*.yaml
+F: Documentation/devicetree/bindings/clock/starfive,jh71*.yaml
F: drivers/clk/starfive/clk-starfive-jh71*
-F: include/dt-bindings/clock/starfive-jh7100*.h
+F: include/dt-bindings/clock/starfive?jh71*.h
STARFIVE JH7100 PINCTRL DRIVER
M: Emil Renner Berthing <kernel@esmil.dk>
@@ -19928,10 +19929,11 @@ F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h
STARFIVE JH71X0 RESET CONTROLLER DRIVERS
M: Emil Renner Berthing <kernel@esmil.dk>
+M: Hal Feng <hal.feng@starfivetech.com>
S: Maintained
F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
F: drivers/reset/starfive/reset-starfive-jh71*
-F: include/dt-bindings/reset/starfive-jh7100.h
+F: include/dt-bindings/reset/starfive?jh71*.h
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
new file mode 100644
index 000000000000..cda199084bcf
--- /dev/null
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
+#define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
+
+/* SYSCRG clocks */
+#define JH7110_SYSCLK_CPU_ROOT 0
+#define JH7110_SYSCLK_CPU_CORE 1
+#define JH7110_SYSCLK_CPU_BUS 2
+#define JH7110_SYSCLK_GPU_ROOT 3
+#define JH7110_SYSCLK_PERH_ROOT 4
+#define JH7110_SYSCLK_BUS_ROOT 5
+#define JH7110_SYSCLK_NOCSTG_BUS 6
+#define JH7110_SYSCLK_AXI_CFG0 7
+#define JH7110_SYSCLK_STG_AXIAHB 8
+#define JH7110_SYSCLK_AHB0 9
+#define JH7110_SYSCLK_AHB1 10
+#define JH7110_SYSCLK_APB_BUS 11
+#define JH7110_SYSCLK_APB0 12
+#define JH7110_SYSCLK_PLL0_DIV2 13
+#define JH7110_SYSCLK_PLL1_DIV2 14
+#define JH7110_SYSCLK_PLL2_DIV2 15
+#define JH7110_SYSCLK_AUDIO_ROOT 16
+#define JH7110_SYSCLK_MCLK_INNER 17
+#define JH7110_SYSCLK_MCLK 18
+#define JH7110_SYSCLK_MCLK_OUT 19
+#define JH7110_SYSCLK_ISP_2X 20
+#define JH7110_SYSCLK_ISP_AXI 21
+#define JH7110_SYSCLK_GCLK0 22
+#define JH7110_SYSCLK_GCLK1 23
+#define JH7110_SYSCLK_GCLK2 24
+#define JH7110_SYSCLK_CORE 25
+#define JH7110_SYSCLK_CORE1 26
+#define JH7110_SYSCLK_CORE2 27
+#define JH7110_SYSCLK_CORE3 28
+#define JH7110_SYSCLK_CORE4 29
+#define JH7110_SYSCLK_DEBUG 30
+#define JH7110_SYSCLK_RTC_TOGGLE 31
+#define JH7110_SYSCLK_TRACE0 32
+#define JH7110_SYSCLK_TRACE1 33
+#define JH7110_SYSCLK_TRACE2 34
+#define JH7110_SYSCLK_TRACE3 35
+#define JH7110_SYSCLK_TRACE4 36
+#define JH7110_SYSCLK_TRACE_COM 37
+#define JH7110_SYSCLK_NOC_BUS_CPU_AXI 38
+#define JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI 39
+#define JH7110_SYSCLK_OSC_DIV2 40
+#define JH7110_SYSCLK_PLL1_DIV4 41
+#define JH7110_SYSCLK_PLL1_DIV8 42
+#define JH7110_SYSCLK_DDR_BUS 43
+#define JH7110_SYSCLK_DDR_AXI 44
+#define JH7110_SYSCLK_GPU_CORE 45
+#define JH7110_SYSCLK_GPU_CORE_CLK 46
+#define JH7110_SYSCLK_GPU_SYS_CLK 47
+#define JH7110_SYSCLK_GPU_APB 48
+#define JH7110_SYSCLK_GPU_RTC_TOGGLE 49
+#define JH7110_SYSCLK_NOC_BUS_GPU_AXI 50
+#define JH7110_SYSCLK_ISP_TOP_CORE 51
+#define JH7110_SYSCLK_ISP_TOP_AXI 52
+#define JH7110_SYSCLK_NOC_BUS_ISP_AXI 53
+#define JH7110_SYSCLK_HIFI4_CORE 54
+#define JH7110_SYSCLK_HIFI4_AXI 55
+#define JH7110_SYSCLK_AXI_CFG1_MAIN 56
+#define JH7110_SYSCLK_AXI_CFG1_AHB 57
+#define JH7110_SYSCLK_VOUT_SRC 58
+#define JH7110_SYSCLK_VOUT_AXI 59
+#define JH7110_SYSCLK_NOC_BUS_DISP_AXI 60
+#define JH7110_SYSCLK_VOUT_TOP_AHB 61
+#define JH7110_SYSCLK_VOUT_TOP_AXI 62
+#define JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK 63
+#define JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF 64
+#define JH7110_SYSCLK_JPEGC_AXI 65
+#define JH7110_SYSCLK_CODAJ12_AXI 66
+#define JH7110_SYSCLK_CODAJ12_CORE 67
+#define JH7110_SYSCLK_CODAJ12_APB 68
+#define JH7110_SYSCLK_VDEC_AXI 69
+#define JH7110_SYSCLK_WAVE511_AXI 70
+#define JH7110_SYSCLK_WAVE511_BPU 71
+#define JH7110_SYSCLK_WAVE511_VCE 72
+#define JH7110_SYSCLK_WAVE511_APB 73
+#define JH7110_SYSCLK_VDEC_JPG 74
+#define JH7110_SYSCLK_VDEC_MAIN 75
+#define JH7110_SYSCLK_NOC_BUS_VDEC_AXI 76
+#define JH7110_SYSCLK_VENC_AXI 77
+#define JH7110_SYSCLK_WAVE420L_AXI 78
+#define JH7110_SYSCLK_WAVE420L_BPU 79
+#define JH7110_SYSCLK_WAVE420L_VCE 80
+#define JH7110_SYSCLK_WAVE420L_APB 81
+#define JH7110_SYSCLK_NOC_BUS_VENC_AXI 82
+#define JH7110_SYSCLK_AXI_CFG0_MAIN_DIV 83
+#define JH7110_SYSCLK_AXI_CFG0_MAIN 84
+#define JH7110_SYSCLK_AXI_CFG0_HIFI4 85
+#define JH7110_SYSCLK_AXIMEM2_AXI 86
+#define JH7110_SYSCLK_QSPI_AHB 87
+#define JH7110_SYSCLK_QSPI_APB 88
+#define JH7110_SYSCLK_QSPI_REF_SRC 89
+#define JH7110_SYSCLK_QSPI_REF 90
+#define JH7110_SYSCLK_SDIO0_AHB 91
+#define JH7110_SYSCLK_SDIO1_AHB 92
+#define JH7110_SYSCLK_SDIO0_SDCARD 93
+#define JH7110_SYSCLK_SDIO1_SDCARD 94
+#define JH7110_SYSCLK_USB_125M 95
+#define JH7110_SYSCLK_NOC_BUS_STG_AXI 96
+#define JH7110_SYSCLK_GMAC1_AHB 97
+#define JH7110_SYSCLK_GMAC1_AXI 98
+#define JH7110_SYSCLK_GMAC_SRC 99
+#define JH7110_SYSCLK_GMAC1_GTXCLK 100
+#define JH7110_SYSCLK_GMAC1_RMII_RTX 101
+#define JH7110_SYSCLK_GMAC1_PTP 102
+#define JH7110_SYSCLK_GMAC1_RX 103
+#define JH7110_SYSCLK_GMAC1_RX_INV 104
+#define JH7110_SYSCLK_GMAC1_TX 105
+#define JH7110_SYSCLK_GMAC1_TX_INV 106
+#define JH7110_SYSCLK_GMAC1_GTXC 107
+#define JH7110_SYSCLK_GMAC0_GTXCLK 108
+#define JH7110_SYSCLK_GMAC0_PTP 109
+#define JH7110_SYSCLK_GMAC_PHY 110
+#define JH7110_SYSCLK_GMAC0_GTXC 111
+#define JH7110_SYSCLK_IOMUX_APB 112
+#define JH7110_SYSCLK_MAILBOX_APB 113
+#define JH7110_SYSCLK_INT_CTRL_APB 114
+#define JH7110_SYSCLK_CAN0_APB 115
+#define JH7110_SYSCLK_CAN0_TIMER 116
+#define JH7110_SYSCLK_CAN0_CAN 117
+#define JH7110_SYSCLK_CAN1_APB 118
+#define JH7110_SYSCLK_CAN1_TIMER 119
+#define JH7110_SYSCLK_CAN1_CAN 120
+#define JH7110_SYSCLK_PWM_APB 121
+#define JH7110_SYSCLK_WDT_APB 122
+#define JH7110_SYSCLK_WDT_CORE 123
+#define JH7110_SYSCLK_TIMER_APB 124
+#define JH7110_SYSCLK_TIMER0 125
+#define JH7110_SYSCLK_TIMER1 126
+#define JH7110_SYSCLK_TIMER2 127
+#define JH7110_SYSCLK_TIMER3 128
+#define JH7110_SYSCLK_TEMP_APB 129
+#define JH7110_SYSCLK_TEMP_CORE 130
+#define JH7110_SYSCLK_SPI0_APB 131
+#define JH7110_SYSCLK_SPI1_APB 132
+#define JH7110_SYSCLK_SPI2_APB 133
+#define JH7110_SYSCLK_SPI3_APB 134
+#define JH7110_SYSCLK_SPI4_APB 135
+#define JH7110_SYSCLK_SPI5_APB 136
+#define JH7110_SYSCLK_SPI6_APB 137
+#define JH7110_SYSCLK_I2C0_APB 138
+#define JH7110_SYSCLK_I2C1_APB 139
+#define JH7110_SYSCLK_I2C2_APB 140
+#define JH7110_SYSCLK_I2C3_APB 141
+#define JH7110_SYSCLK_I2C4_APB 142
+#define JH7110_SYSCLK_I2C5_APB 143
+#define JH7110_SYSCLK_I2C6_APB 144
+#define JH7110_SYSCLK_UART0_APB 145
+#define JH7110_SYSCLK_UART0_CORE 146
+#define JH7110_SYSCLK_UART1_APB 147
+#define JH7110_SYSCLK_UART1_CORE 148
+#define JH7110_SYSCLK_UART2_APB 149
+#define JH7110_SYSCLK_UART2_CORE 150
+#define JH7110_SYSCLK_UART3_APB 151
+#define JH7110_SYSCLK_UART3_CORE 152
+#define JH7110_SYSCLK_UART4_APB 153
+#define JH7110_SYSCLK_UART4_CORE 154
+#define JH7110_SYSCLK_UART5_APB 155
+#define JH7110_SYSCLK_UART5_CORE 156
+#define JH7110_SYSCLK_PWMDAC_APB 157
+#define JH7110_SYSCLK_PWMDAC_CORE 158
+#define JH7110_SYSCLK_SPDIF_APB 159
+#define JH7110_SYSCLK_SPDIF_CORE 160
+#define JH7110_SYSCLK_I2STX0_APB 161
+#define JH7110_SYSCLK_I2STX0_BCLK_MST 162
+#define JH7110_SYSCLK_I2STX0_BCLK_MST_INV 163
+#define JH7110_SYSCLK_I2STX0_LRCK_MST 164
+#define JH7110_SYSCLK_I2STX0_BCLK 165
+#define JH7110_SYSCLK_I2STX0_BCLK_INV 166
+#define JH7110_SYSCLK_I2STX0_LRCK 167
+#define JH7110_SYSCLK_I2STX1_APB 168
+#define JH7110_SYSCLK_I2STX1_BCLK_MST 169
+#define JH7110_SYSCLK_I2STX1_BCLK_MST_INV 170
+#define JH7110_SYSCLK_I2STX1_LRCK_MST 171
+#define JH7110_SYSCLK_I2STX1_BCLK 172
+#define JH7110_SYSCLK_I2STX1_BCLK_INV 173
+#define JH7110_SYSCLK_I2STX1_LRCK 174
+#define JH7110_SYSCLK_I2SRX_APB 175
+#define JH7110_SYSCLK_I2SRX_BCLK_MST 176
+#define JH7110_SYSCLK_I2SRX_BCLK_MST_INV 177
+#define JH7110_SYSCLK_I2SRX_LRCK_MST 178
+#define JH7110_SYSCLK_I2SRX_BCLK 179
+#define JH7110_SYSCLK_I2SRX_BCLK_INV 180
+#define JH7110_SYSCLK_I2SRX_LRCK 181
+#define JH7110_SYSCLK_PDM_DMIC 182
+#define JH7110_SYSCLK_PDM_APB 183
+#define JH7110_SYSCLK_TDM_AHB 184
+#define JH7110_SYSCLK_TDM_APB 185
+#define JH7110_SYSCLK_TDM_INTERNAL 186
+#define JH7110_SYSCLK_TDM_TDM 187
+#define JH7110_SYSCLK_TDM_TDM_INV 188
+#define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
+
+#define JH7110_SYSCLK_PLL0_OUT 190
+#define JH7110_SYSCLK_PLL1_OUT 191
+#define JH7110_SYSCLK_PLL2_OUT 192
+
+#define JH7110_SYSCLK_END 193
+
+#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
new file mode 100644
index 000000000000..b88216a4fe40
--- /dev/null
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -0,0 +1,142 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__
+
+/* SYSCRG resets */
+#define JH7110_SYSRST_JTAG_APB 0
+#define JH7110_SYSRST_SYSCON_APB 1
+#define JH7110_SYSRST_IOMUX_APB 2
+#define JH7110_SYSRST_BUS 3
+#define JH7110_SYSRST_DEBUG 4
+#define JH7110_SYSRST_CORE0 5
+#define JH7110_SYSRST_CORE1 6
+#define JH7110_SYSRST_CORE2 7
+#define JH7110_SYSRST_CORE3 8
+#define JH7110_SYSRST_CORE4 9
+#define JH7110_SYSRST_CORE0_ST 10
+#define JH7110_SYSRST_CORE1_ST 11
+#define JH7110_SYSRST_CORE2_ST 12
+#define JH7110_SYSRST_CORE3_ST 13
+#define JH7110_SYSRST_CORE4_ST 14
+#define JH7110_SYSRST_TRACE0 15
+#define JH7110_SYSRST_TRACE1 16
+#define JH7110_SYSRST_TRACE2 17
+#define JH7110_SYSRST_TRACE3 18
+#define JH7110_SYSRST_TRACE4 19
+#define JH7110_SYSRST_TRACE_COM 20
+#define JH7110_SYSRST_GPU_APB 21
+#define JH7110_SYSRST_GPU_DOMA 22
+#define JH7110_SYSRST_NOC_BUS_APB 23
+#define JH7110_SYSRST_NOC_BUS_AXICFG0_AXI 24
+#define JH7110_SYSRST_NOC_BUS_CPU_AXI 25
+#define JH7110_SYSRST_NOC_BUS_DISP_AXI 26
+#define JH7110_SYSRST_NOC_BUS_GPU_AXI 27
+#define JH7110_SYSRST_NOC_BUS_ISP_AXI 28
+#define JH7110_SYSRST_NOC_BUS_DDRC 29
+#define JH7110_SYSRST_NOC_BUS_STG_AXI 30
+#define JH7110_SYSRST_NOC_BUS_VDEC_AXI 31
+
+#define JH7110_SYSRST_NOC_BUS_VENC_AXI 32
+#define JH7110_SYSRST_AXI_CFG1_AHB 33
+#define JH7110_SYSRST_AXI_CFG1_MAIN 34
+#define JH7110_SYSRST_AXI_CFG0_MAIN 35
+#define JH7110_SYSRST_AXI_CFG0_MAIN_DIV 36
+#define JH7110_SYSRST_AXI_CFG0_HIFI4 37
+#define JH7110_SYSRST_DDR_AXI 38
+#define JH7110_SYSRST_DDR_OSC 39
+#define JH7110_SYSRST_DDR_APB 40
+#define JH7110_SYSRST_ISP_TOP 41
+#define JH7110_SYSRST_ISP_TOP_AXI 42
+#define JH7110_SYSRST_VOUT_TOP_SRC 43
+#define JH7110_SYSRST_CODAJ12_AXI 44
+#define JH7110_SYSRST_CODAJ12_CORE 45
+#define JH7110_SYSRST_CODAJ12_APB 46
+#define JH7110_SYSRST_WAVE511_AXI 47
+#define JH7110_SYSRST_WAVE511_BPU 48
+#define JH7110_SYSRST_WAVE511_VCE 49
+#define JH7110_SYSRST_WAVE511_APB 50
+#define JH7110_SYSRST_VDEC_JPG 51
+#define JH7110_SYSRST_VDEC_MAIN 52
+#define JH7110_SYSRST_AXIMEM0_AXI 53
+#define JH7110_SYSRST_WAVE420L_AXI 54
+#define JH7110_SYSRST_WAVE420L_BPU 55
+#define JH7110_SYSRST_WAVE420L_VCE 56
+#define JH7110_SYSRST_WAVE420L_APB 57
+#define JH7110_SYSRST_AXIMEM1_AXI 58
+#define JH7110_SYSRST_AXIMEM2_AXI 59
+#define JH7110_SYSRST_INTMEM 60
+#define JH7110_SYSRST_QSPI_AHB 61
+#define JH7110_SYSRST_QSPI_APB 62
+#define JH7110_SYSRST_QSPI_REF 63
+
+#define JH7110_SYSRST_SDIO0_AHB 64
+#define JH7110_SYSRST_SDIO1_AHB 65
+#define JH7110_SYSRST_GMAC1_AXI 66
+#define JH7110_SYSRST_GMAC1_AHB 67
+#define JH7110_SYSRST_MAILBOX_APB 68
+#define JH7110_SYSRST_SPI0_APB 69
+#define JH7110_SYSRST_SPI1_APB 70
+#define JH7110_SYSRST_SPI2_APB 71
+#define JH7110_SYSRST_SPI3_APB 72
+#define JH7110_SYSRST_SPI4_APB 73
+#define JH7110_SYSRST_SPI5_APB 74
+#define JH7110_SYSRST_SPI6_APB 75
+#define JH7110_SYSRST_I2C0_APB 76
+#define JH7110_SYSRST_I2C1_APB 77
+#define JH7110_SYSRST_I2C2_APB 78
+#define JH7110_SYSRST_I2C3_APB 79
+#define JH7110_SYSRST_I2C4_APB 80
+#define JH7110_SYSRST_I2C5_APB 81
+#define JH7110_SYSRST_I2C6_APB 82
+#define JH7110_SYSRST_UART0_APB 83
+#define JH7110_SYSRST_UART0_CORE 84
+#define JH7110_SYSRST_UART1_APB 85
+#define JH7110_SYSRST_UART1_CORE 86
+#define JH7110_SYSRST_UART2_APB 87
+#define JH7110_SYSRST_UART2_CORE 88
+#define JH7110_SYSRST_UART3_APB 89
+#define JH7110_SYSRST_UART3_CORE 90
+#define JH7110_SYSRST_UART4_APB 91
+#define JH7110_SYSRST_UART4_CORE 92
+#define JH7110_SYSRST_UART5_APB 93
+#define JH7110_SYSRST_UART5_CORE 94
+#define JH7110_SYSRST_SPDIF_APB 95
+
+#define JH7110_SYSRST_PWMDAC_APB 96
+#define JH7110_SYSRST_PDM_DMIC 97
+#define JH7110_SYSRST_PDM_APB 98
+#define JH7110_SYSRST_I2SRX_APB 99
+#define JH7110_SYSRST_I2SRX_BCLK 100
+#define JH7110_SYSRST_I2STX0_APB 101
+#define JH7110_SYSRST_I2STX0_BCLK 102
+#define JH7110_SYSRST_I2STX1_APB 103
+#define JH7110_SYSRST_I2STX1_BCLK 104
+#define JH7110_SYSRST_TDM_AHB 105
+#define JH7110_SYSRST_TDM_CORE 106
+#define JH7110_SYSRST_TDM_APB 107
+#define JH7110_SYSRST_PWM_APB 108
+#define JH7110_SYSRST_WDT_APB 109
+#define JH7110_SYSRST_WDT_CORE 110
+#define JH7110_SYSRST_CAN0_APB 111
+#define JH7110_SYSRST_CAN0_CORE 112
+#define JH7110_SYSRST_CAN0_TIMER 113
+#define JH7110_SYSRST_CAN1_APB 114
+#define JH7110_SYSRST_CAN1_CORE 115
+#define JH7110_SYSRST_CAN1_TIMER 116
+#define JH7110_SYSRST_TIMER_APB 117
+#define JH7110_SYSRST_TIMER0 118
+#define JH7110_SYSRST_TIMER1 119
+#define JH7110_SYSRST_TIMER2 120
+#define JH7110_SYSRST_TIMER3 121
+#define JH7110_SYSRST_INT_CTRL_APB 122
+#define JH7110_SYSRST_TEMP_APB 123
+#define JH7110_SYSRST_TEMP_CORE 124
+#define JH7110_SYSRST_JTAG_CERTIFICATION 125
+
+#define JH7110_SYSRST_END 126
+
+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (8 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 17:26 ` Conor Dooley
2023-03-09 14:22 ` Geert Uytterhoeven
2023-02-21 2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
` (11 subsequent siblings)
21 siblings, 2 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add bindings for the always-on clock and reset generator (AONCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../clock/starfive,jh7110-aoncrg.yaml | 76 +++++++++++++++++++
.../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++++
.../dt-bindings/reset/starfive,jh7110-crg.h | 12 +++
3 files changed, 106 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
new file mode 100644
index 000000000000..a3cf0570d950
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Always-On Clock and Reset Generator
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+ compatible:
+ const: starfive,jh7110-aoncrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main Oscillator (24 MHz)
+ - description: RTC Oscillator (32.768 kHz)
+ - description: GMAC0 RMII reference
+ - description: GMAC0 RGMII RX
+ - description: STG AXI/AHB
+ - description: APB Bus
+ - description: GMAC0 GTX
+
+ clock-names:
+ items:
+ - const: osc
+ - const: rtc_osc
+ - const: gmac0_rmii_refin
+ - const: gmac0_rgmii_rxin
+ - const: stg_axiahb
+ - const: apb_bus
+ - const: gmac0_gtxclk
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+ clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ reg = <0x17000000 0x10000>;
+ clocks = <&osc>, <&rtc_osc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+ clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
+ "gmac0_rgmii_rxin", "stg_axiahb",
+ "apb_bus", "gmac0_gtxclk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index cda199084bcf..5e4f21ca0642 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -204,4 +204,22 @@
#define JH7110_SYSCLK_END 193
+/* AONCRG clocks */
+#define JH7110_AONCLK_OSC_DIV4 0
+#define JH7110_AONCLK_APB_FUNC 1
+#define JH7110_AONCLK_GMAC0_AHB 2
+#define JH7110_AONCLK_GMAC0_AXI 3
+#define JH7110_AONCLK_GMAC0_RMII_RTX 4
+#define JH7110_AONCLK_GMAC0_TX 5
+#define JH7110_AONCLK_GMAC0_TX_INV 6
+#define JH7110_AONCLK_GMAC0_RX 7
+#define JH7110_AONCLK_GMAC0_RX_INV 8
+#define JH7110_AONCLK_OTPC_APB 9
+#define JH7110_AONCLK_RTC_APB 10
+#define JH7110_AONCLK_RTC_INTERNAL 11
+#define JH7110_AONCLK_RTC_32K 12
+#define JH7110_AONCLK_RTC_CAL 13
+
+#define JH7110_AONCLK_END 14
+
#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
diff --git a/include/dt-bindings/reset/starfive,jh7110-crg.h b/include/dt-bindings/reset/starfive,jh7110-crg.h
index b88216a4fe40..d78e38690ceb 100644
--- a/include/dt-bindings/reset/starfive,jh7110-crg.h
+++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
@@ -139,4 +139,16 @@
#define JH7110_SYSRST_END 126
+/* AONCRG resets */
+#define JH7110_AONRST_GMAC0_AXI 0
+#define JH7110_AONRST_GMAC0_AHB 1
+#define JH7110_AONRST_IOMUX 2
+#define JH7110_AONRST_PMU_APB 3
+#define JH7110_AONRST_PMU_WKUP 4
+#define JH7110_AONRST_RTC_APB 5
+#define JH7110_AONRST_RTC_CAL 6
+#define JH7110_AONRST_RTC_32K 7
+
+#define JH7110_AONRST_END 8
+
#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (9 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 15:12 ` Conor Dooley
2023-02-26 16:07 ` Emil Renner Berthing
2023-02-21 2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
` (10 subsequent siblings)
21 siblings, 2 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add driver for the StarFive JH7110 system clock controller and
register an auxiliary device for system reset controller which
is named as "reset-sys".
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 11 +
drivers/clk/starfive/Makefile | 2 +
.../clk/starfive/clk-starfive-jh7110-sys.c | 448 ++++++++++++++++++
drivers/clk/starfive/clk-starfive-jh71x0.c | 50 ++
drivers/clk/starfive/clk-starfive-jh71x0.h | 8 +
5 files changed, 519 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 594d516dcb38..4640d0665d1c 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -20,3 +20,14 @@ config CLK_STARFIVE_JH7100_AUDIO
help
Say Y or M here to support the audio clocks on the StarFive JH7100
SoC.
+
+config CLK_STARFIVE_JH7110_SYS
+ bool "StarFive JH7110 system clock support"
+ depends on SOC_STARFIVE || COMPILE_TEST
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_JH71X0
+ select RESET_STARFIVE_JH7110
+ default SOC_STARFIVE
+ help
+ Say yes here to support the system clock controller on the
+ StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 82edfa9f9cb8..5ca4e887fb9c 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -3,3 +3,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
+
+obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
new file mode 100644
index 000000000000..6e230b81a387
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -0,0 +1,448 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 System Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh71x0.h"
+
+/* external clocks */
+#define JH7110_SYSCLK_OSC (JH7110_SYSCLK_END + 0)
+#define JH7110_SYSCLK_GMAC1_RMII_REFIN (JH7110_SYSCLK_END + 1)
+#define JH7110_SYSCLK_GMAC1_RGMII_RXIN (JH7110_SYSCLK_END + 2)
+#define JH7110_SYSCLK_I2STX_BCLK_EXT (JH7110_SYSCLK_END + 3)
+#define JH7110_SYSCLK_I2STX_LRCK_EXT (JH7110_SYSCLK_END + 4)
+#define JH7110_SYSCLK_I2SRX_BCLK_EXT (JH7110_SYSCLK_END + 5)
+#define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6)
+#define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7)
+#define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8)
+
+static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
+ /* root */
+ JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_PLL0_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
+ JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
+ JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
+ JH7110_SYSCLK_PLL2_OUT,
+ JH7110_SYSCLK_PLL1_OUT),
+ JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
+ JH7110_SYSCLK_PLL0_OUT,
+ JH7110_SYSCLK_PLL2_OUT),
+ JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_PLL2_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
+ JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
+ JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
+ JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
+ JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
+ JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
+ JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
+ JH7110_SYSCLK_MCLK_INNER,
+ JH7110_SYSCLK_MCLK_EXT),
+ JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
+ JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
+ JH7110_SYSCLK_PLL2_OUT,
+ JH7110_SYSCLK_PLL1_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
+ JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
+ JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
+ JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
+ /* cores */
+ JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
+ JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
+ JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
+ /* noc */
+ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_CPU_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_AXI_CFG0),
+ /* ddr */
+ JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
+ JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
+ JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
+ JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
+ JH7110_SYSCLK_OSC_DIV2,
+ JH7110_SYSCLK_PLL1_DIV2,
+ JH7110_SYSCLK_PLL1_DIV4,
+ JH7110_SYSCLK_PLL1_DIV8),
+ JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IGNORE_UNUSED, JH7110_SYSCLK_DDR_BUS),
+ /* gpu */
+ JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
+ JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
+ JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
+ JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
+ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
+ /* isp */
+ JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
+ JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
+ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
+ JH7110_SYSCLK_ISP_AXI),
+ /* hifi4 */
+ JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
+ JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
+ /* axi_cfg1 */
+ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_ISP_AXI),
+ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AHB0),
+ /* vout */
+ JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
+ JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
+ JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
+ JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
+ JH7110_SYSCLK_MCLK),
+ JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
+ JH7110_SYSCLK_OSC),
+ /* jpegc */
+ JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
+ JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
+ /* vdec */
+ JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
+ JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
+ JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
+ JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
+ JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_JPEGC_AXI),
+ JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_VDEC_AXI),
+ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
+ /* venc */
+ JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
+ JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
+ JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI),
+ /* axi_cfg0 */
+ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AHB1),
+ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AXI_CFG0),
+ JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_HIFI4_AXI),
+ /* intmem */
+ JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_AXI_CFG0),
+ /* qspi */
+ JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB1),
+ JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB_BUS),
+ JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
+ JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", CLK_IGNORE_UNUSED, 2,
+ JH7110_SYSCLK_OSC,
+ JH7110_SYSCLK_QSPI_REF_SRC),
+ /* sdio */
+ JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB0),
+ JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB0),
+ JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", CLK_IGNORE_UNUSED, 15,
+ JH7110_SYSCLK_AXI_CFG0),
+ JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", CLK_IGNORE_UNUSED, 15,
+ JH7110_SYSCLK_AXI_CFG0),
+ /* stg */
+ JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
+ JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_NOCSTG_BUS),
+ /* gmac1 */
+ JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
+ JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
+ JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
+ JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
+ JH7110_SYSCLK_GMAC1_RMII_REFIN),
+ JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
+ JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
+ JH7110_SYSCLK_GMAC1_RGMII_RXIN,
+ JH7110_SYSCLK_GMAC1_RMII_RTX),
+ JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
+ JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", 0, 2,
+ JH7110_SYSCLK_GMAC1_GTXCLK,
+ JH7110_SYSCLK_GMAC1_RMII_RTX),
+ JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
+ JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
+ /* gmac0 */
+ JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
+ JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
+ JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
+ JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
+ /* apb misc */
+ JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB_BUS),
+ /* can0 */
+ JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
+ JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
+ /* can1 */
+ JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
+ JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
+ /* pwm */
+ JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
+ /* wdt */
+ JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
+ /* timer */
+ JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", CLK_IGNORE_UNUSED,
+ JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
+ JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
+ JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
+ JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
+ /* temp sensor */
+ JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
+ /* spi */
+ JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
+ /* i2c */
+ JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
+ JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
+ /* uart */
+ JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
+ JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
+ JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
+ JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
+ JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
+ JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
+ /* pwmdac */
+ JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
+ /* spdif */
+ JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
+ /* i2stx0 */
+ JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
+ JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
+ JH7110_SYSCLK_I2STX0_BCLK_MST),
+ JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
+ JH7110_SYSCLK_I2STX0_BCLK_MST),
+ JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
+ JH7110_SYSCLK_I2STX0_BCLK_MST,
+ JH7110_SYSCLK_I2STX_BCLK_EXT),
+ JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
+ JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
+ JH7110_SYSCLK_I2STX0_LRCK_MST,
+ JH7110_SYSCLK_I2STX_LRCK_EXT),
+ /* i2stx1 */
+ JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
+ JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
+ JH7110_SYSCLK_I2STX1_BCLK_MST),
+ JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
+ JH7110_SYSCLK_I2STX1_BCLK_MST),
+ JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
+ JH7110_SYSCLK_I2STX1_BCLK_MST,
+ JH7110_SYSCLK_I2STX_BCLK_EXT),
+ JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
+ JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
+ JH7110_SYSCLK_I2STX1_LRCK_MST,
+ JH7110_SYSCLK_I2STX_LRCK_EXT),
+ /* i2srx */
+ JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
+ JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
+ JH7110_SYSCLK_I2SRX_BCLK_MST),
+ JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
+ JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
+ JH7110_SYSCLK_I2SRX_BCLK_MST),
+ JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
+ JH7110_SYSCLK_I2SRX_BCLK_MST,
+ JH7110_SYSCLK_I2SRX_BCLK_EXT),
+ JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
+ JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
+ JH7110_SYSCLK_I2SRX_LRCK_MST,
+ JH7110_SYSCLK_I2SRX_LRCK_EXT),
+ /* pdm */
+ JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
+ JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
+ /* tdm */
+ JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
+ JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
+ JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
+ JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
+ JH7110_SYSCLK_TDM_INTERNAL,
+ JH7110_SYSCLK_TDM_EXT),
+ JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
+ /* jtag */
+ JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
+ JH7110_SYSCLK_OSC),
+};
+
+static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_SYSCLK_PLL0_OUT)
+ return &priv->reg[idx].hw;
+
+ if (idx < JH7110_SYSCLK_END)
+ return priv->pll[idx - JH7110_SYSCLK_PLL0_OUT];
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int __init jh7110_syscrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ dev_set_drvdata(priv->dev, (void *)(&priv->base));
+
+ /* 24MHz -> 1000.0MHz */
+ priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
+ "osc", 0, 125, 3);
+ if (IS_ERR(priv->pll[0]))
+ return PTR_ERR(priv->pll[0]);
+
+ /* 24MHz -> 1066.0MHz */
+ priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
+ "osc", 0, 533, 12);
+ if (IS_ERR(priv->pll[1]))
+ return PTR_ERR(priv->pll[1]);
+
+ /* 24MHz -> 1188.0MHz */
+ priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
+ "osc", 0, 99, 2);
+ if (IS_ERR(priv->pll[2]))
+ return PTR_ERR(priv->pll[2]);
+
+ for (idx = 0; idx < JH7110_SYSCLK_PLL0_OUT; idx++) {
+ u32 max = jh7110_sysclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_sysclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_sysclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_sysclk_data[idx].parents[i];
+
+ if (pidx < JH7110_SYSCLK_PLL0_OUT)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx < JH7110_SYSCLK_END)
+ parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
+ else if (pidx == JH7110_SYSCLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN)
+ parents[i].fw_name = "gmac1_rmii_refin";
+ else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN)
+ parents[i].fw_name = "gmac1_rgmii_rxin";
+ else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT)
+ parents[i].fw_name = "i2stx_bclk_ext";
+ else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT)
+ parents[i].fw_name = "i2stx_lrck_ext";
+ else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT)
+ parents[i].fw_name = "i2srx_bclk_ext";
+ else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT)
+ parents[i].fw_name = "i2srx_lrck_ext";
+ else if (pidx == JH7110_SYSCLK_TDM_EXT)
+ parents[i].fw_name = "tdm_ext";
+ else if (pidx == JH7110_SYSCLK_MCLK_EXT)
+ parents[i].fw_name = "mclk_ext";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh7110_reset_controller_register(priv, "reset-sys", 0);
+}
+
+static const struct of_device_id jh7110_syscrg_match[] = {
+ { .compatible = "starfive,jh7110-syscrg" },
+ { /* sentinel */ }
+};
+
+static struct platform_driver jh7110_syscrg_driver = {
+ .driver = {
+ .name = "clk-starfive-jh7110-sys",
+ .of_match_table = jh7110_syscrg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe);
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c
index b372083d11c3..a8c60630ae73 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
@@ -5,6 +5,7 @@
* Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
*/
+#include <linux/auxiliary_bus.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/device.h>
@@ -331,3 +332,52 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
return &jh71x0_clk_inv_ops;
}
EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
+
+#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS)
+
+static void jh7110_reset_unregister_adev(void *_adev)
+{
+ struct auxiliary_device *adev = _adev;
+
+ auxiliary_device_delete(adev);
+}
+
+static void jh7110_reset_adev_release(struct device *dev)
+{
+ struct auxiliary_device *adev = to_auxiliary_dev(dev);
+
+ auxiliary_device_uninit(adev);
+}
+
+int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id)
+{
+ struct auxiliary_device *adev;
+ int ret;
+
+ adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
+ if (!adev)
+ return -ENOMEM;
+
+ adev->name = adev_name;
+ adev->dev.parent = priv->dev;
+ adev->dev.release = jh7110_reset_adev_release;
+ adev->id = adev_id;
+
+ ret = auxiliary_device_init(adev);
+ if (ret)
+ return ret;
+
+ ret = auxiliary_device_add(adev);
+ if (ret) {
+ auxiliary_device_uninit(adev);
+ return ret;
+ }
+
+ return devm_add_action_or_reset(priv->dev,
+ jh7110_reset_unregister_adev, adev);
+}
+EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
+
+#endif
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
index baf4b5cb4b8a..0cbf9d94257a 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
@@ -111,4 +111,12 @@ struct jh71x0_clk_priv {
const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
+#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS)
+
+int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
+ const char *adev_name,
+ u32 adev_id);
+
+#endif
+
#endif
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (10 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-26 17:34 ` Emil Renner Berthing
2023-02-21 2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
` (9 subsequent siblings)
21 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add driver for the StarFive JH7110 always-on clock controller
and register an auxiliary device for always-on reset controller
which is named as "reset-aon".
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 11 ++
drivers/clk/starfive/Makefile | 1 +
.../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++++++++++++++++
3 files changed, 168 insertions(+)
create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 4640d0665d1c..2aa664f2cdee 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -31,3 +31,14 @@ config CLK_STARFIVE_JH7110_SYS
help
Say yes here to support the system clock controller on the
StarFive JH7110 SoC.
+
+config CLK_STARFIVE_JH7110_AON
+ tristate "StarFive JH7110 always-on clock support"
+ depends on CLK_STARFIVE_JH7110_SYS
+ select AUXILIARY_BUS
+ select CLK_STARFIVE_JH71X0
+ select RESET_STARFIVE_JH7110
+ default CLK_STARFIVE_JH7110_SYS
+ help
+ Say yes here to support the always-on clock controller on the
+ StarFive JH7110 SoC.
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index 5ca4e887fb9c..f3df7d957b1e 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -5,3 +5,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
+obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
new file mode 100644
index 000000000000..da808dc93048
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -0,0 +1,156 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 Always-On Clock Driver
+ *
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh71x0.h"
+
+/* external clocks */
+#define JH7110_AONCLK_OSC (JH7110_AONCLK_END + 0)
+#define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 1)
+#define JH7110_AONCLK_GMAC0_RMII_REFIN (JH7110_AONCLK_END + 2)
+#define JH7110_AONCLK_GMAC0_RGMII_RXIN (JH7110_AONCLK_END + 3)
+#define JH7110_AONCLK_STG_AXIAHB (JH7110_AONCLK_END + 4)
+#define JH7110_AONCLK_APB_BUS (JH7110_AONCLK_END + 5)
+#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 6)
+
+static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
+ /* source */
+ JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
+ JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
+ JH7110_AONCLK_OSC_DIV4,
+ JH7110_AONCLK_OSC),
+ /* gmac0 */
+ JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
+ JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
+ JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
+ JH7110_AONCLK_GMAC0_RMII_REFIN),
+ JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", 0, 2,
+ JH7110_AONCLK_GMAC0_GTXCLK,
+ JH7110_AONCLK_GMAC0_RMII_RTX),
+ JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
+ JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
+ JH7110_AONCLK_GMAC0_RGMII_RXIN,
+ JH7110_AONCLK_GMAC0_RMII_RTX),
+ JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
+ /* otpc */
+ JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", CLK_IGNORE_UNUSED, JH7110_AONCLK_APB_BUS),
+ /* rtc */
+ JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", CLK_IGNORE_UNUSED, JH7110_AONCLK_APB_BUS),
+ JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
+ JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
+ JH7110_AONCLK_RTC_OSC,
+ JH7110_AONCLK_RTC_INTERNAL),
+ JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
+};
+
+static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct jh71x0_clk_priv *priv = data;
+ unsigned int idx = clkspec->args[0];
+
+ if (idx < JH7110_AONCLK_END)
+ return &priv->reg[idx].hw;
+
+ return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_aoncrg_probe(struct platform_device *pdev)
+{
+ struct jh71x0_clk_priv *priv;
+ unsigned int idx;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ struct_size(priv, reg, JH7110_AONCLK_END),
+ GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ spin_lock_init(&priv->rmw_lock);
+ priv->dev = &pdev->dev;
+ priv->base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(priv->base))
+ return PTR_ERR(priv->base);
+
+ dev_set_drvdata(priv->dev, (void *)(&priv->base));
+
+ for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
+ u32 max = jh7110_aonclk_data[idx].max;
+ struct clk_parent_data parents[4] = {};
+ struct clk_init_data init = {
+ .name = jh7110_aonclk_data[idx].name,
+ .ops = starfive_jh71x0_clk_ops(max),
+ .parent_data = parents,
+ .num_parents =
+ ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
+ .flags = jh7110_aonclk_data[idx].flags,
+ };
+ struct jh71x0_clk *clk = &priv->reg[idx];
+ unsigned int i;
+
+ for (i = 0; i < init.num_parents; i++) {
+ unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
+
+ if (pidx < JH7110_AONCLK_END)
+ parents[i].hw = &priv->reg[pidx].hw;
+ else if (pidx == JH7110_AONCLK_OSC)
+ parents[i].fw_name = "osc";
+ else if (pidx == JH7110_AONCLK_RTC_OSC)
+ parents[i].fw_name = "rtc_osc";
+ else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
+ parents[i].fw_name = "gmac0_rmii_refin";
+ else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
+ parents[i].fw_name = "gmac0_rgmii_rxin";
+ else if (pidx == JH7110_AONCLK_STG_AXIAHB)
+ parents[i].fw_name = "stg_axiahb";
+ else if (pidx == JH7110_AONCLK_APB_BUS)
+ parents[i].fw_name = "apb_bus";
+ else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
+ parents[i].fw_name = "gmac0_gtxclk";
+ }
+
+ clk->hw.init = &init;
+ clk->idx = idx;
+ clk->max_div = max & JH71X0_CLK_DIV_MASK;
+
+ ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
+ if (ret)
+ return ret;
+ }
+
+ ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
+ if (ret)
+ return ret;
+
+ return jh7110_reset_controller_register(priv, "reset-aon", 1);
+}
+
+static const struct of_device_id jh7110_aoncrg_match[] = {
+ { .compatible = "starfive,jh7110-aoncrg" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match);
+
+static struct platform_driver jh7110_aoncrg_driver = {
+ .probe = jh7110_aoncrg_probe,
+ .driver = {
+ .name = "clk-starfive-jh7110-aon",
+ .of_match_table = jh7110_aoncrg_match,
+ },
+};
+module_platform_driver(jh7110_aoncrg_driver);
+
+MODULE_AUTHOR("Emil Renner Berthing");
+MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
+MODULE_LICENSE("GPL");
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (11 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 15:33 ` Emil Renner Berthing
2023-02-21 2:46 ` [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
` (8 subsequent siblings)
21 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
Add auxiliary driver to support StarFive JH7110 system
and always-on resets.
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
drivers/reset/starfive/Kconfig | 8 +++
drivers/reset/starfive/Makefile | 1 +
.../reset/starfive/reset-starfive-jh7110.c | 64 +++++++++++++++++++
.../reset/starfive/reset-starfive-jh71x0.h | 6 ++
4 files changed, 79 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index 9d15c4110e40..fab1a081af17 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -10,3 +10,11 @@ config RESET_STARFIVE_JH7100
default SOC_STARFIVE
help
This enables the reset controller driver for the StarFive JH7100 SoC.
+
+config RESET_STARFIVE_JH7110
+ bool "StarFive JH7110 Reset Driver"
+ depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS
+ select RESET_STARFIVE_JH71X0
+ default CLK_STARFIVE_JH7110_SYS
+ help
+ This enables the reset controller driver for the StarFive JH7110 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index f6aa12466fad..7a44b66fb9d5 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -2,3 +2,4 @@
obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
+obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
new file mode 100644
index 000000000000..83577d1b7fc6
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Reset driver for the StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/auxiliary_bus.h>
+
+#include "reset-starfive-jh71x0.h"
+
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+static int jh7110_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct reset_info *info = (struct reset_info *)(id->driver_data);
+ void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
+
+ if (!info || !base)
+ return -ENODEV;
+
+ return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
+ *base + info->assert_offset,
+ *base + info->status_offset,
+ NULL,
+ info->nr_resets,
+ NULL);
+}
+
+static const struct reset_info jh7110_sys_info = {
+ .nr_resets = JH7110_SYSRST_END,
+ .assert_offset = 0x2F8,
+ .status_offset = 0x308,
+};
+
+static const struct reset_info jh7110_aon_info = {
+ .nr_resets = JH7110_AONRST_END,
+ .assert_offset = 0x38,
+ .status_offset = 0x3C,
+};
+
+static const struct auxiliary_device_id jh7110_reset_ids[] = {
+ {
+ .name = "clk_starfive_jh71x0.reset-sys",
+ .driver_data = (kernel_ulong_t)&jh7110_sys_info,
+ },
+ {
+ .name = "clk_starfive_jh71x0.reset-aon",
+ .driver_data = (kernel_ulong_t)&jh7110_aon_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids);
+
+static struct auxiliary_driver jh7110_reset_driver = {
+ .probe = jh7110_reset_probe,
+ .id_table = jh7110_reset_ids,
+};
+module_auxiliary_driver(jh7110_reset_driver);
+
+MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JH7110 reset driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
index db7d39a87f87..e485472e1adc 100644
--- a/drivers/reset/starfive/reset-starfive-jh71x0.h
+++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
@@ -6,6 +6,12 @@
#ifndef __RESET_STARFIVE_JH71X0_H
#define __RESET_STARFIVE_JH71X0_H
+struct reset_info {
+ unsigned int nr_resets;
+ unsigned int assert_offset;
+ unsigned int status_offset;
+};
+
int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
void __iomem *assert, void __iomem *status,
const u32 *asserted, unsigned int nr_resets,
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (12 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
` (7 subsequent siblings)
21 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add compatible string for the StarFive JH7110 clint.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index bbad24165837..a9580191f78b 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -27,6 +27,7 @@ properties:
- enum:
- sifive,fu540-c000-clint
- starfive,jh7100-clint
+ - starfive,jh7110-clint
- canaan,k210-clint
- const: sifive,clint0
- items:
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (13 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
` (6 subsequent siblings)
21 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add compatible string for StarFive JH7110 plic.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 99e01f4d0a69..571700d5cb9e 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -60,6 +60,7 @@ properties:
- enum:
- sifive,fu540-c000-plic
- starfive,jh7100-plic
+ - starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (14 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 11:38 ` Krzysztof Kozlowski
2023-02-21 15:10 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
` (5 subsequent siblings)
21 siblings, 2 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index a2884e3113da..54bfe24a436b 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -35,6 +35,7 @@ properties:
- sifive,e7
- sifive,e71
- sifive,rocket0
+ - sifive,s7
- sifive,u5
- sifive,u54
- sifive,u7
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (15 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 17:03 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
` (4 subsequent siblings)
21 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110.dtsi | 507 +++++++++++++++++++++++
1 file changed, 507 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
new file mode 100644
index 000000000000..5a892b3320e5
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -0,0 +1,507 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+#include <dt-bindings/reset/starfive,jh7110-crg.h>
+
+/ {
+ compatible = "starfive,jh7110";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ S7_0: cpu@0 {
+ compatible = "sifive,s7", "riscv";
+ reg = <0>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <8192>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <16384>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imac_zicsr_zba_zbb";
+ tlb-split;
+ status = "disabled";
+
+ cpu0_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_1: cpu@1 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <1>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc_zicsr_zba_zbb";
+ tlb-split;
+
+ cpu1_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_2: cpu@2 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <2>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc_zicsr_zba_zbb";
+ tlb-split;
+
+ cpu2_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_3: cpu@3 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <3>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc_zicsr_zba_zbb";
+ tlb-split;
+
+ cpu3_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ U74_4: cpu@4 {
+ compatible = "sifive,u74-mc", "riscv";
+ reg = <4>;
+ d-cache-block-size = <64>;
+ d-cache-sets = <64>;
+ d-cache-size = <32768>;
+ d-tlb-sets = <1>;
+ d-tlb-size = <40>;
+ device_type = "cpu";
+ i-cache-block-size = <64>;
+ i-cache-sets = <64>;
+ i-cache-size = <32768>;
+ i-tlb-sets = <1>;
+ i-tlb-size = <40>;
+ mmu-type = "riscv,sv39";
+ next-level-cache = <&ccache>;
+ riscv,isa = "rv64imafdc_zicsr_zba_zbb";
+ tlb-split;
+
+ cpu4_intc: interrupt-controller {
+ compatible = "riscv,cpu-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&S7_0>;
+ };
+
+ core1 {
+ cpu = <&U74_1>;
+ };
+
+ core2 {
+ cpu = <&U74_2>;
+ };
+
+ core3 {
+ cpu = <&U74_3>;
+ };
+
+ core4 {
+ cpu = <&U74_4>;
+ };
+ };
+ };
+ };
+
+ osc: oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "osc";
+ #clock-cells = <0>;
+ };
+
+ rtc_osc: rtc-oscillator {
+ compatible = "fixed-clock";
+ clock-output-names = "rtc_osc";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rmii_refin: gmac0-rmii-refin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac0_rmii_refin";
+ #clock-cells = <0>;
+ };
+
+ gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac0_rgmii_rxin";
+ #clock-cells = <0>;
+ };
+
+ gmac1_rmii_refin: gmac1-rmii-refin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac1_rmii_refin";
+ #clock-cells = <0>;
+ };
+
+ gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "gmac1_rgmii_rxin";
+ #clock-cells = <0>;
+ };
+
+ i2stx_bclk_ext: i2stx-bclk-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "i2stx_bclk_ext";
+ #clock-cells = <0>;
+ };
+
+ i2stx_lrck_ext: i2stx-lrck-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "i2stx_lrck_ext";
+ #clock-cells = <0>;
+ };
+
+ i2srx_bclk_ext: i2srx-bclk-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "i2srx_bclk_ext";
+ #clock-cells = <0>;
+ };
+
+ i2srx_lrck_ext: i2srx-lrck-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "i2srx_lrck_ext";
+ #clock-cells = <0>;
+ };
+
+ tdm_ext: tdm-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "tdm_ext";
+ #clock-cells = <0>;
+ };
+
+ mclk_ext: mclk-ext-clock {
+ compatible = "fixed-clock";
+ clock-output-names = "mclk_ext";
+ #clock-cells = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&plic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clint: timer@2000000 {
+ compatible = "starfive,jh7110-clint", "sifive,clint0";
+ reg = <0x0 0x2000000 0x0 0x10000>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
+ };
+
+ plic: interrupt-controller@c000000 {
+ compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
+ reg = <0x0 0xc000000 0x0 0x4000000>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ riscv,ndev = <136>;
+ };
+
+ ccache: cache-controller@2010000 {
+ compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
+ reg = <0x0 0x2010000 0x0 0x4000>;
+ interrupts = <1>, <3>, <4>, <2>;
+ cache-block-size = <64>;
+ cache-level = <2>;
+ cache-sets = <2048>;
+ cache-size = <2097152>;
+ cache-unified;
+ };
+
+ uart0: serial@10000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
+ <&syscrg JH7110_SYSCLK_UART0_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART0_APB>;
+ interrupts = <32>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@10010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
+ <&syscrg JH7110_SYSCLK_UART1_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART1_APB>;
+ interrupts = <33>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart2: serial@10020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x10020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
+ <&syscrg JH7110_SYSCLK_UART2_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART2_APB>;
+ interrupts = <34>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@10030000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x10030000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
+ interrupts = <35>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10040000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x10040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
+ interrupts = <36>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10050000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x10050000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
+ interrupts = <37>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart3: serial@12000000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12000000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
+ <&syscrg JH7110_SYSCLK_UART3_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART3_APB>;
+ interrupts = <45>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart4: serial@12010000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12010000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
+ <&syscrg JH7110_SYSCLK_UART4_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART4_APB>;
+ interrupts = <46>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ uart5: serial@12020000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x0 0x12020000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
+ <&syscrg JH7110_SYSCLK_UART5_APB>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&syscrg JH7110_SYSRST_UART5_APB>;
+ interrupts = <47>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@12030000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12030000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
+ interrupts = <48>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@12040000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
+ interrupts = <49>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@12050000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12050000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
+ interrupts = <50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@12060000 {
+ compatible = "snps,designware-i2c";
+ reg = <0x0 0x12060000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
+ clock-names = "ref";
+ resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
+ interrupts = <51>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ syscrg: clock-controller@13020000 {
+ compatible = "starfive,jh7110-syscrg";
+ reg = <0x0 0x13020000 0x0 0x10000>;
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sysgpio: pinctrl@13040000 {
+ compatible = "starfive,jh7110-sys-pinctrl";
+ reg = <0x0 0x13040000 0x0 0x10000>;
+ clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
+ resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
+ interrupts = <86>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ aoncrg: clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ reg = <0x0 0x17000000 0x0 0x10000>;
+ clocks = <&osc>, <&rtc_osc>,
+ <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
+ clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
+ "gmac0_rgmii_rxin", "stg_axiahb",
+ "apb_bus", "gmac0_gtxclk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ aongpio: pinctrl@17020000 {
+ compatible = "starfive,jh7110-aon-pinctrl";
+ reg = <0x0 0x17020000 0x0 0x10000>;
+ resets = <&aoncrg JH7110_AONRST_IOMUX>;
+ interrupts = <85>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+};
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (16 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
` (3 subsequent siblings)
21 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Jianlong Huang <jianlong.huang@starfivetech.com>
Add pin function definitions for StarFive JH7110 SoC.
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++++++++++++++
1 file changed, 308 insertions(+)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
diff --git a/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
new file mode 100644
index 000000000000..fb0139b56723
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#ifndef __JH7110_PINFUNC_H__
+#define __JH7110_PINFUNC_H__
+
+/*
+ * mux bits:
+ * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 |
+ * | din | dout | doen | function | gpio nr |
+ *
+ * dout: output signal
+ * doen: output enable signal
+ * din: optional input signal, 0xff = none
+ * function: function selector
+ * gpio nr: gpio number, 0 - 63
+ */
+#define GPIOMUX(n, dout, doen, din) ( \
+ (((din) & 0xff) << 24) | \
+ (((dout) & 0xff) << 16) | \
+ (((doen) & 0x3f) << 10) | \
+ ((n) & 0x3f))
+
+#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff))
+
+/* sys_iomux dout */
+#define GPOUT_LOW 0
+#define GPOUT_HIGH 1
+#define GPOUT_SYS_WAVE511_UART_TX 2
+#define GPOUT_SYS_CAN0_STBY 3
+#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4
+#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5
+#define GPOUT_SYS_CAN0_TXD 6
+#define GPOUT_SYS_USB_DRIVE_VBUS 7
+#define GPOUT_SYS_QSPI_CS1 8
+#define GPOUT_SYS_SPDIF 9
+#define GPOUT_SYS_HDMI_CEC_SDA 10
+#define GPOUT_SYS_HDMI_DDC_SCL 11
+#define GPOUT_SYS_HDMI_DDC_SDA 12
+#define GPOUT_SYS_WATCHDOG 13
+#define GPOUT_SYS_I2C0_CLK 14
+#define GPOUT_SYS_I2C0_DATA 15
+#define GPOUT_SYS_SDIO0_BACK_END_POWER 16
+#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17
+#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18
+#define GPOUT_SYS_SDIO0_RST 19
+#define GPOUT_SYS_UART0_TX 20
+#define GPOUT_SYS_HIFI4_JTAG_TDO 21
+#define GPOUT_SYS_JTAG_TDO 22
+#define GPOUT_SYS_PDM_MCLK 23
+#define GPOUT_SYS_PWM_CHANNEL0 24
+#define GPOUT_SYS_PWM_CHANNEL1 25
+#define GPOUT_SYS_PWM_CHANNEL2 26
+#define GPOUT_SYS_PWM_CHANNEL3 27
+#define GPOUT_SYS_PWMDAC_LEFT 28
+#define GPOUT_SYS_PWMDAC_RIGHT 29
+#define GPOUT_SYS_SPI0_CLK 30
+#define GPOUT_SYS_SPI0_FSS 31
+#define GPOUT_SYS_SPI0_TXD 32
+#define GPOUT_SYS_GMAC_PHYCLK 33
+#define GPOUT_SYS_I2SRX_BCLK 34
+#define GPOUT_SYS_I2SRX_LRCK 35
+#define GPOUT_SYS_I2STX0_BCLK 36
+#define GPOUT_SYS_I2STX0_LRCK 37
+#define GPOUT_SYS_MCLK 38
+#define GPOUT_SYS_TDM_CLK 39
+#define GPOUT_SYS_TDM_SYNC 40
+#define GPOUT_SYS_TDM_TXD 41
+#define GPOUT_SYS_TRACE_DATA0 42
+#define GPOUT_SYS_TRACE_DATA1 43
+#define GPOUT_SYS_TRACE_DATA2 44
+#define GPOUT_SYS_TRACE_DATA3 45
+#define GPOUT_SYS_TRACE_REF 46
+#define GPOUT_SYS_CAN1_STBY 47
+#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48
+#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49
+#define GPOUT_SYS_CAN1_TXD 50
+#define GPOUT_SYS_I2C1_CLK 51
+#define GPOUT_SYS_I2C1_DATA 52
+#define GPOUT_SYS_SDIO1_BACK_END_POWER 53
+#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54
+#define GPOUT_SYS_SDIO1_CLK 55
+#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56
+#define GPOUT_SYS_SDIO1_CMD 57
+#define GPOUT_SYS_SDIO1_DATA0 58
+#define GPOUT_SYS_SDIO1_DATA1 59
+#define GPOUT_SYS_SDIO1_DATA2 60
+#define GPOUT_SYS_SDIO1_DATA3 61
+#define GPOUT_SYS_SDIO1_DATA4 63
+#define GPOUT_SYS_SDIO1_DATA5 63
+#define GPOUT_SYS_SDIO1_DATA6 64
+#define GPOUT_SYS_SDIO1_DATA7 65
+#define GPOUT_SYS_SDIO1_RST 66
+#define GPOUT_SYS_UART1_RTS 67
+#define GPOUT_SYS_UART1_TX 68
+#define GPOUT_SYS_I2STX1_SDO0 69
+#define GPOUT_SYS_I2STX1_SDO1 70
+#define GPOUT_SYS_I2STX1_SDO2 71
+#define GPOUT_SYS_I2STX1_SDO3 72
+#define GPOUT_SYS_SPI1_CLK 73
+#define GPOUT_SYS_SPI1_FSS 74
+#define GPOUT_SYS_SPI1_TXD 75
+#define GPOUT_SYS_I2C2_CLK 76
+#define GPOUT_SYS_I2C2_DATA 77
+#define GPOUT_SYS_UART2_RTS 78
+#define GPOUT_SYS_UART2_TX 79
+#define GPOUT_SYS_SPI2_CLK 80
+#define GPOUT_SYS_SPI2_FSS 81
+#define GPOUT_SYS_SPI2_TXD 82
+#define GPOUT_SYS_I2C3_CLK 83
+#define GPOUT_SYS_I2C3_DATA 84
+#define GPOUT_SYS_UART3_TX 85
+#define GPOUT_SYS_SPI3_CLK 86
+#define GPOUT_SYS_SPI3_FSS 87
+#define GPOUT_SYS_SPI3_TXD 88
+#define GPOUT_SYS_I2C4_CLK 89
+#define GPOUT_SYS_I2C4_DATA 90
+#define GPOUT_SYS_UART4_RTS 91
+#define GPOUT_SYS_UART4_TX 92
+#define GPOUT_SYS_SPI4_CLK 93
+#define GPOUT_SYS_SPI4_FSS 94
+#define GPOUT_SYS_SPI4_TXD 95
+#define GPOUT_SYS_I2C5_CLK 96
+#define GPOUT_SYS_I2C5_DATA 97
+#define GPOUT_SYS_UART5_RTS 98
+#define GPOUT_SYS_UART5_TX 99
+#define GPOUT_SYS_SPI5_CLK 100
+#define GPOUT_SYS_SPI5_FSS 101
+#define GPOUT_SYS_SPI5_TXD 102
+#define GPOUT_SYS_I2C6_CLK 103
+#define GPOUT_SYS_I2C6_DATA 104
+#define GPOUT_SYS_SPI6_CLK 105
+#define GPOUT_SYS_SPI6_FSS 106
+#define GPOUT_SYS_SPI6_TXD 107
+
+/* aon_iomux dout */
+#define GPOUT_AON_CLK_32K_OUT 2
+#define GPOUT_AON_PTC0_PWM4 3
+#define GPOUT_AON_PTC0_PWM5 4
+#define GPOUT_AON_PTC0_PWM6 5
+#define GPOUT_AON_PTC0_PWM7 6
+#define GPOUT_AON_CLK_GCLK0 7
+#define GPOUT_AON_CLK_GCLK1 8
+#define GPOUT_AON_CLK_GCLK2 9
+
+/* sys_iomux doen */
+#define GPOEN_ENABLE 0
+#define GPOEN_DISABLE 1
+#define GPOEN_SYS_HDMI_CEC_SDA 2
+#define GPOEN_SYS_HDMI_DDC_SCL 3
+#define GPOEN_SYS_HDMI_DDC_SDA 4
+#define GPOEN_SYS_I2C0_CLK 5
+#define GPOEN_SYS_I2C0_DATA 6
+#define GPOEN_SYS_HIFI4_JTAG_TDO 7
+#define GPOEN_SYS_JTAG_TDO 8
+#define GPOEN_SYS_PWM0_CHANNEL0 9
+#define GPOEN_SYS_PWM0_CHANNEL1 10
+#define GPOEN_SYS_PWM0_CHANNEL2 11
+#define GPOEN_SYS_PWM0_CHANNEL3 12
+#define GPOEN_SYS_SPI0_NSSPCTL 13
+#define GPOEN_SYS_SPI0_NSSP 14
+#define GPOEN_SYS_TDM_SYNC 15
+#define GPOEN_SYS_TDM_TXD 16
+#define GPOEN_SYS_I2C1_CLK 17
+#define GPOEN_SYS_I2C1_DATA 18
+#define GPOEN_SYS_SDIO1_CMD 19
+#define GPOEN_SYS_SDIO1_DATA0 20
+#define GPOEN_SYS_SDIO1_DATA1 21
+#define GPOEN_SYS_SDIO1_DATA2 22
+#define GPOEN_SYS_SDIO1_DATA3 23
+#define GPOEN_SYS_SDIO1_DATA4 24
+#define GPOEN_SYS_SDIO1_DATA5 25
+#define GPOEN_SYS_SDIO1_DATA6 26
+#define GPOEN_SYS_SDIO1_DATA7 27
+#define GPOEN_SYS_SPI1_NSSPCTL 28
+#define GPOEN_SYS_SPI1_NSSP 29
+#define GPOEN_SYS_I2C2_CLK 30
+#define GPOEN_SYS_I2C2_DATA 31
+#define GPOEN_SYS_SPI2_NSSPCTL 32
+#define GPOEN_SYS_SPI2_NSSP 33
+#define GPOEN_SYS_I2C3_CLK 34
+#define GPOEN_SYS_I2C3_DATA 35
+#define GPOEN_SYS_SPI3_NSSPCTL 36
+#define GPOEN_SYS_SPI3_NSSP 37
+#define GPOEN_SYS_I2C4_CLK 38
+#define GPOEN_SYS_I2C4_DATA 39
+#define GPOEN_SYS_SPI4_NSSPCTL 40
+#define GPOEN_SYS_SPI4_NSSP 41
+#define GPOEN_SYS_I2C5_CLK 42
+#define GPOEN_SYS_I2C5_DATA 43
+#define GPOEN_SYS_SPI5_NSSPCTL 44
+#define GPOEN_SYS_SPI5_NSSP 45
+#define GPOEN_SYS_I2C6_CLK 46
+#define GPOEN_SYS_I2C6_DATA 47
+#define GPOEN_SYS_SPI6_NSSPCTL 48
+#define GPOEN_SYS_SPI6_NSSP 49
+
+/* aon_iomux doen */
+#define GPOEN_AON_PTC0_OE_N_4 2
+#define GPOEN_AON_PTC0_OE_N_5 3
+#define GPOEN_AON_PTC0_OE_N_6 4
+#define GPOEN_AON_PTC0_OE_N_7 5
+
+/* sys_iomux gin */
+#define GPI_NONE 255
+
+#define GPI_SYS_WAVE511_UART_RX 0
+#define GPI_SYS_CAN0_RXD 1
+#define GPI_SYS_USB_OVERCURRENT 2
+#define GPI_SYS_SPDIF 3
+#define GPI_SYS_JTAG_RST 4
+#define GPI_SYS_HDMI_CEC_SDA 5
+#define GPI_SYS_HDMI_DDC_SCL 6
+#define GPI_SYS_HDMI_DDC_SDA 7
+#define GPI_SYS_HDMI_HPD 8
+#define GPI_SYS_I2C0_CLK 9
+#define GPI_SYS_I2C0_DATA 10
+#define GPI_SYS_SDIO0_CD 11
+#define GPI_SYS_SDIO0_INT 12
+#define GPI_SYS_SDIO0_WP 13
+#define GPI_SYS_UART0_RX 14
+#define GPI_SYS_HIFI4_JTAG_TCK 15
+#define GPI_SYS_HIFI4_JTAG_TDI 16
+#define GPI_SYS_HIFI4_JTAG_TMS 17
+#define GPI_SYS_HIFI4_JTAG_RST 18
+#define GPI_SYS_JTAG_TDI 19
+#define GPI_SYS_JTAG_TMS 20
+#define GPI_SYS_PDM_DMIC0 21
+#define GPI_SYS_PDM_DMIC1 22
+#define GPI_SYS_I2SRX_SDIN0 23
+#define GPI_SYS_I2SRX_SDIN1 24
+#define GPI_SYS_I2SRX_SDIN2 25
+#define GPI_SYS_SPI0_CLK 26
+#define GPI_SYS_SPI0_FSS 27
+#define GPI_SYS_SPI0_RXD 28
+#define GPI_SYS_JTAG_TCK 29
+#define GPI_SYS_MCLK_EXT 30
+#define GPI_SYS_I2SRX_BCLK 31
+#define GPI_SYS_I2SRX_LRCK 32
+#define GPI_SYS_I2STX0_BCLK 33
+#define GPI_SYS_I2STX0_LRCK 34
+#define GPI_SYS_TDM_CLK 35
+#define GPI_SYS_TDM_RXD 36
+#define GPI_SYS_TDM_SYNC 37
+#define GPI_SYS_CAN1_RXD 38
+#define GPI_SYS_I2C1_CLK 39
+#define GPI_SYS_I2C1_DATA 40
+#define GPI_SYS_SDIO1_CD 41
+#define GPI_SYS_SDIO1_INT 42
+#define GPI_SYS_SDIO1_WP 43
+#define GPI_SYS_SDIO1_CMD 44
+#define GPI_SYS_SDIO1_DATA0 45
+#define GPI_SYS_SDIO1_DATA1 46
+#define GPI_SYS_SDIO1_DATA2 47
+#define GPI_SYS_SDIO1_DATA3 48
+#define GPI_SYS_SDIO1_DATA4 49
+#define GPI_SYS_SDIO1_DATA5 50
+#define GPI_SYS_SDIO1_DATA6 51
+#define GPI_SYS_SDIO1_DATA7 52
+#define GPI_SYS_SDIO1_STRB 53
+#define GPI_SYS_UART1_CTS 54
+#define GPI_SYS_UART1_RX 55
+#define GPI_SYS_SPI1_CLK 56
+#define GPI_SYS_SPI1_FSS 57
+#define GPI_SYS_SPI1_RXD 58
+#define GPI_SYS_I2C2_CLK 59
+#define GPI_SYS_I2C2_DATA 60
+#define GPI_SYS_UART2_CTS 61
+#define GPI_SYS_UART2_RX 62
+#define GPI_SYS_SPI2_CLK 63
+#define GPI_SYS_SPI2_FSS 64
+#define GPI_SYS_SPI2_RXD 65
+#define GPI_SYS_I2C3_CLK 66
+#define GPI_SYS_I2C3_DATA 67
+#define GPI_SYS_UART3_RX 68
+#define GPI_SYS_SPI3_CLK 69
+#define GPI_SYS_SPI3_FSS 70
+#define GPI_SYS_SPI3_RXD 71
+#define GPI_SYS_I2C4_CLK 72
+#define GPI_SYS_I2C4_DATA 73
+#define GPI_SYS_UART4_CTS 74
+#define GPI_SYS_UART4_RX 75
+#define GPI_SYS_SPI4_CLK 76
+#define GPI_SYS_SPI4_FSS 77
+#define GPI_SYS_SPI4_RXD 78
+#define GPI_SYS_I2C5_CLK 79
+#define GPI_SYS_I2C5_DATA 80
+#define GPI_SYS_UART5_CTS 81
+#define GPI_SYS_UART5_RX 82
+#define GPI_SYS_SPI5_CLK 83
+#define GPI_SYS_SPI5_FSS 84
+#define GPI_SYS_SPI5_RXD 85
+#define GPI_SYS_I2C6_CLK 86
+#define GPI_SYS_I2C6_DATA 87
+#define GPI_SYS_SPI6_CLK 88
+#define GPI_SYS_SPI6_FSS 89
+#define GPI_SYS_SPI6_RXD 90
+
+/* aon_iomux gin */
+#define GPI_AON_PMU_GPIO_WAKEUP_0 0
+#define GPI_AON_PMU_GPIO_WAKEUP_1 1
+#define GPI_AON_PMU_GPIO_WAKEUP_2 2
+#define GPI_AON_PMU_GPIO_WAKEUP_3 3
+
+#endif
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (17 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
@ 2023-02-21 2:46 ` Hal Feng
2023-02-21 15:03 ` Emil Renner Berthing
2023-02-22 15:00 ` [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC patchwork-bot+linux-riscv
` (2 subsequent siblings)
21 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-21 2:46 UTC (permalink / raw)
To: linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, Hal Feng, linux-kernel
From: Emil Renner Berthing <kernel@esmil.dk>
Add a minimal device tree for StarFive JH7110 VisionFive 2 board
which has version A and version B. Support booting and basic
clock/reset/pinctrl/uart drivers.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
---
arch/riscv/boot/dts/starfive/Makefile | 6 +-
.../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
.../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
.../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
4 files changed, 246 insertions(+), 1 deletion(-)
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
index 039c143cba33..cd73519b907b 100644
--- a/arch/riscv/boot/dts/starfive/Makefile
+++ b/arch/riscv/boot/dts/starfive/Makefile
@@ -1,2 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
+
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
+dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
new file mode 100644
index 000000000000..4af3300f3cf3
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.2A";
+ compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
new file mode 100644
index 000000000000..9230cc3d8946
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110-starfive-visionfive-2.dtsi"
+
+/ {
+ model = "StarFive VisionFive 2 v1.3B";
+ compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
new file mode 100644
index 000000000000..c2aa8946a0f1
--- /dev/null
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
+ */
+
+/dts-v1/;
+#include "jh7110.dtsi"
+#include "jh7110-pinfunc.h"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ timebase-frequency = <4000000>;
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0x0 0x40000000 0x1 0x0>;
+ };
+
+ gpio-restart {
+ compatible = "gpio-restart";
+ gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
+ priority = <224>;
+ };
+};
+
+&osc {
+ clock-frequency = <24000000>;
+};
+
+&rtc_osc {
+ clock-frequency = <32768>;
+};
+
+&gmac0_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac0_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&gmac1_rmii_refin {
+ clock-frequency = <50000000>;
+};
+
+&gmac1_rgmii_rxin {
+ clock-frequency = <125000000>;
+};
+
+&i2stx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2stx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&i2srx_bclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&i2srx_lrck_ext {
+ clock-frequency = <192000>;
+};
+
+&tdm_ext {
+ clock-frequency = <49152000>;
+};
+
+&mclk_ext {
+ clock-frequency = <12288000>;
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&i2c0 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+ status = "okay";
+};
+
+&i2c5 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5_pins>;
+ status = "okay";
+};
+
+&i2c6 {
+ clock-frequency = <100000>;
+ i2c-sda-hold-time-ns = <300>;
+ i2c-sda-falling-time-ns = <510>;
+ i2c-scl-falling-time-ns = <510>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pins>;
+ status = "okay";
+};
+
+&sysgpio {
+ uart0_pins: uart0-0 {
+ tx-pins {
+ pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
+ GPOEN_ENABLE,
+ GPI_NONE)>;
+ bias-disable;
+ drive-strength = <12>;
+ input-disable;
+ input-schmitt-disable;
+ slew-rate = <0>;
+ };
+
+ rx-pins {
+ pinmux = <GPIOMUX(6, GPOUT_LOW,
+ GPOEN_DISABLE,
+ GPI_SYS_UART0_RX)>;
+ bias-disable; /* external pull-up */
+ drive-strength = <2>;
+ input-enable;
+ input-schmitt-enable;
+ slew-rate = <0>;
+ };
+ };
+
+ i2c0_pins: i2c0-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(57, GPOUT_LOW,
+ GPOEN_SYS_I2C0_CLK,
+ GPI_SYS_I2C0_CLK)>,
+ <GPIOMUX(58, GPOUT_LOW,
+ GPOEN_SYS_I2C0_DATA,
+ GPI_SYS_I2C0_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c2_pins: i2c2-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(3, GPOUT_LOW,
+ GPOEN_SYS_I2C2_CLK,
+ GPI_SYS_I2C2_CLK)>,
+ <GPIOMUX(2, GPOUT_LOW,
+ GPOEN_SYS_I2C2_DATA,
+ GPI_SYS_I2C2_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c5_pins: i2c5-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(19, GPOUT_LOW,
+ GPOEN_SYS_I2C5_CLK,
+ GPI_SYS_I2C5_CLK)>,
+ <GPIOMUX(20, GPOUT_LOW,
+ GPOEN_SYS_I2C5_DATA,
+ GPI_SYS_I2C5_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+
+ i2c6_pins: i2c6-0 {
+ i2c-pins {
+ pinmux = <GPIOMUX(16, GPOUT_LOW,
+ GPOEN_SYS_I2C6_CLK,
+ GPI_SYS_I2C6_CLK)>,
+ <GPIOMUX(17, GPOUT_LOW,
+ GPOEN_SYS_I2C6_DATA,
+ GPI_SYS_I2C6_DATA)>;
+ bias-disable; /* external pull-up */
+ input-enable;
+ input-schmitt-enable;
+ };
+ };
+};
--
2.38.1
^ permalink raw reply related [flat|nested] 71+ messages in thread
* Re: [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible
2023-02-21 2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
@ 2023-02-21 11:38 ` Krzysztof Kozlowski
2023-02-21 15:10 ` Conor Dooley
1 sibling, 0 replies; 71+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-21 11:38 UTC (permalink / raw)
To: Hal Feng, linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
On 21/02/2023 03:46, Hal Feng wrote:
> Add a new compatible string in cpu.yaml for SiFive S7 CPU
> core which is used on SiFive U74-MC core complex etc.
>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-21 2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
@ 2023-02-21 15:03 ` Emil Renner Berthing
2023-02-23 8:50 ` Hal Feng
0 siblings, 1 reply; 71+ messages in thread
From: Emil Renner Berthing @ 2023-02-21 15:03 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> which has version A and version B. Support booting and basic
> clock/reset/pinctrl/uart drivers.
>
> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/Makefile | 6 +-
> .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
> .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
> .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
> 4 files changed, 246 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>
> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> index 039c143cba33..cd73519b907b 100644
> --- a/arch/riscv/boot/dts/starfive/Makefile
> +++ b/arch/riscv/boot/dts/starfive/Makefile
> @@ -1,2 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
> +
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
> new file mode 100644
> index 000000000000..4af3300f3cf3
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-starfive-visionfive-2.dtsi"
> +
> +/ {
> + model = "StarFive VisionFive 2 v1.2A";
> + compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
> new file mode 100644
> index 000000000000..9230cc3d8946
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
> @@ -0,0 +1,13 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110-starfive-visionfive-2.dtsi"
> +
> +/ {
> + model = "StarFive VisionFive 2 v1.3B";
> + compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
> +};
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> new file mode 100644
> index 000000000000..c2aa8946a0f1
> --- /dev/null
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -0,0 +1,215 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + */
> +
> +/dts-v1/;
> +#include "jh7110.dtsi"
> +#include "jh7110-pinfunc.h"
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + aliases {
> + serial0 = &uart0;
> + i2c0 = &i2c0;
> + i2c2 = &i2c2;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
Let's keep these sorted alphabetically.
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + cpus {
> + timebase-frequency = <4000000>;
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x0 0x40000000 0x1 0x0>;
> + };
> +
> + gpio-restart {
> + compatible = "gpio-restart";
> + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
> + priority = <224>;
> + };
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&rtc_osc {
> + clock-frequency = <32768>;
> +};
> +
> +&gmac0_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac0_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&gmac1_rmii_refin {
> + clock-frequency = <50000000>;
> +};
> +
> +&gmac1_rgmii_rxin {
> + clock-frequency = <125000000>;
> +};
> +
> +&i2stx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2stx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&i2srx_bclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&i2srx_lrck_ext {
> + clock-frequency = <192000>;
> +};
> +
> +&tdm_ext {
> + clock-frequency = <49152000>;
> +};
> +
> +&mclk_ext {
> + clock-frequency = <12288000>;
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + i2c-sda-hold-time-ns = <300>;
> + i2c-sda-falling-time-ns = <510>;
> + i2c-scl-falling-time-ns = <510>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "okay";
> +};
> +
> +&i2c2 {
> + clock-frequency = <100000>;
> + i2c-sda-hold-time-ns = <300>;
> + i2c-sda-falling-time-ns = <510>;
> + i2c-scl-falling-time-ns = <510>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c2_pins>;
> + status = "okay";
> +};
> +
> +&i2c5 {
> + clock-frequency = <100000>;
> + i2c-sda-hold-time-ns = <300>;
> + i2c-sda-falling-time-ns = <510>;
> + i2c-scl-falling-time-ns = <510>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c5_pins>;
> + status = "okay";
> +};
> +
> +&i2c6 {
> + clock-frequency = <100000>;
> + i2c-sda-hold-time-ns = <300>;
> + i2c-sda-falling-time-ns = <510>;
> + i2c-scl-falling-time-ns = <510>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c6_pins>;
> + status = "okay";
> +};
> +
> +&sysgpio {
> + uart0_pins: uart0-0 {
> + tx-pins {
> + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
> + GPOEN_ENABLE,
> + GPI_NONE)>;
> + bias-disable;
> + drive-strength = <12>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> +
> + rx-pins {
> + pinmux = <GPIOMUX(6, GPOUT_LOW,
> + GPOEN_DISABLE,
> + GPI_SYS_UART0_RX)>;
> + bias-disable; /* external pull-up */
> + drive-strength = <2>;
> + input-enable;
> + input-schmitt-enable;
> + slew-rate = <0>;
> + };
> + };
> +
> + i2c0_pins: i2c0-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(57, GPOUT_LOW,
> + GPOEN_SYS_I2C0_CLK,
> + GPI_SYS_I2C0_CLK)>,
> + <GPIOMUX(58, GPOUT_LOW,
> + GPOEN_SYS_I2C0_DATA,
> + GPI_SYS_I2C0_DATA)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +
> + i2c2_pins: i2c2-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(3, GPOUT_LOW,
> + GPOEN_SYS_I2C2_CLK,
> + GPI_SYS_I2C2_CLK)>,
> + <GPIOMUX(2, GPOUT_LOW,
> + GPOEN_SYS_I2C2_DATA,
> + GPI_SYS_I2C2_DATA)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +
> + i2c5_pins: i2c5-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(19, GPOUT_LOW,
> + GPOEN_SYS_I2C5_CLK,
> + GPI_SYS_I2C5_CLK)>,
> + <GPIOMUX(20, GPOUT_LOW,
> + GPOEN_SYS_I2C5_DATA,
> + GPI_SYS_I2C5_DATA)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +
> + i2c6_pins: i2c6-0 {
> + i2c-pins {
> + pinmux = <GPIOMUX(16, GPOUT_LOW,
> + GPOEN_SYS_I2C6_CLK,
> + GPI_SYS_I2C6_CLK)>,
> + <GPIOMUX(17, GPOUT_LOW,
> + GPOEN_SYS_I2C6_DATA,
> + GPI_SYS_I2C6_DATA)>;
> + bias-disable; /* external pull-up */
> + input-enable;
> + input-schmitt-enable;
> + };
> + };
> +};
It would be great to have some sort of order to this file so it's
obvious where to add new nodes. I suggest we do
- root node
- external clocks
- other node references in alphabetical order
You're almost there with this patch except the uart0 node is out of place.
/Emil
> 2.38.1
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible
2023-02-21 2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-02-21 11:38 ` Krzysztof Kozlowski
@ 2023-02-21 15:10 ` Conor Dooley
1 sibling, 0 replies; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 15:10 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
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On Tue, Feb 21, 2023 at 10:46:42AM +0800, Hal Feng wrote:
> Add a new compatible string in cpu.yaml for SiFive S7 CPU
> core which is used on SiFive U74-MC core complex etc.
>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index a2884e3113da..54bfe24a436b 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -35,6 +35,7 @@ properties:
> - sifive,e7
> - sifive,e71
> - sifive,rocket0
> + - sifive,s7
> - sifive,u5
> - sifive,u54
> - sifive,u7
> --
> 2.38.1
>
>
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver
2023-02-21 2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
@ 2023-02-21 15:12 ` Conor Dooley
2023-02-23 6:17 ` Hal Feng
2023-02-26 16:07 ` Emil Renner Berthing
1 sibling, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 15:12 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
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On Tue, Feb 21, 2023 at 10:46:37AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add driver for the StarFive JH7110 system clock controller and
> register an auxiliary device for system reset controller which
> is named as "reset-sys".
>
> Reported-by: kernel test robot <lkp@intel.com>
How is this Reported-by lkp?
If lkp responded to your patch saying there was a problem with it, it
doesn't get a Reported-by - just like how any other reviewer doesn't get
a Reported-by for pointing out build issues ;)
You only need to add that for bugs it reports on patches that have
already been applied ;)
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver
2023-02-21 2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
@ 2023-02-21 15:33 ` Emil Renner Berthing
2023-02-21 16:34 ` Conor Dooley
2023-02-23 6:29 ` Hal Feng
0 siblings, 2 replies; 71+ messages in thread
From: Emil Renner Berthing @ 2023-02-21 15:33 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> Add auxiliary driver to support StarFive JH7110 system
> and always-on resets.
>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> drivers/reset/starfive/Kconfig | 8 +++
> drivers/reset/starfive/Makefile | 1 +
> .../reset/starfive/reset-starfive-jh7110.c | 64 +++++++++++++++++++
> .../reset/starfive/reset-starfive-jh71x0.h | 6 ++
> 4 files changed, 79 insertions(+)
> create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
>
> diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
> index 9d15c4110e40..fab1a081af17 100644
> --- a/drivers/reset/starfive/Kconfig
> +++ b/drivers/reset/starfive/Kconfig
> @@ -10,3 +10,11 @@ config RESET_STARFIVE_JH7100
> default SOC_STARFIVE
> help
> This enables the reset controller driver for the StarFive JH7100 SoC.
> +
> +config RESET_STARFIVE_JH7110
> + bool "StarFive JH7110 Reset Driver"
> + depends on AUXILIARY_BUS && CLK_STARFIVE_JH7110_SYS
> + select RESET_STARFIVE_JH71X0
> + default CLK_STARFIVE_JH7110_SYS
> + help
> + This enables the reset controller driver for the StarFive JH7110 SoC.
> diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
> index f6aa12466fad..7a44b66fb9d5 100644
> --- a/drivers/reset/starfive/Makefile
> +++ b/drivers/reset/starfive/Makefile
> @@ -2,3 +2,4 @@
> obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
>
> obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
> +obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
> diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
> new file mode 100644
> index 000000000000..83577d1b7fc6
> --- /dev/null
> +++ b/drivers/reset/starfive/reset-starfive-jh7110.c
> @@ -0,0 +1,64 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Reset driver for the StarFive JH7110 SoC
> + *
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/auxiliary_bus.h>
> +
> +#include "reset-starfive-jh71x0.h"
> +
> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> +static int jh7110_reset_probe(struct auxiliary_device *adev,
> + const struct auxiliary_device_id *id)
> +{
> + struct reset_info *info = (struct reset_info *)(id->driver_data);
> + void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
Hi Hal,
I saw the kernel test robot complain about this, but I still wonder if
the extra level of indirection is really needed. Isn't it enough to
just add the explicit casts, so
dev_set_drvdata(priv->dev, (void *)priv->base);
in the clock drivers and here just
void __iomem *base = (void __iomem *)dev_get_drvdata(adev->dev.parent);
> +
> + if (!info || !base)
> + return -ENODEV;
> +
> + return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
> + *base + info->assert_offset,
> + *base + info->status_offset,
> + NULL,
> + info->nr_resets,
> + NULL);
> +}
> +
> +static const struct reset_info jh7110_sys_info = {
> + .nr_resets = JH7110_SYSRST_END,
> + .assert_offset = 0x2F8,
> + .status_offset = 0x308,
> +};
> +
> +static const struct reset_info jh7110_aon_info = {
> + .nr_resets = JH7110_AONRST_END,
> + .assert_offset = 0x38,
> + .status_offset = 0x3C,
> +};
> +
> +static const struct auxiliary_device_id jh7110_reset_ids[] = {
> + {
> + .name = "clk_starfive_jh71x0.reset-sys",
> + .driver_data = (kernel_ulong_t)&jh7110_sys_info,
> + },
> + {
> + .name = "clk_starfive_jh71x0.reset-aon",
> + .driver_data = (kernel_ulong_t)&jh7110_aon_info,
> + },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(auxiliary, jh7110_reset_ids);
> +
> +static struct auxiliary_driver jh7110_reset_driver = {
> + .probe = jh7110_reset_probe,
> + .id_table = jh7110_reset_ids,
> +};
> +module_auxiliary_driver(jh7110_reset_driver);
> +
> +MODULE_AUTHOR("Hal Feng <hal.feng@starfivetech.com>");
> +MODULE_DESCRIPTION("StarFive JH7110 reset driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
> index db7d39a87f87..e485472e1adc 100644
> --- a/drivers/reset/starfive/reset-starfive-jh71x0.h
> +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
> @@ -6,6 +6,12 @@
> #ifndef __RESET_STARFIVE_JH71X0_H
> #define __RESET_STARFIVE_JH71X0_H
>
> +struct reset_info {
> + unsigned int nr_resets;
> + unsigned int assert_offset;
> + unsigned int status_offset;
> +};
As far as I can tell this struct isn't used anywhere but in
reset-starfive-jh7110.c. If so just move it there, and in any case
please call it something less generic like struct jh7110_reset_info.
> +
> int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
> void __iomem *assert, void __iomem *status,
> const u32 *asserted, unsigned int nr_resets,
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver
2023-02-21 15:33 ` Emil Renner Berthing
@ 2023-02-21 16:34 ` Conor Dooley
2023-02-23 6:48 ` Hal Feng
2023-02-23 6:29 ` Hal Feng
1 sibling, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 16:34 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: Hal Feng, linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 2040 bytes --]
On Tue, Feb 21, 2023 at 04:33:09PM +0100, Emil Renner Berthing wrote:
> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
> >
> > Add auxiliary driver to support StarFive JH7110 system
> > and always-on resets.
> >
> > Reported-by: kernel test robot <lkp@intel.com>
Drop the reported-by here too please Hal.
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > +static int jh7110_reset_probe(struct auxiliary_device *adev,
> > + const struct auxiliary_device_id *id)
> > +{
> > + struct reset_info *info = (struct reset_info *)(id->driver_data);
> > + void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
>
> Hi Hal,
>
> I saw the kernel test robot complain about this, but I still wonder if
> the extra level of indirection is really needed. Isn't it enough to
> just add the explicit casts, so
>
> dev_set_drvdata(priv->dev, (void *)priv->base);
>
> in the clock drivers and here just
>
> void __iomem *base = (void __iomem *)dev_get_drvdata(adev->dev.parent);
I *think* if you do that, sparse will complain that you cast away the
__iomem. The complaint is something like "cast removes address space
qualifier from expression".
The other option is, rather than set the base as the drvdata, just pass
the whole priv struct. That's what I did for mpfs at least & I thought I
had suggested it on v3, but must not have.
It looks prettier than the casting madness at least ;)
> > +
> > + if (!info || !base)
> > + return -ENODEV;
> > +
> > + return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
> > + *base + info->assert_offset,
> > + *base + info->status_offset,
> > + NULL,
> > + info->nr_resets,
> > + NULL);
> > +}
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-21 2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
@ 2023-02-21 17:03 ` Conor Dooley
2023-02-23 7:16 ` Hal Feng
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 17:03 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
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On Tue, Feb 21, 2023 at 10:46:43AM +0800, Hal Feng wrote:
> + S7_0: cpu@0 {
> + compatible = "sifive,s7", "riscv";
> + reg = <0>;
> + d-cache-block-size = <64>;
> + d-cache-sets = <64>;
> + d-cache-size = <8192>;
> + d-tlb-sets = <1>;
> + d-tlb-size = <40>;
> + device_type = "cpu";
> + i-cache-block-size = <64>;
> + i-cache-sets = <64>;
> + i-cache-size = <16384>;
> + i-tlb-sets = <1>;
> + i-tlb-size = <40>;
> + mmu-type = "riscv,sv39";
> + next-level-cache = <&ccache>;
> + riscv,isa = "rv64imac_zicsr_zba_zbb";
I still think that adding just zicsr here is pointless. If you're going
to be specific, why not also mention that you have zifencei too?
> + tlb-split;
> + status = "disabled";
> +
> + cpu0_intc: interrupt-controller {
> + compatible = "riscv,cpu-intc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> + };
Rest of this looks fine to me though, thanks for adding the s7
compatible and zba/zbb :)
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code
2023-02-21 2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng
@ 2023-02-21 17:10 ` Conor Dooley
0 siblings, 0 replies; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 17:10 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
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On Tue, Feb 21, 2023 at 10:46:31AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> The StarFive JH7100 SoC has additional reset controllers for audio and
> video, but the registers follow the same structure. On the JH7110 the
> reset registers don't get their own memory range, but instead follow the
> clock control registers. The registers still follow the same structure
> though, so let's factor out the common code to handle all these cases.
I think you split this out compared to the previous version of t he
series, and does look as described.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 06/19] reset: starfive: Extract the common JH71X0 reset code
2023-02-21 2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng
@ 2023-02-21 17:13 ` Conor Dooley
0 siblings, 0 replies; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 17:13 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
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On Tue, Feb 21, 2023 at 10:46:32AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Extract the common JH71X0 reset code for reusing them to
> support JH7110 SoC.
>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Split out makes it easier to follow, thanks.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code
2023-02-21 2:46 ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
@ 2023-02-21 17:17 ` Conor Dooley
0 siblings, 0 replies; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 17:17 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
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On Tue, Feb 21, 2023 at 10:46:33AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> For the common code will be shared with the StarFive JH7110 SoC.
>
> Reported-by: kernel test robot <lkp@intel.com>
And here too ;)
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
2023-02-21 2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
@ 2023-02-21 17:23 ` Conor Dooley
2023-02-23 3:40 ` Hal Feng
2023-02-22 9:13 ` Krzysztof Kozlowski
1 sibling, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 17:23 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
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Hey Hal,
On Tue, Feb 21, 2023 at 10:46:35AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add bindings for the system clock and reset generator (SYSCRG) on the
> JH7110 RISC-V SoC by StarFive Ltd.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> new file mode 100644
> index 000000000000..ec81504dcb27
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 System Clock and Reset Generator
> +
> +maintainers:
> + - Emil Renner Berthing <kernel@esmil.dk>
> +
> +properties:
> + compatible:
> + const: starfive,jh7110-syscrg
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Main Oscillator (24 MHz)
> + - description: GMAC1 RMII reference
> + - description: GMAC1 RGMII RX
> + - description: External I2S TX bit clock
> + - description: External I2S TX left/right channel clock
> + - description: External I2S RX bit clock
> + - description: External I2S RX left/right channel clock
> + - description: External TDM clock
> + - description: External audio master clock
You didn't reply to the conversation I had with Krzysztof about how to
represent the optional nature of some of these clocks, contained in this
thread here:
https://lore.kernel.org/all/7a7bccb1-4d47-3d32-36e6-4aab7b5b8dad@starfivetech.com/
What happens to the gmac1 mux if only one of the input clocks is
provided?
And I mean what does the hardware do, not the software representation of
that mux in the driver.
> +
> + clock-names:
> + items:
> + - const: osc
> + - const: gmac1_rmii_refin
> + - const: gmac1_rgmii_rxin
> + - const: i2stx_bclk_ext
> + - const: i2stx_lrck_ext
> + - const: i2srx_bclk_ext
> + - const: i2srx_lrck_ext
> + - const: tdm_ext
> + - const: mclk_ext
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
2023-02-21 2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
@ 2023-02-21 17:26 ` Conor Dooley
2023-02-23 5:52 ` Hal Feng
2023-03-09 14:22 ` Geert Uytterhoeven
1 sibling, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-02-21 17:26 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
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On Tue, Feb 21, 2023 at 10:46:36AM +0800, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add bindings for the always-on clock and reset generator (AONCRG) on the
> JH7110 RISC-V SoC by StarFive Ltd.
> + clocks:
> + items:
> + - description: Main Oscillator (24 MHz)
> + - description: RTC Oscillator (32.768 kHz)
> + - description: GMAC0 RMII reference
> + - description: GMAC0 RGMII RX
> + - description: STG AXI/AHB
> + - description: APB Bus
> + - description: GMAC0 GTX
Ditto here, are some of these clocks, especially gmac0, also optional?
> +
> + clock-names:
> + items:
> + - const: osc
> + - const: rtc_osc
> + - const: gmac0_rmii_refin
> + - const: gmac0_rgmii_rxin
> + - const: stg_axiahb
> + - const: apb_bus
> + - const: gmac0_gtxclk
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
2023-02-21 2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-02-21 17:23 ` Conor Dooley
@ 2023-02-22 9:13 ` Krzysztof Kozlowski
2023-02-22 10:40 ` Conor Dooley
1 sibling, 1 reply; 71+ messages in thread
From: Krzysztof Kozlowski @ 2023-02-22 9:13 UTC (permalink / raw)
To: Hal Feng, linux-clk, devicetree, linux-riscv
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
On 21/02/2023 03:46, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add bindings for the system clock and reset generator (SYSCRG) on the
> JH7110 RISC-V SoC by StarFive Ltd.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
I don't know what is happening here as neither this nor other patchset
explains anything. Please stop writing what you do in the patches, but
explain why. What is easy to get.
(...)
> +
> +#define JH7110_SYSCLK_PLL0_OUT 190
> +#define JH7110_SYSCLK_PLL1_OUT 191
> +#define JH7110_SYSCLK_PLL2_OUT 192
NAK. Do not add incorrect bindings just to remove it THE SAME TIME.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
2023-02-22 9:13 ` Krzysztof Kozlowski
@ 2023-02-22 10:40 ` Conor Dooley
2023-02-23 10:22 ` Hal Feng
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-02-22 10:40 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Hal Feng, linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
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On Wed, Feb 22, 2023 at 10:13:19AM +0100, Krzysztof Kozlowski wrote:
> On 21/02/2023 03:46, Hal Feng wrote:
> > From: Emil Renner Berthing <kernel@esmil.dk>
> >
> > Add bindings for the system clock and reset generator (SYSCRG) on the
> > JH7110 RISC-V SoC by StarFive Ltd.
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
> I don't know what is happening here as neither this nor other patchset
> explains anything. Please stop writing what you do in the patches, but
> explain why. What is easy to get.
>
> (...)
>
>
> > +
> > +#define JH7110_SYSCLK_PLL0_OUT 190
> > +#define JH7110_SYSCLK_PLL1_OUT 191
> > +#define JH7110_SYSCLK_PLL2_OUT 192
>
> NAK. Do not add incorrect bindings just to remove it THE SAME TIME.
For some context, the PLL driver series [1] does the following, which is
where this complaint stems from:
> diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
> index 5e4f21ca0642..086a6ddcf380 100644
> --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
> +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
> @@ -6,6 +6,12 @@
> #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
> #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>
> +/* PLL clocks */
> +#define JH7110_CLK_PLL0_OUT 0
> +#define JH7110_CLK_PLL1_OUT 1
> +#define JH7110_CLK_PLL2_OUT 2
> +#define JH7110_PLLCLK_END 3
> +
> /* SYSCRG clocks */
> #define JH7110_SYSCLK_CPU_ROOT 0
> #define JH7110_SYSCLK_CPU_CORE 1
> @@ -198,11 +204,7 @@
> #define JH7110_SYSCLK_TDM_TDM_INV 188
> #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
>
> -#define JH7110_SYSCLK_PLL0_OUT 190
> -#define JH7110_SYSCLK_PLL1_OUT 191
> -#define JH7110_SYSCLK_PLL2_OUT 192
I was talking to Emil, who pointed out that these defines aren't
actually ever used in the dts, so there's nothing really gained
by adding them here in the first place.
Seems like this series could simply move these defines into the driver
(as the PLL addition series also does) and then we would not have to
be worried about breaking the ABI in the future?
Thanks,
Conor.
1 - https://patchwork.kernel.org/project/linux-riscv/patch/20230221141147.303642-3-xingyu.wu@starfivetech.com/
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (18 preceding siblings ...)
2023-02-21 2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
@ 2023-02-22 15:00 ` patchwork-bot+linux-riscv
2023-03-03 19:08 ` Tommaso Merciai
2023-03-07 8:36 ` Hal Feng
21 siblings, 0 replies; 71+ messages in thread
From: patchwork-bot+linux-riscv @ 2023-02-22 15:00 UTC (permalink / raw)
To: Hal Feng
Cc: linux-riscv, linux-clk, devicetree, sboyd, mturquette, p.zabel,
robh+dt, krzysztof.kozlowski+dt, conor, palmer, paul.walmsley,
aou, ben.dooks, daniel.lezcano, tglx, maz, emil.renner.berthing,
linux-kernel
Hello:
This series was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Tue, 21 Feb 2023 10:46:26 +0800 you wrote:
> This patch series adds basic clock, reset & DT support for StarFive
> JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
> dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
> of VisionFive 2 board and JH7110 SoC.
>
> You can simply review or test the patches at the link [3].
>
> [...]
Here is the summary with links:
- [v4,01/19] clk: starfive: Factor out common JH7100 and JH7110 code
(no matching commit)
- [v4,02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
https://git.kernel.org/riscv/c/f3af3b0039fe
- [v4,03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code
(no matching commit)
- [v4,04/19] reset: Create subdirectory for StarFive drivers
(no matching commit)
- [v4,05/19] reset: starfive: Factor out common JH71X0 reset code
(no matching commit)
- [v4,06/19] reset: starfive: Extract the common JH71X0 reset code
(no matching commit)
- [v4,07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code
(no matching commit)
- [v4,08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
(no matching commit)
- [v4,09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
(no matching commit)
- [v4,10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
(no matching commit)
- [v4,11/19] clk: starfive: Add StarFive JH7110 system clock driver
(no matching commit)
- [v4,12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
(no matching commit)
- [v4,13/19] reset: starfive: Add StarFive JH7110 reset driver
(no matching commit)
- [v4,14/19] dt-bindings: timer: Add StarFive JH7110 clint
(no matching commit)
- [v4,15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic
(no matching commit)
- [v4,16/19] dt-bindings: riscv: Add SiFive S7 compatible
(no matching commit)
- [v4,17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree
(no matching commit)
- [v4,18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions
(no matching commit)
- [v4,19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
(no matching commit)
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
2023-02-21 17:23 ` Conor Dooley
@ 2023-02-23 3:40 ` Hal Feng
0 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-23 3:40 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
On Tue, 21 Feb 2023 17:23:36 +0000, Conor Dooley wrote:
> Hey Hal,
>
> On Tue, Feb 21, 2023 at 10:46:35AM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add bindings for the system clock and reset generator (SYSCRG) on the
>> JH7110 RISC-V SoC by StarFive Ltd.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
>> diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> new file mode 100644
>> index 000000000000..ec81504dcb27
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
>> @@ -0,0 +1,80 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 System Clock and Reset Generator
>> +
>> +maintainers:
>> + - Emil Renner Berthing <kernel@esmil.dk>
>> +
>> +properties:
>> + compatible:
>> + const: starfive,jh7110-syscrg
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: Main Oscillator (24 MHz)
>> + - description: GMAC1 RMII reference
>> + - description: GMAC1 RGMII RX
>> + - description: External I2S TX bit clock
>> + - description: External I2S TX left/right channel clock
>> + - description: External I2S RX bit clock
>> + - description: External I2S RX left/right channel clock
>> + - description: External TDM clock
>> + - description: External audio master clock
>
> You didn't reply to the conversation I had with Krzysztof about how to
> represent the optional nature of some of these clocks, contained in this
> thread here:
> https://lore.kernel.org/all/7a7bccb1-4d47-3d32-36e6-4aab7b5b8dad@starfivetech.com/
>
> What happens to the gmac1 mux if only one of the input clocks is
> provided?
> And I mean what does the hardware do, not the software representation of
> that mux in the driver.
In hardware, just providing the required input clocks is enough. Refer to the
following link for the required clocks. Thanks.
https://lore.kernel.org/all/c0472d7f-56fe-3e91-e0a0-49ee51700b5d@starfivetech.com/
Best regards,
Hal
>
>> +
>> + clock-names:
>> + items:
>> + - const: osc
>> + - const: gmac1_rmii_refin
>> + - const: gmac1_rgmii_rxin
>> + - const: i2stx_bclk_ext
>> + - const: i2stx_lrck_ext
>> + - const: i2srx_bclk_ext
>> + - const: i2srx_lrck_ext
>> + - const: tdm_ext
>> + - const: mclk_ext
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
2023-02-21 17:26 ` Conor Dooley
@ 2023-02-23 5:52 ` Hal Feng
0 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-23 5:52 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
On Tue, 21 Feb 2023 17:26:52 +0000, Conor Dooley wrote:
> On Tue, Feb 21, 2023 at 10:46:36AM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add bindings for the always-on clock and reset generator (AONCRG) on the
>> JH7110 RISC-V SoC by StarFive Ltd.
>
>> + clocks:
>> + items:
>> + - description: Main Oscillator (24 MHz)
>> + - description: RTC Oscillator (32.768 kHz)
>> + - description: GMAC0 RMII reference
>> + - description: GMAC0 RGMII RX
>> + - description: STG AXI/AHB
>> + - description: APB Bus
>> + - description: GMAC0 GTX
>
> Ditto here, are some of these clocks, especially gmac0, also optional?
The clock "rtc_osc" and "gmac0_rmii_refin" are optional, the other
clocks are required. I will modify accordingly. Thanks.
Best regards,
Hal
>
>> +
>> + clock-names:
>> + items:
>> + - const: osc
>> + - const: rtc_osc
>> + - const: gmac0_rmii_refin
>> + - const: gmac0_rgmii_rxin
>> + - const: stg_axiahb
>> + - const: apb_bus
>> + - const: gmac0_gtxclk
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver
2023-02-21 15:12 ` Conor Dooley
@ 2023-02-23 6:17 ` Hal Feng
0 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-23 6:17 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
On Tue, 21 Feb 2023 15:12:43 +0000, Conor Dooley wrote:
> On Tue, Feb 21, 2023 at 10:46:37AM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add driver for the StarFive JH7110 system clock controller and
>> register an auxiliary device for system reset controller which
>> is named as "reset-sys".
>>
>> Reported-by: kernel test robot <lkp@intel.com>
>
> How is this Reported-by lkp?
> If lkp responded to your patch saying there was a problem with it, it
> doesn't get a Reported-by - just like how any other reviewer doesn't get
> a Reported-by for pointing out build issues ;)
> You only need to add that for bugs it reports on patches that have
> already been applied ;)
I don't know. I just saw the following message in [1]. I will remove
it as you suggested. Ditto for the other patches. Thank you.
"If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>"
[1] https://lore.kernel.org/all/202212231726.ZYGFg045-lkp@intel.com/
Best regards,
Hal
>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver
2023-02-21 15:33 ` Emil Renner Berthing
2023-02-21 16:34 ` Conor Dooley
@ 2023-02-23 6:29 ` Hal Feng
1 sibling, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-23 6:29 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Tue, 21 Feb 2023 16:33:09 +0100, Emil Renner Berthing wrote:
> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>>
>> Add auxiliary driver to support StarFive JH7110 system
>> and always-on resets.
>>
>> Reported-by: kernel test robot <lkp@intel.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> drivers/reset/starfive/Kconfig | 8 +++
>> drivers/reset/starfive/Makefile | 1 +
>> .../reset/starfive/reset-starfive-jh7110.c | 64 +++++++++++++++++++
>> .../reset/starfive/reset-starfive-jh71x0.h | 6 ++
>> 4 files changed, 79 insertions(+)
>> create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
>>
[...]
>> diff --git a/drivers/reset/starfive/reset-starfive-jh71x0.h b/drivers/reset/starfive/reset-starfive-jh71x0.h
>> index db7d39a87f87..e485472e1adc 100644
>> --- a/drivers/reset/starfive/reset-starfive-jh71x0.h
>> +++ b/drivers/reset/starfive/reset-starfive-jh71x0.h
>> @@ -6,6 +6,12 @@
>> #ifndef __RESET_STARFIVE_JH71X0_H
>> #define __RESET_STARFIVE_JH71X0_H
>>
>> +struct reset_info {
>> + unsigned int nr_resets;
>> + unsigned int assert_offset;
>> + unsigned int status_offset;
>> +};
>
> As far as I can tell this struct isn't used anywhere but in
> reset-starfive-jh7110.c. If so just move it there, and in any case
> please call it something less generic like struct jh7110_reset_info.
OK, will fix it. Thanks.
Best regards,
Hal
>
>> +
>> int reset_starfive_jh71x0_register(struct device *dev, struct device_node *of_node,
>> void __iomem *assert, void __iomem *status,
>> const u32 *asserted, unsigned int nr_resets,
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver
2023-02-21 16:34 ` Conor Dooley
@ 2023-02-23 6:48 ` Hal Feng
0 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-23 6:48 UTC (permalink / raw)
To: Conor Dooley, Emil Renner Berthing
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
linux-kernel
On Tue, 21 Feb 2023 16:34:11 +0000, Conor Dooley wrote:
> On Tue, Feb 21, 2023 at 04:33:09PM +0100, Emil Renner Berthing wrote:
>> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>> >
>> > Add auxiliary driver to support StarFive JH7110 system
>> > and always-on resets.
>> >
>> > Reported-by: kernel test robot <lkp@intel.com>
>
> Drop the reported-by here too please Hal.
OK.
>
>> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
>> > +static int jh7110_reset_probe(struct auxiliary_device *adev,
>> > + const struct auxiliary_device_id *id)
>> > +{
>> > + struct reset_info *info = (struct reset_info *)(id->driver_data);
>> > + void __iomem **base = (void __iomem **)dev_get_drvdata(adev->dev.parent);
>>
>> Hi Hal,
>>
>> I saw the kernel test robot complain about this, but I still wonder if
>> the extra level of indirection is really needed. Isn't it enough to
>> just add the explicit casts, so
>>
>> dev_set_drvdata(priv->dev, (void *)priv->base);
>>
>> in the clock drivers and here just
>>
>> void __iomem *base = (void __iomem *)dev_get_drvdata(adev->dev.parent);
>
> I *think* if you do that, sparse will complain that you cast away the
> __iomem. The complaint is something like "cast removes address space
> qualifier from expression".
>
> The other option is, rather than set the base as the drvdata, just pass
> the whole priv struct. That's what I did for mpfs at least & I thought I
> had suggested it on v3, but must not have.
> It looks prettier than the casting madness at least ;)
I modified this just because we need to use container_of() to get some
struct in [1].
+struct isp_top_crg {
+ struct clk_bulk_data *top_clks;
+ struct reset_control *top_rsts;
+ int top_clks_num;
+ void __iomem *base;
+};
+static struct isp_top_crg *top_crg_from(void __iomem **base)
+{
+ return container_of(base, struct isp_top_crg, base);
+}
[1] https://lore.kernel.org/all/20230221083323.302471-7-xingyu.wu@starfivetech.com/
If we pass the whole priv struct, we need to make the priv struct
public. I think setting the address of "base" as the drvdata is
enough and easier.
Best regards,
Hal
>
>> > +
>> > + if (!info || !base)
>> > + return -ENODEV;
>> > +
>> > + return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
>> > + *base + info->assert_offset,
>> > + *base + info->status_offset,
>> > + NULL,
>> > + info->nr_resets,
>> > + NULL);
>> > +}
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-21 17:03 ` Conor Dooley
@ 2023-02-23 7:16 ` Hal Feng
2023-02-27 18:10 ` Conor Dooley
0 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-23 7:16 UTC (permalink / raw)
To: Conor Dooley
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
On Tue, 21 Feb 2023 17:03:52 +0000, Conor Dooley wrote:
> On Tue, Feb 21, 2023 at 10:46:43AM +0800, Hal Feng wrote:
>
>> + S7_0: cpu@0 {
>> + compatible = "sifive,s7", "riscv";
>> + reg = <0>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <8192>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <16384>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imac_zicsr_zba_zbb";
>
> I still think that adding just zicsr here is pointless. If you're going
> to be specific, why not also mention that you have zifencei too?
I would like to remove "_zicsr" in the next version. Thanks.
>
>> + tlb-split;
>> + status = "disabled";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>
> Rest of this looks fine to me though, thanks for adding the s7
> compatible and zba/zbb :)
Thanks for your review. :)
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-21 15:03 ` Emil Renner Berthing
@ 2023-02-23 8:50 ` Hal Feng
2023-02-27 18:12 ` Conor Dooley
0 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-23 8:50 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Tue, 21 Feb 2023 16:03:08 +0100, Emil Renner Berthing wrote:
> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
>> which has version A and version B. Support booting and basic
>> clock/reset/pinctrl/uart drivers.
>>
>> Acked-by: Conor Dooley <conor.dooley@microchip.com>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> arch/riscv/boot/dts/starfive/Makefile | 6 +-
>> .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
>> .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
>> .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
>> 4 files changed, 246 insertions(+), 1 deletion(-)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
>> index 039c143cba33..cd73519b907b 100644
>> --- a/arch/riscv/boot/dts/starfive/Makefile
>> +++ b/arch/riscv/boot/dts/starfive/Makefile
>> @@ -1,2 +1,6 @@
>> # SPDX-License-Identifier: GPL-2.0
>> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
>> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
>> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
>> +
>> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
>> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
>> new file mode 100644
>> index 000000000000..4af3300f3cf3
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110-starfive-visionfive-2.dtsi"
>> +
>> +/ {
>> + model = "StarFive VisionFive 2 v1.2A";
>> + compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
>> +};
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
>> new file mode 100644
>> index 000000000000..9230cc3d8946
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
>> @@ -0,0 +1,13 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110-starfive-visionfive-2.dtsi"
>> +
>> +/ {
>> + model = "StarFive VisionFive 2 v1.3B";
>> + compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
>> +};
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> new file mode 100644
>> index 000000000000..c2aa8946a0f1
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -0,0 +1,215 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + */
>> +
>> +/dts-v1/;
>> +#include "jh7110.dtsi"
>> +#include "jh7110-pinfunc.h"
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/ {
>> + aliases {
>> + serial0 = &uart0;
>> + i2c0 = &i2c0;
>> + i2c2 = &i2c2;
>> + i2c5 = &i2c5;
>> + i2c6 = &i2c6;
>
> Let's keep these sorted alphabetically.
OK, will fix it.
>
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial0:115200n8";
>> + };
>> +
>> + cpus {
>> + timebase-frequency = <4000000>;
>> + };
>> +
>> + memory@40000000 {
>> + device_type = "memory";
>> + reg = <0x0 0x40000000 0x1 0x0>;
>> + };
>> +
>> + gpio-restart {
>> + compatible = "gpio-restart";
>> + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
>> + priority = <224>;
>> + };
>> +};
>> +
>> +&osc {
>> + clock-frequency = <24000000>;
>> +};
>> +
>> +&rtc_osc {
>> + clock-frequency = <32768>;
>> +};
>> +
>> +&gmac0_rmii_refin {
>> + clock-frequency = <50000000>;
>> +};
>> +
>> +&gmac0_rgmii_rxin {
>> + clock-frequency = <125000000>;
>> +};
>> +
>> +&gmac1_rmii_refin {
>> + clock-frequency = <50000000>;
>> +};
>> +
>> +&gmac1_rgmii_rxin {
>> + clock-frequency = <125000000>;
>> +};
>> +
>> +&i2stx_bclk_ext {
>> + clock-frequency = <12288000>;
>> +};
>> +
>> +&i2stx_lrck_ext {
>> + clock-frequency = <192000>;
>> +};
>> +
>> +&i2srx_bclk_ext {
>> + clock-frequency = <12288000>;
>> +};
>> +
>> +&i2srx_lrck_ext {
>> + clock-frequency = <192000>;
>> +};
>> +
>> +&tdm_ext {
>> + clock-frequency = <49152000>;
>> +};
>> +
>> +&mclk_ext {
>> + clock-frequency = <12288000>;
>> +};
>> +
>> +&uart0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&uart0_pins>;
>> + status = "okay";
>> +};
>> +
>> +&i2c0 {
>> + clock-frequency = <100000>;
>> + i2c-sda-hold-time-ns = <300>;
>> + i2c-sda-falling-time-ns = <510>;
>> + i2c-scl-falling-time-ns = <510>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c0_pins>;
>> + status = "okay";
>> +};
>> +
>> +&i2c2 {
>> + clock-frequency = <100000>;
>> + i2c-sda-hold-time-ns = <300>;
>> + i2c-sda-falling-time-ns = <510>;
>> + i2c-scl-falling-time-ns = <510>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c2_pins>;
>> + status = "okay";
>> +};
>> +
>> +&i2c5 {
>> + clock-frequency = <100000>;
>> + i2c-sda-hold-time-ns = <300>;
>> + i2c-sda-falling-time-ns = <510>;
>> + i2c-scl-falling-time-ns = <510>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c5_pins>;
>> + status = "okay";
>> +};
>> +
>> +&i2c6 {
>> + clock-frequency = <100000>;
>> + i2c-sda-hold-time-ns = <300>;
>> + i2c-sda-falling-time-ns = <510>;
>> + i2c-scl-falling-time-ns = <510>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&i2c6_pins>;
>> + status = "okay";
>> +};
>> +
>> +&sysgpio {
>> + uart0_pins: uart0-0 {
>> + tx-pins {
>> + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
>> + GPOEN_ENABLE,
>> + GPI_NONE)>;
>> + bias-disable;
>> + drive-strength = <12>;
>> + input-disable;
>> + input-schmitt-disable;
>> + slew-rate = <0>;
>> + };
>> +
>> + rx-pins {
>> + pinmux = <GPIOMUX(6, GPOUT_LOW,
>> + GPOEN_DISABLE,
>> + GPI_SYS_UART0_RX)>;
>> + bias-disable; /* external pull-up */
>> + drive-strength = <2>;
>> + input-enable;
>> + input-schmitt-enable;
>> + slew-rate = <0>;
>> + };
>> + };
>> +
>> + i2c0_pins: i2c0-0 {
>> + i2c-pins {
>> + pinmux = <GPIOMUX(57, GPOUT_LOW,
>> + GPOEN_SYS_I2C0_CLK,
>> + GPI_SYS_I2C0_CLK)>,
>> + <GPIOMUX(58, GPOUT_LOW,
>> + GPOEN_SYS_I2C0_DATA,
>> + GPI_SYS_I2C0_DATA)>;
>> + bias-disable; /* external pull-up */
>> + input-enable;
>> + input-schmitt-enable;
>> + };
>> + };
>> +
>> + i2c2_pins: i2c2-0 {
>> + i2c-pins {
>> + pinmux = <GPIOMUX(3, GPOUT_LOW,
>> + GPOEN_SYS_I2C2_CLK,
>> + GPI_SYS_I2C2_CLK)>,
>> + <GPIOMUX(2, GPOUT_LOW,
>> + GPOEN_SYS_I2C2_DATA,
>> + GPI_SYS_I2C2_DATA)>;
>> + bias-disable; /* external pull-up */
>> + input-enable;
>> + input-schmitt-enable;
>> + };
>> + };
>> +
>> + i2c5_pins: i2c5-0 {
>> + i2c-pins {
>> + pinmux = <GPIOMUX(19, GPOUT_LOW,
>> + GPOEN_SYS_I2C5_CLK,
>> + GPI_SYS_I2C5_CLK)>,
>> + <GPIOMUX(20, GPOUT_LOW,
>> + GPOEN_SYS_I2C5_DATA,
>> + GPI_SYS_I2C5_DATA)>;
>> + bias-disable; /* external pull-up */
>> + input-enable;
>> + input-schmitt-enable;
>> + };
>> + };
>> +
>> + i2c6_pins: i2c6-0 {
>> + i2c-pins {
>> + pinmux = <GPIOMUX(16, GPOUT_LOW,
>> + GPOEN_SYS_I2C6_CLK,
>> + GPI_SYS_I2C6_CLK)>,
>> + <GPIOMUX(17, GPOUT_LOW,
>> + GPOEN_SYS_I2C6_DATA,
>> + GPI_SYS_I2C6_DATA)>;
>> + bias-disable; /* external pull-up */
>> + input-enable;
>> + input-schmitt-enable;
>> + };
>> + };
>> +};
>
> It would be great to have some sort of order to this file so it's
> obvious where to add new nodes. I suggest we do
> - root node
> - external clocks
> - other node references in alphabetical order
>
> You're almost there with this patch except the uart0 node is out of place.
Will fix accordingly. Thanks for your suggestions.
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
2023-02-22 10:40 ` Conor Dooley
@ 2023-02-23 10:22 ` Hal Feng
0 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-23 10:22 UTC (permalink / raw)
To: Conor Dooley, Krzysztof Kozlowski
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
On Wed, 22 Feb 2023 10:40:59 +0000, Conor Dooley wrote:
> On Wed, Feb 22, 2023 at 10:13:19AM +0100, Krzysztof Kozlowski wrote:
>> On 21/02/2023 03:46, Hal Feng wrote:
>> > From: Emil Renner Berthing <kernel@esmil.dk>
>> >
>> > Add bindings for the system clock and reset generator (SYSCRG) on the
>> > JH7110 RISC-V SoC by StarFive Ltd.
>> >
>> > Reviewed-by: Rob Herring <robh@kernel.org>
>> > Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> > Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>
>> I don't know what is happening here as neither this nor other patchset
>> explains anything. Please stop writing what you do in the patches, but
>> explain why. What is easy to get.
>>
>> (...)
>>
>>
>> > +
>> > +#define JH7110_SYSCLK_PLL0_OUT 190
>> > +#define JH7110_SYSCLK_PLL1_OUT 191
>> > +#define JH7110_SYSCLK_PLL2_OUT 192
>>
>> NAK. Do not add incorrect bindings just to remove it THE SAME TIME.
>
> For some context, the PLL driver series [1] does the following, which is
> where this complaint stems from:
>> diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> index 5e4f21ca0642..086a6ddcf380 100644
>> --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
>> +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
>> @@ -6,6 +6,12 @@
>> #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>> #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
>>
>> +/* PLL clocks */
>> +#define JH7110_CLK_PLL0_OUT 0
>> +#define JH7110_CLK_PLL1_OUT 1
>> +#define JH7110_CLK_PLL2_OUT 2
>> +#define JH7110_PLLCLK_END 3
>> +
>> /* SYSCRG clocks */
>> #define JH7110_SYSCLK_CPU_ROOT 0
>> #define JH7110_SYSCLK_CPU_CORE 1
>> @@ -198,11 +204,7 @@
>> #define JH7110_SYSCLK_TDM_TDM_INV 188
>> #define JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG 189
>>
>> -#define JH7110_SYSCLK_PLL0_OUT 190
>> -#define JH7110_SYSCLK_PLL1_OUT 191
>> -#define JH7110_SYSCLK_PLL2_OUT 192
>
> I was talking to Emil, who pointed out that these defines aren't
> actually ever used in the dts, so there's nothing really gained
> by adding them here in the first place.
> Seems like this series could simply move these defines into the driver
> (as the PLL addition series also does) and then we would not have to
> be worried about breaking the ABI in the future?
Sorry for that I didn't synchronize this with Xingyu. I'll move these
PLL definitions into the driver in the next version.
Best regards,
Hal
>
> 1 - https://patchwork.kernel.org/project/linux-riscv/patch/20230221141147.303642-3-xingyu.wu@starfivetech.com/
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver
2023-02-21 2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-02-21 15:12 ` Conor Dooley
@ 2023-02-26 16:07 ` Emil Renner Berthing
2023-02-28 2:30 ` Hal Feng
1 sibling, 1 reply; 71+ messages in thread
From: Emil Renner Berthing @ 2023-02-26 16:07 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add driver for the StarFive JH7110 system clock controller and
> register an auxiliary device for system reset controller which
> is named as "reset-sys".
>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> drivers/clk/starfive/Kconfig | 11 +
> drivers/clk/starfive/Makefile | 2 +
> .../clk/starfive/clk-starfive-jh7110-sys.c | 448 ++++++++++++++++++
> drivers/clk/starfive/clk-starfive-jh71x0.c | 50 ++
> drivers/clk/starfive/clk-starfive-jh71x0.h | 8 +
> 5 files changed, 519 insertions(+)
> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
>
> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> index 594d516dcb38..4640d0665d1c 100644
> --- a/drivers/clk/starfive/Kconfig
> +++ b/drivers/clk/starfive/Kconfig
> @@ -20,3 +20,14 @@ config CLK_STARFIVE_JH7100_AUDIO
> help
> Say Y or M here to support the audio clocks on the StarFive JH7100
> SoC.
> +
> +config CLK_STARFIVE_JH7110_SYS
> + bool "StarFive JH7110 system clock support"
> + depends on SOC_STARFIVE || COMPILE_TEST
> + select AUXILIARY_BUS
> + select CLK_STARFIVE_JH71X0
> + select RESET_STARFIVE_JH7110
> + default SOC_STARFIVE
> + help
> + Say yes here to support the system clock controller on the
> + StarFive JH7110 SoC.
> diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> index 82edfa9f9cb8..5ca4e887fb9c 100644
> --- a/drivers/clk/starfive/Makefile
> +++ b/drivers/clk/starfive/Makefile
> @@ -3,3 +3,5 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0) += clk-starfive-jh71x0.o
>
> obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
> obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
> +
> +obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> new file mode 100644
> index 000000000000..6e230b81a387
> --- /dev/null
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
> @@ -0,0 +1,448 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive JH7110 System Clock Driver
> + *
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> +
> +#include "clk-starfive-jh71x0.h"
> +
> +/* external clocks */
> +#define JH7110_SYSCLK_OSC (JH7110_SYSCLK_END + 0)
> +#define JH7110_SYSCLK_GMAC1_RMII_REFIN (JH7110_SYSCLK_END + 1)
> +#define JH7110_SYSCLK_GMAC1_RGMII_RXIN (JH7110_SYSCLK_END + 2)
> +#define JH7110_SYSCLK_I2STX_BCLK_EXT (JH7110_SYSCLK_END + 3)
> +#define JH7110_SYSCLK_I2STX_LRCK_EXT (JH7110_SYSCLK_END + 4)
> +#define JH7110_SYSCLK_I2SRX_BCLK_EXT (JH7110_SYSCLK_END + 5)
> +#define JH7110_SYSCLK_I2SRX_LRCK_EXT (JH7110_SYSCLK_END + 6)
> +#define JH7110_SYSCLK_TDM_EXT (JH7110_SYSCLK_END + 7)
> +#define JH7110_SYSCLK_MCLK_EXT (JH7110_SYSCLK_END + 8)
> +
> +static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
> + /* root */
> + JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
> + JH7110_SYSCLK_OSC,
> + JH7110_SYSCLK_PLL0_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
> + JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
> + JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
> + JH7110_SYSCLK_PLL2_OUT,
> + JH7110_SYSCLK_PLL1_OUT),
> + JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
> + JH7110_SYSCLK_PLL0_OUT,
> + JH7110_SYSCLK_PLL2_OUT),
> + JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
> + JH7110_SYSCLK_OSC,
> + JH7110_SYSCLK_PLL2_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
> + JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
> + JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
> + JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
> + JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
> + JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
> + JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
> + JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
> + JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
> + JH7110_SYSCLK_MCLK_INNER,
> + JH7110_SYSCLK_MCLK_EXT),
> + JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
> + JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
> + JH7110_SYSCLK_PLL2_OUT,
> + JH7110_SYSCLK_PLL1_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
> + JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
> + JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
> + JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
> + /* cores */
> + JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
> + JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
> + JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
> + /* noc */
> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_CPU_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_AXI_CFG0),
> + /* ddr */
> + JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
> + JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
> + JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
> + JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
> + JH7110_SYSCLK_OSC_DIV2,
> + JH7110_SYSCLK_PLL1_DIV2,
> + JH7110_SYSCLK_PLL1_DIV4,
> + JH7110_SYSCLK_PLL1_DIV8),
> + JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IGNORE_UNUSED, JH7110_SYSCLK_DDR_BUS),
> + /* gpu */
> + JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
> + JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
> + JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
> + JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
> + /* isp */
> + JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
> + JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
> + JH7110_SYSCLK_ISP_AXI),
> + /* hifi4 */
> + JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
> + JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
> + /* axi_cfg1 */
> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_ISP_AXI),
> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_AHB0),
> + /* vout */
> + JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
> + JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
> + JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
> + JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
> + JH7110_SYSCLK_MCLK),
> + JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
> + JH7110_SYSCLK_OSC),
> + /* jpegc */
> + JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
> + JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
> + /* vdec */
> + JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
> + JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
> + JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
> + JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
> + JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_JPEGC_AXI),
> + JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_VDEC_AXI),
> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
> + /* venc */
> + JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
> + JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
> + JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI),
> + /* axi_cfg0 */
> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_AHB1),
> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_AXI_CFG0),
> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_HIFI4_AXI),
> + /* intmem */
> + JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_AXI_CFG0),
> + /* qspi */
> + JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB1),
> + JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB_BUS),
> + JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
> + JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", CLK_IGNORE_UNUSED, 2,
> + JH7110_SYSCLK_OSC,
> + JH7110_SYSCLK_QSPI_REF_SRC),
> + /* sdio */
> + JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB0),
> + JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB0),
> + JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", CLK_IGNORE_UNUSED, 15,
> + JH7110_SYSCLK_AXI_CFG0),
> + JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", CLK_IGNORE_UNUSED, 15,
> + JH7110_SYSCLK_AXI_CFG0),
> + /* stg */
> + JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_NOCSTG_BUS),
> + /* gmac1 */
> + JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
> + JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
> + JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
> + JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
> + JH7110_SYSCLK_GMAC1_RMII_REFIN),
> + JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> + JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
> + JH7110_SYSCLK_GMAC1_RGMII_RXIN,
> + JH7110_SYSCLK_GMAC1_RMII_RTX),
> + JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
> + JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", 0, 2,
> + JH7110_SYSCLK_GMAC1_GTXCLK,
> + JH7110_SYSCLK_GMAC1_RMII_RTX),
> + JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
> + JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
> + /* gmac0 */
> + JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
> + JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> + JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
> + JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
> + /* apb misc */
> + JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_APB_BUS),
> + /* can0 */
> + JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
> + JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
> + /* can1 */
> + JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
> + JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
> + /* pwm */
> + JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
> + /* wdt */
> + JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
> + /* timer */
> + JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", CLK_IGNORE_UNUSED,
> + JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
> + JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
> + JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
> + JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
> + /* temp sensor */
> + JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
> + /* spi */
> + JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
> + /* i2c */
> + JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
> + JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
> + /* uart */
> + JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
> + JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
> + JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
> + JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> + JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> + JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
> + /* pwmdac */
> + JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
> + /* spdif */
> + JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
> + /* i2stx0 */
> + JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> + JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
> + JH7110_SYSCLK_I2STX0_BCLK_MST),
> + JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
> + JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
> + JH7110_SYSCLK_I2STX0_BCLK_MST),
> + JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
> + JH7110_SYSCLK_I2STX0_BCLK_MST,
> + JH7110_SYSCLK_I2STX_BCLK_EXT),
> + JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
> + JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
> + JH7110_SYSCLK_I2STX0_LRCK_MST,
> + JH7110_SYSCLK_I2STX_LRCK_EXT),
> + /* i2stx1 */
> + JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> + JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
> + JH7110_SYSCLK_I2STX1_BCLK_MST),
> + JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
> + JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
> + JH7110_SYSCLK_I2STX1_BCLK_MST),
> + JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
> + JH7110_SYSCLK_I2STX1_BCLK_MST,
> + JH7110_SYSCLK_I2STX_BCLK_EXT),
> + JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
> + JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
> + JH7110_SYSCLK_I2STX1_LRCK_MST,
> + JH7110_SYSCLK_I2STX_LRCK_EXT),
> + /* i2srx */
> + JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
> + JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
> + JH7110_SYSCLK_I2SRX_BCLK_MST),
> + JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
> + JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
> + JH7110_SYSCLK_I2SRX_BCLK_MST),
> + JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
> + JH7110_SYSCLK_I2SRX_BCLK_MST,
> + JH7110_SYSCLK_I2SRX_BCLK_EXT),
> + JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
> + JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
> + JH7110_SYSCLK_I2SRX_LRCK_MST,
> + JH7110_SYSCLK_I2SRX_LRCK_EXT),
> + /* pdm */
> + JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
> + JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
> + /* tdm */
> + JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
> + JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
> + JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
> + JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
> + JH7110_SYSCLK_TDM_INTERNAL,
> + JH7110_SYSCLK_TDM_EXT),
> + JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
> + /* jtag */
> + JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
> + JH7110_SYSCLK_OSC),
> +};
Hi Hal,
I noticed this list still contains both clocks with the
CLK_IS_CRITICAL flag and the CLK_IGNORE_UNUSED. I fear I may be source
of this because I used the CLK_IGNORE_UNUSED as a placeholder until I
figured out if the clock was critical or not. For the next revision
could you please go through clocks marked with CLK_IGNORE_UNUSED and
determine if they're critical or they can be safely turned off when
not used by any peripheral.
/Emil
> +static struct clk_hw *jh7110_sysclk_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct jh71x0_clk_priv *priv = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx < JH7110_SYSCLK_PLL0_OUT)
> + return &priv->reg[idx].hw;
> +
> + if (idx < JH7110_SYSCLK_END)
> + return priv->pll[idx - JH7110_SYSCLK_PLL0_OUT];
> +
> + return ERR_PTR(-EINVAL);
> +}
> +
> +static int __init jh7110_syscrg_probe(struct platform_device *pdev)
> +{
> + struct jh71x0_clk_priv *priv;
> + unsigned int idx;
> + int ret;
> +
> + priv = devm_kzalloc(&pdev->dev,
> + struct_size(priv, reg, JH7110_SYSCLK_PLL0_OUT),
> + GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + spin_lock_init(&priv->rmw_lock);
> + priv->dev = &pdev->dev;
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + dev_set_drvdata(priv->dev, (void *)(&priv->base));
> +
> + /* 24MHz -> 1000.0MHz */
> + priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
> + "osc", 0, 125, 3);
> + if (IS_ERR(priv->pll[0]))
> + return PTR_ERR(priv->pll[0]);
> +
> + /* 24MHz -> 1066.0MHz */
> + priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
> + "osc", 0, 533, 12);
> + if (IS_ERR(priv->pll[1]))
> + return PTR_ERR(priv->pll[1]);
> +
> + /* 24MHz -> 1188.0MHz */
> + priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
> + "osc", 0, 99, 2);
> + if (IS_ERR(priv->pll[2]))
> + return PTR_ERR(priv->pll[2]);
> +
> + for (idx = 0; idx < JH7110_SYSCLK_PLL0_OUT; idx++) {
> + u32 max = jh7110_sysclk_data[idx].max;
> + struct clk_parent_data parents[4] = {};
> + struct clk_init_data init = {
> + .name = jh7110_sysclk_data[idx].name,
> + .ops = starfive_jh71x0_clk_ops(max),
> + .parent_data = parents,
> + .num_parents =
> + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + .flags = jh7110_sysclk_data[idx].flags,
> + };
> + struct jh71x0_clk *clk = &priv->reg[idx];
> + unsigned int i;
> +
> + for (i = 0; i < init.num_parents; i++) {
> + unsigned int pidx = jh7110_sysclk_data[idx].parents[i];
> +
> + if (pidx < JH7110_SYSCLK_PLL0_OUT)
> + parents[i].hw = &priv->reg[pidx].hw;
> + else if (pidx < JH7110_SYSCLK_END)
> + parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
> + else if (pidx == JH7110_SYSCLK_OSC)
> + parents[i].fw_name = "osc";
> + else if (pidx == JH7110_SYSCLK_GMAC1_RMII_REFIN)
> + parents[i].fw_name = "gmac1_rmii_refin";
> + else if (pidx == JH7110_SYSCLK_GMAC1_RGMII_RXIN)
> + parents[i].fw_name = "gmac1_rgmii_rxin";
> + else if (pidx == JH7110_SYSCLK_I2STX_BCLK_EXT)
> + parents[i].fw_name = "i2stx_bclk_ext";
> + else if (pidx == JH7110_SYSCLK_I2STX_LRCK_EXT)
> + parents[i].fw_name = "i2stx_lrck_ext";
> + else if (pidx == JH7110_SYSCLK_I2SRX_BCLK_EXT)
> + parents[i].fw_name = "i2srx_bclk_ext";
> + else if (pidx == JH7110_SYSCLK_I2SRX_LRCK_EXT)
> + parents[i].fw_name = "i2srx_lrck_ext";
> + else if (pidx == JH7110_SYSCLK_TDM_EXT)
> + parents[i].fw_name = "tdm_ext";
> + else if (pidx == JH7110_SYSCLK_MCLK_EXT)
> + parents[i].fw_name = "mclk_ext";
> + }
> +
> + clk->hw.init = &init;
> + clk->idx = idx;
> + clk->max_div = max & JH71X0_CLK_DIV_MASK;
> +
> + ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
> + if (ret)
> + return ret;
> + }
> +
> + ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_sysclk_get, priv);
> + if (ret)
> + return ret;
> +
> + return jh7110_reset_controller_register(priv, "reset-sys", 0);
> +}
> +
> +static const struct of_device_id jh7110_syscrg_match[] = {
> + { .compatible = "starfive,jh7110-syscrg" },
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver jh7110_syscrg_driver = {
> + .driver = {
> + .name = "clk-starfive-jh7110-sys",
> + .of_match_table = jh7110_syscrg_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +builtin_platform_driver_probe(jh7110_syscrg_driver, jh7110_syscrg_probe);
> diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c
> index b372083d11c3..a8c60630ae73 100644
> --- a/drivers/clk/starfive/clk-starfive-jh71x0.c
> +++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
> @@ -5,6 +5,7 @@
> * Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
> */
>
> +#include <linux/auxiliary_bus.h>
> #include <linux/clk-provider.h>
> #include <linux/debugfs.h>
> #include <linux/device.h>
> @@ -331,3 +332,52 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
> return &jh71x0_clk_inv_ops;
> }
> EXPORT_SYMBOL_GPL(starfive_jh71x0_clk_ops);
> +
> +#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS)
> +
> +static void jh7110_reset_unregister_adev(void *_adev)
> +{
> + struct auxiliary_device *adev = _adev;
> +
> + auxiliary_device_delete(adev);
> +}
> +
> +static void jh7110_reset_adev_release(struct device *dev)
> +{
> + struct auxiliary_device *adev = to_auxiliary_dev(dev);
> +
> + auxiliary_device_uninit(adev);
> +}
> +
> +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> + const char *adev_name,
> + u32 adev_id)
> +{
> + struct auxiliary_device *adev;
> + int ret;
> +
> + adev = devm_kzalloc(priv->dev, sizeof(*adev), GFP_KERNEL);
> + if (!adev)
> + return -ENOMEM;
> +
> + adev->name = adev_name;
> + adev->dev.parent = priv->dev;
> + adev->dev.release = jh7110_reset_adev_release;
> + adev->id = adev_id;
> +
> + ret = auxiliary_device_init(adev);
> + if (ret)
> + return ret;
> +
> + ret = auxiliary_device_add(adev);
> + if (ret) {
> + auxiliary_device_uninit(adev);
> + return ret;
> + }
> +
> + return devm_add_action_or_reset(priv->dev,
> + jh7110_reset_unregister_adev, adev);
> +}
> +EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
> +
> +#endif
> diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
> index baf4b5cb4b8a..0cbf9d94257a 100644
> --- a/drivers/clk/starfive/clk-starfive-jh71x0.h
> +++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
> @@ -111,4 +111,12 @@ struct jh71x0_clk_priv {
>
> const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
>
> +#if IS_ENABLED(CONFIG_CLK_STARFIVE_JH7110_SYS)
> +
> +int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
> + const char *adev_name,
> + u32 adev_id);
> +
> +#endif
> +
> #endif
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
2023-02-21 2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
@ 2023-02-26 17:34 ` Emil Renner Berthing
2023-02-28 2:42 ` Hal Feng
0 siblings, 1 reply; 71+ messages in thread
From: Emil Renner Berthing @ 2023-02-26 17:34 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add driver for the StarFive JH7110 always-on clock controller
> and register an auxiliary device for always-on reset controller
> which is named as "reset-aon".
>
> Reported-by: kernel test robot <lkp@intel.com>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> ---
> drivers/clk/starfive/Kconfig | 11 ++
> drivers/clk/starfive/Makefile | 1 +
> .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++++++++++++++++
> 3 files changed, 168 insertions(+)
> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
>
> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> index 4640d0665d1c..2aa664f2cdee 100644
> --- a/drivers/clk/starfive/Kconfig
> +++ b/drivers/clk/starfive/Kconfig
> @@ -31,3 +31,14 @@ config CLK_STARFIVE_JH7110_SYS
> help
> Say yes here to support the system clock controller on the
> StarFive JH7110 SoC.
> +
> +config CLK_STARFIVE_JH7110_AON
> + tristate "StarFive JH7110 always-on clock support"
> + depends on CLK_STARFIVE_JH7110_SYS
> + select AUXILIARY_BUS
> + select CLK_STARFIVE_JH71X0
> + select RESET_STARFIVE_JH7110
> + default CLK_STARFIVE_JH7110_SYS
As far as I can tell the JH7110 boots fine without this driver and it
already depends on the _SYS driver above, so please do
default m if SOC_STARFIVE
And consider helping Conor by changing all the SOC_STARFIVE instances
to ARCH_STARFIVE for the next version.
> + help
> + Say yes here to support the always-on clock controller on the
> + StarFive JH7110 SoC.
> diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
> index 5ca4e887fb9c..f3df7d957b1e 100644
> --- a/drivers/clk/starfive/Makefile
> +++ b/drivers/clk/starfive/Makefile
> @@ -5,3 +5,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
> obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
>
> obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
> +obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
> new file mode 100644
> index 000000000000..da808dc93048
> --- /dev/null
> +++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
> @@ -0,0 +1,156 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * StarFive JH7110 Always-On Clock Driver
> + *
> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
> +
> +#include "clk-starfive-jh71x0.h"
> +
> +/* external clocks */
> +#define JH7110_AONCLK_OSC (JH7110_AONCLK_END + 0)
> +#define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 1)
> +#define JH7110_AONCLK_GMAC0_RMII_REFIN (JH7110_AONCLK_END + 2)
> +#define JH7110_AONCLK_GMAC0_RGMII_RXIN (JH7110_AONCLK_END + 3)
> +#define JH7110_AONCLK_STG_AXIAHB (JH7110_AONCLK_END + 4)
> +#define JH7110_AONCLK_APB_BUS (JH7110_AONCLK_END + 5)
> +#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 6)
> +
> +static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
> + /* source */
> + JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
> + JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
> + JH7110_AONCLK_OSC_DIV4,
> + JH7110_AONCLK_OSC),
> + /* gmac0 */
> + JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
> + JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
> + JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
> + JH7110_AONCLK_GMAC0_RMII_REFIN),
> + JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", 0, 2,
> + JH7110_AONCLK_GMAC0_GTXCLK,
> + JH7110_AONCLK_GMAC0_RMII_RTX),
> + JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
> + JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
> + JH7110_AONCLK_GMAC0_RGMII_RXIN,
> + JH7110_AONCLK_GMAC0_RMII_RTX),
> + JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
> + /* otpc */
> + JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", CLK_IGNORE_UNUSED, JH7110_AONCLK_APB_BUS),
> + /* rtc */
> + JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", CLK_IGNORE_UNUSED, JH7110_AONCLK_APB_BUS),
> + JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
> + JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
> + JH7110_AONCLK_RTC_OSC,
> + JH7110_AONCLK_RTC_INTERNAL),
> + JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
> +};
This list also contains instances of the CLK_IGNORE_UNUSED flag. Again
please go through them and figure out which clocks are critical and
which are fine to turn off when not used.
> +
> +static struct clk_hw *jh7110_aonclk_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct jh71x0_clk_priv *priv = data;
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx < JH7110_AONCLK_END)
> + return &priv->reg[idx].hw;
> +
> + return ERR_PTR(-EINVAL);
> +}
> +
> +static int jh7110_aoncrg_probe(struct platform_device *pdev)
> +{
> + struct jh71x0_clk_priv *priv;
> + unsigned int idx;
> + int ret;
> +
> + priv = devm_kzalloc(&pdev->dev,
> + struct_size(priv, reg, JH7110_AONCLK_END),
> + GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + spin_lock_init(&priv->rmw_lock);
> + priv->dev = &pdev->dev;
> + priv->base = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + dev_set_drvdata(priv->dev, (void *)(&priv->base));
> +
> + for (idx = 0; idx < JH7110_AONCLK_END; idx++) {
> + u32 max = jh7110_aonclk_data[idx].max;
> + struct clk_parent_data parents[4] = {};
> + struct clk_init_data init = {
> + .name = jh7110_aonclk_data[idx].name,
> + .ops = starfive_jh71x0_clk_ops(max),
> + .parent_data = parents,
> + .num_parents =
> + ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
> + .flags = jh7110_aonclk_data[idx].flags,
> + };
> + struct jh71x0_clk *clk = &priv->reg[idx];
> + unsigned int i;
> +
> + for (i = 0; i < init.num_parents; i++) {
> + unsigned int pidx = jh7110_aonclk_data[idx].parents[i];
> +
> + if (pidx < JH7110_AONCLK_END)
> + parents[i].hw = &priv->reg[pidx].hw;
> + else if (pidx == JH7110_AONCLK_OSC)
> + parents[i].fw_name = "osc";
> + else if (pidx == JH7110_AONCLK_RTC_OSC)
> + parents[i].fw_name = "rtc_osc";
> + else if (pidx == JH7110_AONCLK_GMAC0_RMII_REFIN)
> + parents[i].fw_name = "gmac0_rmii_refin";
> + else if (pidx == JH7110_AONCLK_GMAC0_RGMII_RXIN)
> + parents[i].fw_name = "gmac0_rgmii_rxin";
> + else if (pidx == JH7110_AONCLK_STG_AXIAHB)
> + parents[i].fw_name = "stg_axiahb";
> + else if (pidx == JH7110_AONCLK_APB_BUS)
> + parents[i].fw_name = "apb_bus";
> + else if (pidx == JH7110_AONCLK_GMAC0_GTXCLK)
> + parents[i].fw_name = "gmac0_gtxclk";
> + }
> +
> + clk->hw.init = &init;
> + clk->idx = idx;
> + clk->max_div = max & JH71X0_CLK_DIV_MASK;
> +
> + ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
> + if (ret)
> + return ret;
> + }
> +
> + ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_aonclk_get, priv);
> + if (ret)
> + return ret;
> +
> + return jh7110_reset_controller_register(priv, "reset-aon", 1);
> +}
> +
> +static const struct of_device_id jh7110_aoncrg_match[] = {
> + { .compatible = "starfive,jh7110-aoncrg" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, jh7110_aoncrg_match);
> +
> +static struct platform_driver jh7110_aoncrg_driver = {
> + .probe = jh7110_aoncrg_probe,
> + .driver = {
> + .name = "clk-starfive-jh7110-aon",
> + .of_match_table = jh7110_aoncrg_match,
> + },
> +};
> +module_platform_driver(jh7110_aoncrg_driver);
> +
> +MODULE_AUTHOR("Emil Renner Berthing");
> +MODULE_DESCRIPTION("StarFive JH7110 always-on clock driver");
> +MODULE_LICENSE("GPL");
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree
2023-02-23 7:16 ` Hal Feng
@ 2023-02-27 18:10 ` Conor Dooley
0 siblings, 0 replies; 71+ messages in thread
From: Conor Dooley @ 2023-02-27 18:10 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1477 bytes --]
On Thu, Feb 23, 2023 at 03:16:51PM +0800, Hal Feng wrote:
> On Tue, 21 Feb 2023 17:03:52 +0000, Conor Dooley wrote:
> > On Tue, Feb 21, 2023 at 10:46:43AM +0800, Hal Feng wrote:
> >
> >> + S7_0: cpu@0 {
> >> + compatible = "sifive,s7", "riscv";
> >> + reg = <0>;
> >> + d-cache-block-size = <64>;
> >> + d-cache-sets = <64>;
> >> + d-cache-size = <8192>;
> >> + d-tlb-sets = <1>;
> >> + d-tlb-size = <40>;
> >> + device_type = "cpu";
> >> + i-cache-block-size = <64>;
> >> + i-cache-sets = <64>;
> >> + i-cache-size = <16384>;
> >> + i-tlb-sets = <1>;
> >> + i-tlb-size = <40>;
> >> + mmu-type = "riscv,sv39";
> >> + next-level-cache = <&ccache>;
> >> + riscv,isa = "rv64imac_zicsr_zba_zbb";
> >
> > I still think that adding just zicsr here is pointless. If you're going
> > to be specific, why not also mention that you have zifencei too?
>
> I would like to remove "_zicsr" in the next version. Thanks.
>
> >
> >> + tlb-split;
> >> + status = "disabled";
> >> +
> >> + cpu0_intc: interrupt-controller {
> >> + compatible = "riscv,cpu-intc";
> >> + interrupt-controller;
> >> + #interrupt-cells = <1>;
> >> + };
> >> + };
> >
> > Rest of this looks fine to me though, thanks for adding the s7
> > compatible and zba/zbb :)
>
> Thanks for your review. :)
I hadn't actually given you one yet ;)
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-23 8:50 ` Hal Feng
@ 2023-02-27 18:12 ` Conor Dooley
2023-02-27 20:00 ` Conor Dooley
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-02-27 18:12 UTC (permalink / raw)
To: Hal Feng
Cc: Emil Renner Berthing, linux-clk, devicetree, linux-riscv,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3027 bytes --]
On Thu, Feb 23, 2023 at 04:50:20PM +0800, Hal Feng wrote:
> On Tue, 21 Feb 2023 16:03:08 +0100, Emil Renner Berthing wrote:
> > On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
> >> From: Emil Renner Berthing <kernel@esmil.dk>
> >>
> >> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> >> which has version A and version B. Support booting and basic
> >> clock/reset/pinctrl/uart drivers.
> >>
> >> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> >> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> >> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> >> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> >> ---
> >> arch/riscv/boot/dts/starfive/Makefile | 6 +-
> >> .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
> >> .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
> >> .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
> >> 4 files changed, 246 insertions(+), 1 deletion(-)
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
> >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> >>
> >> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> >> index 039c143cba33..cd73519b907b 100644
> >> --- a/arch/riscv/boot/dts/starfive/Makefile
> >> +++ b/arch/riscv/boot/dts/starfive/Makefile
> >> @@ -1,2 +1,6 @@
> >> # SPDX-License-Identifier: GPL-2.0
> >> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
> >> +
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
If you could rebase on top of v6.3-rc1 for the next version & use ARCH_
not SOC_ here that'd be great.
> >> +/ {
> >> + aliases {
> >> + serial0 = &uart0;
> >> + i2c0 = &i2c0;
> >> + i2c2 = &i2c2;
> >> + i2c5 = &i2c5;
> >> + i2c6 = &i2c6;
> >
> > Let's keep these sorted alphabetically.
>
> OK, will fix it.
>
> > It would be great to have some sort of order to this file so it's
> > obvious where to add new nodes. I suggest we do
> > - root node
> > - external clocks
> > - other node references in alphabetical order
> >
> > You're almost there with this patch except the uart0 node is out of place.
>
> Will fix accordingly. Thanks for your suggestions.
With Emil's suggestions implemented:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-27 18:12 ` Conor Dooley
@ 2023-02-27 20:00 ` Conor Dooley
2023-02-28 2:58 ` Hal Feng
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-02-27 20:00 UTC (permalink / raw)
To: Hal Feng
Cc: Emil Renner Berthing, linux-clk, devicetree, linux-riscv,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 3359 bytes --]
On Mon, Feb 27, 2023 at 06:12:40PM +0000, Conor Dooley wrote:
> On Thu, Feb 23, 2023 at 04:50:20PM +0800, Hal Feng wrote:
> > On Tue, 21 Feb 2023 16:03:08 +0100, Emil Renner Berthing wrote:
> > > On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
> > >> From: Emil Renner Berthing <kernel@esmil.dk>
> > >>
> > >> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
> > >> which has version A and version B. Support booting and basic
> > >> clock/reset/pinctrl/uart drivers.
> > >>
> > >> Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> > >> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > >> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
> > >> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> > >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> > >> ---
> > >> arch/riscv/boot/dts/starfive/Makefile | 6 +-
> > >> .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
> > >> .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
> > >> .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
> > >> 4 files changed, 246 insertions(+), 1 deletion(-)
> > >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
> > >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
> > >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > >>
> > >> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
> > >> index 039c143cba33..cd73519b907b 100644
> > >> --- a/arch/riscv/boot/dts/starfive/Makefile
> > >> +++ b/arch/riscv/boot/dts/starfive/Makefile
> > >> @@ -1,2 +1,6 @@
> > >> # SPDX-License-Identifier: GPL-2.0
> > >> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
> > >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
> > >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
> > >> +
> > >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
> > >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
>
> If you could rebase on top of v6.3-rc1 for the next version & use ARCH_
> not SOC_ here that'd be great.
>
> > >> +/ {
> > >> + aliases {
> > >> + serial0 = &uart0;
> > >> + i2c0 = &i2c0;
> > >> + i2c2 = &i2c2;
> > >> + i2c5 = &i2c5;
> > >> + i2c6 = &i2c6;
> > >
> > > Let's keep these sorted alphabetically.
> >
> > OK, will fix it.
> >
>
> > > It would be great to have some sort of order to this file so it's
> > > obvious where to add new nodes. I suggest we do
> > > - root node
> > > - external clocks
> > > - other node references in alphabetical order
> > >
> > > You're almost there with this patch except the uart0 node is out of place.
> >
> > Will fix accordingly. Thanks for your suggestions.
>
> With Emil's suggestions implemented:
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Actually, there's one thing that I don't think was (explicitly?) mentioned,
could you sort the external clocks alphanumerically too?
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver
2023-02-26 16:07 ` Emil Renner Berthing
@ 2023-02-28 2:30 ` Hal Feng
0 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-28 2:30 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Sun, 26 Feb 2023 17:07:04 +0100, Emil Renner Berthing wrote:
> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
>> new file mode 100644
>> index 000000000000..6e230b81a387
>> --- /dev/null
>> +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
>> @@ -0,0 +1,448 @@
[...]
>> +static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
>> + /* root */
>> + JH71X0__MUX(JH7110_SYSCLK_CPU_ROOT, "cpu_root", 2,
>> + JH7110_SYSCLK_OSC,
>> + JH7110_SYSCLK_PLL0_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_CPU_CORE, "cpu_core", 7, JH7110_SYSCLK_CPU_ROOT),
>> + JH71X0__DIV(JH7110_SYSCLK_CPU_BUS, "cpu_bus", 2, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0__MUX(JH7110_SYSCLK_GPU_ROOT, "gpu_root", 2,
>> + JH7110_SYSCLK_PLL2_OUT,
>> + JH7110_SYSCLK_PLL1_OUT),
>> + JH71X0_MDIV(JH7110_SYSCLK_PERH_ROOT, "perh_root", 2, 2,
>> + JH7110_SYSCLK_PLL0_OUT,
>> + JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0__MUX(JH7110_SYSCLK_BUS_ROOT, "bus_root", 2,
>> + JH7110_SYSCLK_OSC,
>> + JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_NOCSTG_BUS, "nocstg_bus", 3, JH7110_SYSCLK_BUS_ROOT),
>> + JH71X0__DIV(JH7110_SYSCLK_AXI_CFG0, "axi_cfg0", 3, JH7110_SYSCLK_BUS_ROOT),
>> + JH71X0__DIV(JH7110_SYSCLK_STG_AXIAHB, "stg_axiahb", 2, JH7110_SYSCLK_AXI_CFG0),
>> + JH71X0_GATE(JH7110_SYSCLK_AHB0, "ahb0", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
>> + JH71X0_GATE(JH7110_SYSCLK_AHB1, "ahb1", CLK_IS_CRITICAL, JH7110_SYSCLK_STG_AXIAHB),
>> + JH71X0__DIV(JH7110_SYSCLK_APB_BUS, "apb_bus", 8, JH7110_SYSCLK_STG_AXIAHB),
>> + JH71X0_GATE(JH7110_SYSCLK_APB0, "apb0", CLK_IS_CRITICAL, JH7110_SYSCLK_APB_BUS),
>> + JH71X0__DIV(JH7110_SYSCLK_PLL0_DIV2, "pll0_div2", 2, JH7110_SYSCLK_PLL0_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV2, "pll1_div2", 2, JH7110_SYSCLK_PLL1_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_PLL2_DIV2, "pll2_div2", 2, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_AUDIO_ROOT, "audio_root", 8, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_MCLK_INNER, "mclk_inner", 64, JH7110_SYSCLK_AUDIO_ROOT),
>> + JH71X0__MUX(JH7110_SYSCLK_MCLK, "mclk", 2,
>> + JH7110_SYSCLK_MCLK_INNER,
>> + JH7110_SYSCLK_MCLK_EXT),
>> + JH71X0_GATE(JH7110_SYSCLK_MCLK_OUT, "mclk_out", 0, JH7110_SYSCLK_MCLK_INNER),
>> + JH71X0_MDIV(JH7110_SYSCLK_ISP_2X, "isp_2x", 8, 2,
>> + JH7110_SYSCLK_PLL2_OUT,
>> + JH7110_SYSCLK_PLL1_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_ISP_AXI, "isp_axi", 4, JH7110_SYSCLK_ISP_2X),
>> + JH71X0_GDIV(JH7110_SYSCLK_GCLK0, "gclk0", 0, 62, JH7110_SYSCLK_PLL0_DIV2),
>> + JH71X0_GDIV(JH7110_SYSCLK_GCLK1, "gclk1", 0, 62, JH7110_SYSCLK_PLL1_DIV2),
>> + JH71X0_GDIV(JH7110_SYSCLK_GCLK2, "gclk2", 0, 62, JH7110_SYSCLK_PLL2_DIV2),
>> + /* cores */
>> + JH71X0_GATE(JH7110_SYSCLK_CORE, "core", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_CORE1, "core1", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_CORE2, "core2", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_CORE3, "core3", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_CORE4, "core4", CLK_IS_CRITICAL, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_DEBUG, "debug", 0, JH7110_SYSCLK_CPU_BUS),
>> + JH71X0__DIV(JH7110_SYSCLK_RTC_TOGGLE, "rtc_toggle", 6, JH7110_SYSCLK_OSC),
>> + JH71X0_GATE(JH7110_SYSCLK_TRACE0, "trace0", 0, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_TRACE1, "trace1", 0, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_TRACE2, "trace2", 0, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_TRACE3, "trace3", 0, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_TRACE4, "trace4", 0, JH7110_SYSCLK_CPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_TRACE_COM, "trace_com", 0, JH7110_SYSCLK_CPU_BUS),
>> + /* noc */
>> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_CPU_AXI, "noc_bus_cpu_axi", CLK_IS_CRITICAL,
>> + JH7110_SYSCLK_CPU_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_AXICFG0_AXI, "noc_bus_axicfg0_axi", CLK_IS_CRITICAL,
>> + JH7110_SYSCLK_AXI_CFG0),
>> + /* ddr */
>> + JH71X0__DIV(JH7110_SYSCLK_OSC_DIV2, "osc_div2", 2, JH7110_SYSCLK_OSC),
>> + JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV4, "pll1_div4", 2, JH7110_SYSCLK_PLL1_DIV2),
>> + JH71X0__DIV(JH7110_SYSCLK_PLL1_DIV8, "pll1_div8", 2, JH7110_SYSCLK_PLL1_DIV4),
>> + JH71X0__MUX(JH7110_SYSCLK_DDR_BUS, "ddr_bus", 4,
>> + JH7110_SYSCLK_OSC_DIV2,
>> + JH7110_SYSCLK_PLL1_DIV2,
>> + JH7110_SYSCLK_PLL1_DIV4,
>> + JH7110_SYSCLK_PLL1_DIV8),
>> + JH71X0_GATE(JH7110_SYSCLK_DDR_AXI, "ddr_axi", CLK_IGNORE_UNUSED, JH7110_SYSCLK_DDR_BUS),
>> + /* gpu */
>> + JH71X0__DIV(JH7110_SYSCLK_GPU_CORE, "gpu_core", 7, JH7110_SYSCLK_GPU_ROOT),
>> + JH71X0_GATE(JH7110_SYSCLK_GPU_CORE_CLK, "gpu_core_clk", 0, JH7110_SYSCLK_GPU_CORE),
>> + JH71X0_GATE(JH7110_SYSCLK_GPU_SYS_CLK, "gpu_sys_clk", 0, JH7110_SYSCLK_ISP_AXI),
>> + JH71X0_GATE(JH7110_SYSCLK_GPU_APB, "gpu_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GDIV(JH7110_SYSCLK_GPU_RTC_TOGGLE, "gpu_rtc_toggle", 0, 12, JH7110_SYSCLK_OSC),
>> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_GPU_AXI, "noc_bus_gpu_axi", 0, JH7110_SYSCLK_GPU_CORE),
>> + /* isp */
>> + JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_CORE, "isp_top_core", 0, JH7110_SYSCLK_ISP_2X),
>> + JH71X0_GATE(JH7110_SYSCLK_ISP_TOP_AXI, "isp_top_axi", 0, JH7110_SYSCLK_ISP_AXI),
>> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_ISP_AXI, "noc_bus_isp_axi", CLK_IS_CRITICAL,
>> + JH7110_SYSCLK_ISP_AXI),
>> + /* hifi4 */
>> + JH71X0__DIV(JH7110_SYSCLK_HIFI4_CORE, "hifi4_core", 15, JH7110_SYSCLK_BUS_ROOT),
>> + JH71X0__DIV(JH7110_SYSCLK_HIFI4_AXI, "hifi4_axi", 2, JH7110_SYSCLK_HIFI4_CORE),
>> + /* axi_cfg1 */
>> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_MAIN, "axi_cfg1_main", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_ISP_AXI),
>> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG1_AHB, "axi_cfg1_ahb", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_AHB0),
>> + /* vout */
>> + JH71X0_GATE(JH7110_SYSCLK_VOUT_SRC, "vout_src", 0, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_VOUT_AXI, "vout_axi", 7, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_DISP_AXI, "noc_bus_disp_axi", 0, JH7110_SYSCLK_VOUT_AXI),
>> + JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AHB, "vout_top_ahb", 0, JH7110_SYSCLK_AHB1),
>> + JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_AXI, "vout_top_axi", 0, JH7110_SYSCLK_VOUT_AXI),
>> + JH71X0_GATE(JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK, "vout_top_hdmitx0_mclk", 0,
>> + JH7110_SYSCLK_MCLK),
>> + JH71X0__DIV(JH7110_SYSCLK_VOUT_TOP_MIPIPHY_REF, "vout_top_mipiphy_ref", 2,
>> + JH7110_SYSCLK_OSC),
>> + /* jpegc */
>> + JH71X0__DIV(JH7110_SYSCLK_JPEGC_AXI, "jpegc_axi", 16, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0_GATE(JH7110_SYSCLK_CODAJ12_AXI, "codaj12_axi", 0, JH7110_SYSCLK_JPEGC_AXI),
>> + JH71X0_GDIV(JH7110_SYSCLK_CODAJ12_CORE, "codaj12_core", 0, 16, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0_GATE(JH7110_SYSCLK_CODAJ12_APB, "codaj12_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + /* vdec */
>> + JH71X0__DIV(JH7110_SYSCLK_VDEC_AXI, "vdec_axi", 7, JH7110_SYSCLK_BUS_ROOT),
>> + JH71X0_GATE(JH7110_SYSCLK_WAVE511_AXI, "wave511_axi", 0, JH7110_SYSCLK_VDEC_AXI),
>> + JH71X0_GDIV(JH7110_SYSCLK_WAVE511_BPU, "wave511_bpu", 0, 7, JH7110_SYSCLK_BUS_ROOT),
>> + JH71X0_GDIV(JH7110_SYSCLK_WAVE511_VCE, "wave511_vce", 0, 7, JH7110_SYSCLK_PLL0_OUT),
>> + JH71X0_GATE(JH7110_SYSCLK_WAVE511_APB, "wave511_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_VDEC_JPG, "vdec_jpg", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_JPEGC_AXI),
>> + JH71X0_GATE(JH7110_SYSCLK_VDEC_MAIN, "vdec_main", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_VDEC_AXI),
>> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VDEC_AXI, "noc_bus_vdec_axi", 0, JH7110_SYSCLK_VDEC_AXI),
>> + /* venc */
>> + JH71X0__DIV(JH7110_SYSCLK_VENC_AXI, "venc_axi", 15, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0_GATE(JH7110_SYSCLK_WAVE420L_AXI, "wave420l_axi", 0, JH7110_SYSCLK_VENC_AXI),
>> + JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_BPU, "wave420l_bpu", 0, 15, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0_GDIV(JH7110_SYSCLK_WAVE420L_VCE, "wave420l_vce", 0, 15, JH7110_SYSCLK_PLL2_OUT),
>> + JH71X0_GATE(JH7110_SYSCLK_WAVE420L_APB, "wave420l_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_VENC_AXI, "noc_bus_venc_axi", 0, JH7110_SYSCLK_VENC_AXI),
>> + /* axi_cfg0 */
>> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN_DIV, "axi_cfg0_main_div", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_AHB1),
>> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_MAIN, "axi_cfg0_main", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_AXI_CFG0),
>> + JH71X0_GATE(JH7110_SYSCLK_AXI_CFG0_HIFI4, "axi_cfg0_hifi4", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_HIFI4_AXI),
>> + /* intmem */
>> + JH71X0_GATE(JH7110_SYSCLK_AXIMEM2_AXI, "aximem2_axi", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_AXI_CFG0),
>> + /* qspi */
>> + JH71X0_GATE(JH7110_SYSCLK_QSPI_AHB, "qspi_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB1),
>> + JH71X0_GATE(JH7110_SYSCLK_QSPI_APB, "qspi_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB_BUS),
>> + JH71X0__DIV(JH7110_SYSCLK_QSPI_REF_SRC, "qspi_ref_src", 16, JH7110_SYSCLK_PLL0_OUT),
>> + JH71X0_GMUX(JH7110_SYSCLK_QSPI_REF, "qspi_ref", CLK_IGNORE_UNUSED, 2,
>> + JH7110_SYSCLK_OSC,
>> + JH7110_SYSCLK_QSPI_REF_SRC),
>> + /* sdio */
>> + JH71X0_GATE(JH7110_SYSCLK_SDIO0_AHB, "sdio0_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB0),
>> + JH71X0_GATE(JH7110_SYSCLK_SDIO1_AHB, "sdio1_ahb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_AHB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_SDIO0_SDCARD, "sdio0_sdcard", CLK_IGNORE_UNUSED, 15,
>> + JH7110_SYSCLK_AXI_CFG0),
>> + JH71X0_GDIV(JH7110_SYSCLK_SDIO1_SDCARD, "sdio1_sdcard", CLK_IGNORE_UNUSED, 15,
>> + JH7110_SYSCLK_AXI_CFG0),
>> + /* stg */
>> + JH71X0__DIV(JH7110_SYSCLK_USB_125M, "usb_125m", 15, JH7110_SYSCLK_PLL0_OUT),
>> + JH71X0_GATE(JH7110_SYSCLK_NOC_BUS_STG_AXI, "noc_bus_stg_axi", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_NOCSTG_BUS),
>> + /* gmac1 */
>> + JH71X0_GATE(JH7110_SYSCLK_GMAC1_AHB, "gmac1_ahb", 0, JH7110_SYSCLK_AHB0),
>> + JH71X0_GATE(JH7110_SYSCLK_GMAC1_AXI, "gmac1_axi", 0, JH7110_SYSCLK_STG_AXIAHB),
>> + JH71X0__DIV(JH7110_SYSCLK_GMAC_SRC, "gmac_src", 7, JH7110_SYSCLK_PLL0_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_GMAC1_GTXCLK, "gmac1_gtxclk", 15, JH7110_SYSCLK_PLL0_OUT),
>> + JH71X0__DIV(JH7110_SYSCLK_GMAC1_RMII_RTX, "gmac1_rmii_rtx", 30,
>> + JH7110_SYSCLK_GMAC1_RMII_REFIN),
>> + JH71X0_GDIV(JH7110_SYSCLK_GMAC1_PTP, "gmac1_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
>> + JH71X0__MUX(JH7110_SYSCLK_GMAC1_RX, "gmac1_rx", 2,
>> + JH7110_SYSCLK_GMAC1_RGMII_RXIN,
>> + JH7110_SYSCLK_GMAC1_RMII_RTX),
>> + JH71X0__INV(JH7110_SYSCLK_GMAC1_RX_INV, "gmac1_rx_inv", JH7110_SYSCLK_GMAC1_RX),
>> + JH71X0_GMUX(JH7110_SYSCLK_GMAC1_TX, "gmac1_tx", 0, 2,
>> + JH7110_SYSCLK_GMAC1_GTXCLK,
>> + JH7110_SYSCLK_GMAC1_RMII_RTX),
>> + JH71X0__INV(JH7110_SYSCLK_GMAC1_TX_INV, "gmac1_tx_inv", JH7110_SYSCLK_GMAC1_TX),
>> + JH71X0_GATE(JH7110_SYSCLK_GMAC1_GTXC, "gmac1_gtxc", 0, JH7110_SYSCLK_GMAC1_GTXCLK),
>> + /* gmac0 */
>> + JH71X0_GDIV(JH7110_SYSCLK_GMAC0_GTXCLK, "gmac0_gtxclk", 0, 15, JH7110_SYSCLK_PLL0_OUT),
>> + JH71X0_GDIV(JH7110_SYSCLK_GMAC0_PTP, "gmac0_ptp", 0, 31, JH7110_SYSCLK_GMAC_SRC),
>> + JH71X0_GDIV(JH7110_SYSCLK_GMAC_PHY, "gmac_phy", 0, 31, JH7110_SYSCLK_GMAC_SRC),
>> + JH71X0_GATE(JH7110_SYSCLK_GMAC0_GTXC, "gmac0_gtxc", 0, JH7110_SYSCLK_GMAC0_GTXCLK),
>> + /* apb misc */
>> + JH71X0_GATE(JH7110_SYSCLK_IOMUX_APB, "iomux_apb", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_MAILBOX_APB, "mailbox_apb", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_INT_CTRL_APB, "int_ctrl_apb", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_APB_BUS),
>> + /* can0 */
>> + JH71X0_GATE(JH7110_SYSCLK_CAN0_APB, "can0_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GDIV(JH7110_SYSCLK_CAN0_TIMER, "can0_timer", 0, 24, JH7110_SYSCLK_OSC),
>> + JH71X0_GDIV(JH7110_SYSCLK_CAN0_CAN, "can0_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
>> + /* can1 */
>> + JH71X0_GATE(JH7110_SYSCLK_CAN1_APB, "can1_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GDIV(JH7110_SYSCLK_CAN1_TIMER, "can1_timer", 0, 24, JH7110_SYSCLK_OSC),
>> + JH71X0_GDIV(JH7110_SYSCLK_CAN1_CAN, "can1_can", 0, 63, JH7110_SYSCLK_PERH_ROOT),
>> + /* pwm */
>> + JH71X0_GATE(JH7110_SYSCLK_PWM_APB, "pwm_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + /* wdt */
>> + JH71X0_GATE(JH7110_SYSCLK_WDT_APB, "wdt_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_WDT_CORE, "wdt_core", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
>> + /* timer */
>> + JH71X0_GATE(JH7110_SYSCLK_TIMER_APB, "timer_apb", CLK_IGNORE_UNUSED,
>> + JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_TIMER0, "timer0", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
>> + JH71X0_GATE(JH7110_SYSCLK_TIMER1, "timer1", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
>> + JH71X0_GATE(JH7110_SYSCLK_TIMER2, "timer2", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
>> + JH71X0_GATE(JH7110_SYSCLK_TIMER3, "timer3", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
>> + /* temp sensor */
>> + JH71X0_GATE(JH7110_SYSCLK_TEMP_APB, "temp_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GDIV(JH7110_SYSCLK_TEMP_CORE, "temp_core", 0, 24, JH7110_SYSCLK_OSC),
>> + /* spi */
>> + JH71X0_GATE(JH7110_SYSCLK_SPI0_APB, "spi0_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_SPI1_APB, "spi1_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_SPI2_APB, "spi2_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_SPI3_APB, "spi3_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_SPI4_APB, "spi4_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_SPI5_APB, "spi5_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_SPI6_APB, "spi6_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + /* i2c */
>> + JH71X0_GATE(JH7110_SYSCLK_I2C0_APB, "i2c0_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_I2C1_APB, "i2c1_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_I2C2_APB, "i2c2_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_I2C3_APB, "i2c3_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_I2C4_APB, "i2c4_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_I2C5_APB, "i2c5_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + JH71X0_GATE(JH7110_SYSCLK_I2C6_APB, "i2c6_apb", 0, JH7110_SYSCLK_APB_BUS),
>> + /* uart */
>> + JH71X0_GATE(JH7110_SYSCLK_UART0_APB, "uart0_apb", CLK_IGNORE_UNUSED, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_UART0_CORE, "uart0_core", CLK_IGNORE_UNUSED, JH7110_SYSCLK_OSC),
>> + JH71X0_GATE(JH7110_SYSCLK_UART1_APB, "uart1_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_UART1_CORE, "uart1_core", 0, JH7110_SYSCLK_OSC),
>> + JH71X0_GATE(JH7110_SYSCLK_UART2_APB, "uart2_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_UART2_CORE, "uart2_core", 0, JH7110_SYSCLK_OSC),
>> + JH71X0_GATE(JH7110_SYSCLK_UART3_APB, "uart3_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_UART3_CORE, "uart3_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
>> + JH71X0_GATE(JH7110_SYSCLK_UART4_APB, "uart4_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_UART4_CORE, "uart4_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
>> + JH71X0_GATE(JH7110_SYSCLK_UART5_APB, "uart5_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_UART5_CORE, "uart5_core", 0, 10, JH7110_SYSCLK_PERH_ROOT),
>> + /* pwmdac */
>> + JH71X0_GATE(JH7110_SYSCLK_PWMDAC_APB, "pwmdac_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_PWMDAC_CORE, "pwmdac_core", 0, 256, JH7110_SYSCLK_AUDIO_ROOT),
>> + /* spdif */
>> + JH71X0_GATE(JH7110_SYSCLK_SPDIF_APB, "spdif_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GATE(JH7110_SYSCLK_SPDIF_CORE, "spdif_core", 0, JH7110_SYSCLK_MCLK),
>> + /* i2stx0 */
>> + JH71X0_GATE(JH7110_SYSCLK_I2STX0_APB, "i2stx0_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_I2STX0_BCLK_MST, "i2stx0_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
>> + JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_MST_INV, "i2stx0_bclk_mst_inv",
>> + JH7110_SYSCLK_I2STX0_BCLK_MST),
>> + JH71X0_MDIV(JH7110_SYSCLK_I2STX0_LRCK_MST, "i2stx0_lrck_mst", 64, 2,
>> + JH7110_SYSCLK_I2STX0_BCLK_MST_INV,
>> + JH7110_SYSCLK_I2STX0_BCLK_MST),
>> + JH71X0__MUX(JH7110_SYSCLK_I2STX0_BCLK, "i2stx0_bclk", 2,
>> + JH7110_SYSCLK_I2STX0_BCLK_MST,
>> + JH7110_SYSCLK_I2STX_BCLK_EXT),
>> + JH71X0__INV(JH7110_SYSCLK_I2STX0_BCLK_INV, "i2stx0_bclk_inv", JH7110_SYSCLK_I2STX0_BCLK),
>> + JH71X0__MUX(JH7110_SYSCLK_I2STX0_LRCK, "i2stx0_lrck", 2,
>> + JH7110_SYSCLK_I2STX0_LRCK_MST,
>> + JH7110_SYSCLK_I2STX_LRCK_EXT),
>> + /* i2stx1 */
>> + JH71X0_GATE(JH7110_SYSCLK_I2STX1_APB, "i2stx1_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_I2STX1_BCLK_MST, "i2stx1_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
>> + JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_MST_INV, "i2stx1_bclk_mst_inv",
>> + JH7110_SYSCLK_I2STX1_BCLK_MST),
>> + JH71X0_MDIV(JH7110_SYSCLK_I2STX1_LRCK_MST, "i2stx1_lrck_mst", 64, 2,
>> + JH7110_SYSCLK_I2STX1_BCLK_MST_INV,
>> + JH7110_SYSCLK_I2STX1_BCLK_MST),
>> + JH71X0__MUX(JH7110_SYSCLK_I2STX1_BCLK, "i2stx1_bclk", 2,
>> + JH7110_SYSCLK_I2STX1_BCLK_MST,
>> + JH7110_SYSCLK_I2STX_BCLK_EXT),
>> + JH71X0__INV(JH7110_SYSCLK_I2STX1_BCLK_INV, "i2stx1_bclk_inv", JH7110_SYSCLK_I2STX1_BCLK),
>> + JH71X0__MUX(JH7110_SYSCLK_I2STX1_LRCK, "i2stx1_lrck", 2,
>> + JH7110_SYSCLK_I2STX1_LRCK_MST,
>> + JH7110_SYSCLK_I2STX_LRCK_EXT),
>> + /* i2srx */
>> + JH71X0_GATE(JH7110_SYSCLK_I2SRX_APB, "i2srx_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_I2SRX_BCLK_MST, "i2srx_bclk_mst", 0, 32, JH7110_SYSCLK_MCLK),
>> + JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_MST_INV, "i2srx_bclk_mst_inv",
>> + JH7110_SYSCLK_I2SRX_BCLK_MST),
>> + JH71X0_MDIV(JH7110_SYSCLK_I2SRX_LRCK_MST, "i2srx_lrck_mst", 64, 2,
>> + JH7110_SYSCLK_I2SRX_BCLK_MST_INV,
>> + JH7110_SYSCLK_I2SRX_BCLK_MST),
>> + JH71X0__MUX(JH7110_SYSCLK_I2SRX_BCLK, "i2srx_bclk", 2,
>> + JH7110_SYSCLK_I2SRX_BCLK_MST,
>> + JH7110_SYSCLK_I2SRX_BCLK_EXT),
>> + JH71X0__INV(JH7110_SYSCLK_I2SRX_BCLK_INV, "i2srx_bclk_inv", JH7110_SYSCLK_I2SRX_BCLK),
>> + JH71X0__MUX(JH7110_SYSCLK_I2SRX_LRCK, "i2srx_lrck", 2,
>> + JH7110_SYSCLK_I2SRX_LRCK_MST,
>> + JH7110_SYSCLK_I2SRX_LRCK_EXT),
>> + /* pdm */
>> + JH71X0_GDIV(JH7110_SYSCLK_PDM_DMIC, "pdm_dmic", 0, 64, JH7110_SYSCLK_MCLK),
>> + JH71X0_GATE(JH7110_SYSCLK_PDM_APB, "pdm_apb", 0, JH7110_SYSCLK_APB0),
>> + /* tdm */
>> + JH71X0_GATE(JH7110_SYSCLK_TDM_AHB, "tdm_ahb", 0, JH7110_SYSCLK_AHB0),
>> + JH71X0_GATE(JH7110_SYSCLK_TDM_APB, "tdm_apb", 0, JH7110_SYSCLK_APB0),
>> + JH71X0_GDIV(JH7110_SYSCLK_TDM_INTERNAL, "tdm_internal", 0, 64, JH7110_SYSCLK_MCLK),
>> + JH71X0__MUX(JH7110_SYSCLK_TDM_TDM, "tdm_tdm", 2,
>> + JH7110_SYSCLK_TDM_INTERNAL,
>> + JH7110_SYSCLK_TDM_EXT),
>> + JH71X0__INV(JH7110_SYSCLK_TDM_TDM_INV, "tdm_tdm_inv", JH7110_SYSCLK_TDM_TDM),
>> + /* jtag */
>> + JH71X0__DIV(JH7110_SYSCLK_JTAG_CERTIFICATION_TRNG, "jtag_certification_trng", 4,
>> + JH7110_SYSCLK_OSC),
>> +};
>
> Hi Hal,
>
> I noticed this list still contains both clocks with the
> CLK_IS_CRITICAL flag and the CLK_IGNORE_UNUSED. I fear I may be source
> of this because I used the CLK_IGNORE_UNUSED as a placeholder until I
> figured out if the clock was critical or not. For the next revision
> could you please go through clocks marked with CLK_IGNORE_UNUSED and
> determine if they're critical or they can be safely turned off when
> not used by any peripheral.
I had synchronized these clock flags with JH7110 SDK before. I will
recheck these again. Thanks.
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
2023-02-26 17:34 ` Emil Renner Berthing
@ 2023-02-28 2:42 ` Hal Feng
2023-03-09 9:43 ` Hal Feng
0 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-02-28 2:42 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Sun, 26 Feb 2023 18:34:52 +0100, Emil Renner Berthing wrote:
> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add driver for the StarFive JH7110 always-on clock controller
>> and register an auxiliary device for always-on reset controller
>> which is named as "reset-aon".
>>
>> Reported-by: kernel test robot <lkp@intel.com>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> drivers/clk/starfive/Kconfig | 11 ++
>> drivers/clk/starfive/Makefile | 1 +
>> .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++++++++++++++++
>> 3 files changed, 168 insertions(+)
>> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
>>
>> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
>> index 4640d0665d1c..2aa664f2cdee 100644
>> --- a/drivers/clk/starfive/Kconfig
>> +++ b/drivers/clk/starfive/Kconfig
>> @@ -31,3 +31,14 @@ config CLK_STARFIVE_JH7110_SYS
>> help
>> Say yes here to support the system clock controller on the
>> StarFive JH7110 SoC.
>> +
>> +config CLK_STARFIVE_JH7110_AON
>> + tristate "StarFive JH7110 always-on clock support"
>> + depends on CLK_STARFIVE_JH7110_SYS
>> + select AUXILIARY_BUS
>> + select CLK_STARFIVE_JH71X0
>> + select RESET_STARFIVE_JH7110
>> + default CLK_STARFIVE_JH7110_SYS
>
> As far as I can tell the JH7110 boots fine without this driver and it
> already depends on the _SYS driver above, so please do
>
> default m if SOC_STARFIVE
OK. Will fix it.
>
> And consider helping Conor by changing all the SOC_STARFIVE instances
> to ARCH_STARFIVE for the next version.
OK, I see. Will use the ARCH_ symbol instead.
>
>> + help
>> + Say yes here to support the always-on clock controller on the
>> + StarFive JH7110 SoC.
>> diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
>> index 5ca4e887fb9c..f3df7d957b1e 100644
>> --- a/drivers/clk/starfive/Makefile
>> +++ b/drivers/clk/starfive/Makefile
>> @@ -5,3 +5,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100) += clk-starfive-jh7100.o
>> obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO) += clk-starfive-jh7100-audio.o
>>
>> obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS) += clk-starfive-jh7110-sys.o
>> +obj-$(CONFIG_CLK_STARFIVE_JH7110_AON) += clk-starfive-jh7110-aon.o
>> diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
>> new file mode 100644
>> index 000000000000..da808dc93048
>> --- /dev/null
>> +++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
>> @@ -0,0 +1,156 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * StarFive JH7110 Always-On Clock Driver
>> + *
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/io.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +
>> +#include "clk-starfive-jh71x0.h"
>> +
>> +/* external clocks */
>> +#define JH7110_AONCLK_OSC (JH7110_AONCLK_END + 0)
>> +#define JH7110_AONCLK_RTC_OSC (JH7110_AONCLK_END + 1)
>> +#define JH7110_AONCLK_GMAC0_RMII_REFIN (JH7110_AONCLK_END + 2)
>> +#define JH7110_AONCLK_GMAC0_RGMII_RXIN (JH7110_AONCLK_END + 3)
>> +#define JH7110_AONCLK_STG_AXIAHB (JH7110_AONCLK_END + 4)
>> +#define JH7110_AONCLK_APB_BUS (JH7110_AONCLK_END + 5)
>> +#define JH7110_AONCLK_GMAC0_GTXCLK (JH7110_AONCLK_END + 6)
>> +
>> +static const struct jh71x0_clk_data jh7110_aonclk_data[] = {
>> + /* source */
>> + JH71X0__DIV(JH7110_AONCLK_OSC_DIV4, "osc_div4", 4, JH7110_AONCLK_OSC),
>> + JH71X0__MUX(JH7110_AONCLK_APB_FUNC, "apb_func", 2,
>> + JH7110_AONCLK_OSC_DIV4,
>> + JH7110_AONCLK_OSC),
>> + /* gmac0 */
>> + JH71X0_GATE(JH7110_AONCLK_GMAC0_AHB, "gmac0_ahb", 0, JH7110_AONCLK_STG_AXIAHB),
>> + JH71X0_GATE(JH7110_AONCLK_GMAC0_AXI, "gmac0_axi", 0, JH7110_AONCLK_STG_AXIAHB),
>> + JH71X0__DIV(JH7110_AONCLK_GMAC0_RMII_RTX, "gmac0_rmii_rtx", 30,
>> + JH7110_AONCLK_GMAC0_RMII_REFIN),
>> + JH71X0_GMUX(JH7110_AONCLK_GMAC0_TX, "gmac0_tx", 0, 2,
>> + JH7110_AONCLK_GMAC0_GTXCLK,
>> + JH7110_AONCLK_GMAC0_RMII_RTX),
>> + JH71X0__INV(JH7110_AONCLK_GMAC0_TX_INV, "gmac0_tx_inv", JH7110_AONCLK_GMAC0_TX),
>> + JH71X0__MUX(JH7110_AONCLK_GMAC0_RX, "gmac0_rx", 2,
>> + JH7110_AONCLK_GMAC0_RGMII_RXIN,
>> + JH7110_AONCLK_GMAC0_RMII_RTX),
>> + JH71X0__INV(JH7110_AONCLK_GMAC0_RX_INV, "gmac0_rx_inv", JH7110_AONCLK_GMAC0_RX),
>> + /* otpc */
>> + JH71X0_GATE(JH7110_AONCLK_OTPC_APB, "otpc_apb", CLK_IGNORE_UNUSED, JH7110_AONCLK_APB_BUS),
>> + /* rtc */
>> + JH71X0_GATE(JH7110_AONCLK_RTC_APB, "rtc_apb", CLK_IGNORE_UNUSED, JH7110_AONCLK_APB_BUS),
>> + JH71X0__DIV(JH7110_AONCLK_RTC_INTERNAL, "rtc_internal", 1022, JH7110_AONCLK_OSC),
>> + JH71X0__MUX(JH7110_AONCLK_RTC_32K, "rtc_32k", 2,
>> + JH7110_AONCLK_RTC_OSC,
>> + JH7110_AONCLK_RTC_INTERNAL),
>> + JH71X0_GATE(JH7110_AONCLK_RTC_CAL, "rtc_cal", 0, JH7110_AONCLK_OSC),
>> +};
>
> This list also contains instances of the CLK_IGNORE_UNUSED flag. Again
> please go through them and figure out which clocks are critical and
> which are fine to turn off when not used.
I had synchronized these clock flags with JH7110 SDK before and I will
recheck these flags. Thanks.
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
2023-02-27 20:00 ` Conor Dooley
@ 2023-02-28 2:58 ` Hal Feng
0 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-02-28 2:58 UTC (permalink / raw)
To: Conor Dooley
Cc: Emil Renner Berthing, linux-clk, devicetree, linux-riscv,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
linux-kernel
On Mon, 27 Feb 2023 20:00:33 +0000, Conor Dooley wrote:
> On Mon, Feb 27, 2023 at 06:12:40PM +0000, Conor Dooley wrote:
>> On Thu, Feb 23, 2023 at 04:50:20PM +0800, Hal Feng wrote:
>> > On Tue, 21 Feb 2023 16:03:08 +0100, Emil Renner Berthing wrote:
>> > > On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>> > >> From: Emil Renner Berthing <kernel@esmil.dk>
>> > >>
>> > >> Add a minimal device tree for StarFive JH7110 VisionFive 2 board
>> > >> which has version A and version B. Support booting and basic
>> > >> clock/reset/pinctrl/uart drivers.
>> > >>
>> > >> Acked-by: Conor Dooley <conor.dooley@microchip.com>
>> > >> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> > >> Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> > >> Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
>> > >> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>> > >> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>> > >> ---
>> > >> arch/riscv/boot/dts/starfive/Makefile | 6 +-
>> > >> .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
>> > >> .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
>> > >> .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
>> > >> 4 files changed, 246 insertions(+), 1 deletion(-)
>> > >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
>> > >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
>> > >> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> > >>
>> > >> diff --git a/arch/riscv/boot/dts/starfive/Makefile b/arch/riscv/boot/dts/starfive/Makefile
>> > >> index 039c143cba33..cd73519b907b 100644
>> > >> --- a/arch/riscv/boot/dts/starfive/Makefile
>> > >> +++ b/arch/riscv/boot/dts/starfive/Makefile
>> > >> @@ -1,2 +1,6 @@
>> > >> # SPDX-License-Identifier: GPL-2.0
>> > >> -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb jh7100-starfive-visionfive-v1.dtb
>> > >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
>> > >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
>> > >> +
>> > >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
>> > >> +dtb-$(CONFIG_SOC_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
>>
>> If you could rebase on top of v6.3-rc1 for the next version & use ARCH_
>> not SOC_ here that'd be great.
I will use the ARCH_ symbol instead and tell the other people from StarFive
to do so.
>>
>> > >> +/ {
>> > >> + aliases {
>> > >> + serial0 = &uart0;
>> > >> + i2c0 = &i2c0;
>> > >> + i2c2 = &i2c2;
>> > >> + i2c5 = &i2c5;
>> > >> + i2c6 = &i2c6;
>> > >
>> > > Let's keep these sorted alphabetically.
>> >
>> > OK, will fix it.
>> >
>>
>> > > It would be great to have some sort of order to this file so it's
>> > > obvious where to add new nodes. I suggest we do
>> > > - root node
>> > > - external clocks
>> > > - other node references in alphabetical order
>> > >
>> > > You're almost there with this patch except the uart0 node is out of place.
>> >
>> > Will fix accordingly. Thanks for your suggestions.
>>
>> With Emil's suggestions implemented:
>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Actually, there's one thing that I don't think was (explicitly?) mentioned,
> could you sort the external clocks alphanumerically too?
OK. I will sort them in the next version. Thanks.
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (19 preceding siblings ...)
2023-02-22 15:00 ` [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC patchwork-bot+linux-riscv
@ 2023-03-03 19:08 ` Tommaso Merciai
2023-03-06 3:29 ` Hal Feng
2023-03-07 8:36 ` Hal Feng
21 siblings, 1 reply; 71+ messages in thread
From: Tommaso Merciai @ 2023-03-03 19:08 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
Hello Hal,
I start to play with jh7110-starfive-visionfive-2-v1.3b I have collect
your series [3]. Now I'm trying to boot the image with the following
cmds:
setenv bootfile vmlinuz;
setenv fileaddr a0000000;
setenv fdtcontroladdr 0xffffffffffffffff;
setenv ipaddr 10.0.0.100;
setenv serverip 10.0.0.1;
setenv kernel_comp_addr_r 0xb0000000;
setenv kernel_comp_size 0x10000000;
tftpboot ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb;
tftpboot ${kernel_addr_r} Image.gz;
run chipa_set_linux;
booti ${kernel_addr_r} - ${fdt_addr_r}
This the result:
Bytes transferred = 109443584 (685fa00 hex)
StarFive # run chipa_set_linux;
StarFive # printenv file
fileaddr filesize
StarFive # printenv filesize
filesize=685fa00
StarFive # booti ${kernel_addr_r} - ${fdt_addr_r}
Uncompressing Kernel Image
## Flattened Device Tree blob at 46000000
Booting using the fdt blob at 0x46000000
Using Device Tree in place at 0000000046000000, end 0000000046005c14
Starting kernel ...
clk u5_dw_i2c_clk_core already disabled
clk u5_dw_i2c_clk_apb already disabled
---------------------------------------------
I'm missing something? Any hints?
Many thanks in advance! :)
Regards,
Tommaso
On Tue, Feb 21, 2023 at 10:46:26AM +0800, Hal Feng wrote:
> This patch series adds basic clock, reset & DT support for StarFive
> JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
> dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
> of VisionFive 2 board and JH7110 SoC.
>
> You can simply review or test the patches at the link [3].
>
> [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/
> [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/
> [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
>
> Changes since v3:
> - Suggested by Conor, Merged clock & reset series and DT series together
> so that they could go via the same tree as the dt-binding headers are
> required by both driver & devicetree.
> - Rebased on tag v6.2.
>
> [Clock & reset]
> Patch 2:
> - Split patch 2 into two. One for renaming file and one for renaming
> variables. (by Conor)
> Patch 4:
> - Split patch 4 into two. One for code movement and one for
> extraction. (by Conor)
> Patch 5 & 9 & 10 & 11:
> - Fixed the issues reported by kernel test robot.
> Patch 9:
> - Set (&priv->base) as driver data instead of (priv->base).
> - Set the frequency of clock PLL0 as 1000MHz for Synchronizing with the
> lastest u-boot setting from StarFive. (by Emil)
> - Used devm_kzalloc() instead of kzalloc() when registering aux device.
> Patch 10:
> - Set (&priv->base) as driver data instead of (priv->base).
> Patch 11:
> - Used (*base) to get the register base address instead of (base).
>
> [Device tree]
> - Dropped patch 1, 4, 5 because they were accepted.
> - Added a new patch to add SiFive S7 compatible. (by Conor)
> - Added a new patch to add JH7110 pin function definitions.
> Patch 6:
> - Changed the label "S76_0" to "S7_0" and used compatible "sifive,s7"
> for core 0.
> - Updated ISA of each cores. (by Conor)
> - Made the node names generic. (by Krzysztof)
> - Added clock-output-names for all external clocks.
> - Added i2c0~6 nodes.
> - Changed the node name "gpio" to "pinctrl". Changed the label "gpio"
> and "gpioa" to "sysgpio" and "aongpio". (by Conor)
> Patch 7:
> - Separated the long lines into more lines in Makefile. (by Conor)
> - Renamed jh7110-starfive-visionfive-2-va.dts and
> jh7110-starfive-visionfive-2-vb.dts to
> jh7110-starfive-visionfive-2-v1.2a.dts and
> jh7110-starfive-visionfive-2-v1.3b.dts.
> Changed the model and compatible to match v1.2A and v1.3B which
> are printed on the silkscreen of VisionFive 2 board. (by Emil)
> - Configured pins for i2c0/2/5/6 and enabled them.
>
> clock & reset v3: https://lore.kernel.org/all/20221220005054.34518-1-hal.feng@starfivetech.com/
> DT v3: https://lore.kernel.org/all/20221220011247.35560-1-hal.feng@starfivetech.com/
>
> Changes since v2:
> [Clock & reset]
> - Rebased on tag v6.1.
> - Added "JH71X0" to the StarFive driver headers in MAINTAINERS.
> - Removed Co-developed-by tag of Hal in patch 1 and patch 4.
> - Changed the commit author from Hal to Emil in patch 2 and patch 5.
> Removed Co-developed-by tag of Emil in patch 2 and patch 5. (by Emil)
> - Improved the coding style of patch 11, 12 and 13.
> - Dropped patch 14. (by Emil)
> Patch 4:
> - Passed the "owner" member of reset_controller_dev structure
> directly in reset_starfive_jh7100_register(). (by Emil)
> - Added MAINTAINERS changes.
> Patch 7:
> - Split patch 7 into sys part and aon part. Merged them into patch 9 and
> patch 10 respectively. (by Krzysztof)
> - Renamed include/dt-bindings/clock/starfive-jh7110.h to
> include/dt-bindings/clock/starfive,jh7110-crg.h. (by Krzysztof)
> - Synchronized the definitions with the latest changes from Emil.
> Patch 8:
> - Split patch 8 into sys part and aon part. Merged them into patch 9 and
> patch 10 respectively. (by Krzysztof)
> - Renamed include/dt-bindings/reset/starfive-jh7110.h to
> include/dt-bindings/reset/starfive,jh7110-crg.h. (by Krzysztof)
> - Fixed the date of Copyright. (by Emil)
> - Dropped weird indentations. (by Krzysztof)
> - Synchronized the definitions with the latest changes from Emil.
> Patch 9:
> - Improved the description of clocks. (by Emil and Krzysztof)
> - Added MAINTAINERS changes.
> Patch 10:
> - Improved the description of clocks. (by Emil and Krzysztof)
> - Changed the clock-name "clk_rtc" to "rtc_osc" and "apb_bus_func" to
> "apb_bus".
> Patch 11:
> - Removed the flags of trace/debug clocks and set the flags of core clocks
> as CLK_IS_CRITICAL. (by Emil)
> - Deleted the extra 1-1 clocks and synchronized the clock tree with the
> latest changes from Emil. (by Emil)
> - Selected RESET_STARFIVE_JH7110 in Kconfig option CLK_STARFIVE_JH7110_SYS.
> Patch 12:
> - Changed the macro JH7110_AONCLK_RTC to JH7110_AONCLK_RTC_OSC and
> JH7110_AONCLK_APB_BUS_FUNC to JH7110_AONCLK_APB_BUS.
> - Synchronized the clock tree with the latest changes from Emil.
> - Set the MODULE_LICENSE as "GPL" according to commit bf7fbeeae6db.
> Patch 13:
> - Removed the "asserted" member in reset_info structure and always pass
> NULL when calling reset_starfive_jh71x0_register(). (by Emil)
>
> [Device tree]
> - Rebased on tag v6.1.
> - Dropped patch 8 because it was merged.
> Patch 1:
> - Made the links into "Link:" tags. (by Conor)
> - Corrected the board name to "VisionFive 2" instead of
> "VisionFive V2" and added compatibles for version A and
> version B of VisionFive 2. (by Emil)
> Patch 4:
> - Used "sifive,ccache0" compatible string to match. (by Conor)
> Patch 5:
> - Dropped "select SIFIVE_CCACHE" in config SOC_STARFIVE. (by Conor)
> - Dropped "starfive,jh7110-ccache" compatible in
> drivers/soc/sifive/sifive_ccache.c.
> Patch 6:
> - Removed all "clock-frequency = <0>". (by Conor)
> - Sorted the nodes after their addresses. (by Emil)
> - Renamed "clk_rtc" to "rtc_osc".
> - Added "sifive,ccache0" compatible in the cache-controller node.
> - Renamed "JH7110_SYSCLK_APB_BUS_FUNC" to "JH7110_SYSCLK_APB_BUS" and
> renamed "apb_bus_func" to "apb_bus".
> Renamed "JH7110_SYSCLK_IOMUX" to "JH7110_SYSCLK_IOMUX_APB".
> Renamed "JH7110_SYSRST_IOMUX" to "JH7110_SYSRST_IOMUX_APB".
> Renamed "JH7110_AONRST_AON_IOMUX" to "JH7110_AONRST_IOMUX".
> - Removed "reg-names" in gpio nodes.
> Patch 7:
> - Corrected the board name to "VisionFive 2" instead of "VisionFive V2".
> - Renamed jh7110-starfive-visionfive-v2.dts to
> jh7110-starfive-visionfive-2.dtsi.
> - Added dts for VisionFive 2 version A and version B boards.
> - In the chosen node, deleted "linux,initrd-start" and "linux,initrd-end"
> and changed the value of "stdout-path" to "serial0:115200n8".
> - Changed the bias of uart0 "rx-pins" to
> "bias-disable; /* external pull-up */".
> - Renamed "clk_rtc" to "rtc_osc".
> - Moved the gpio node behind the uart0 node.
>
> clock & reset v2: https://lore.kernel.org/all/20221118010627.70576-1-hal.feng@starfivetech.com/
> DT v2: https://lore.kernel.org/all/20221118011714.70877-1-hal.feng@starfivetech.com/
>
> Changes since v1:
> [Clock & reset]
> - Rebased on tag v6.1-rc5.
> - Rewrote the clock and reset drivers using auxiliary bus framework, so
> patch 8, 9, 15 were dropped and all patches changed a lot. (by Stephen)
> - Split Patch 14 into two patches. One is for factoring out the common
> JH71X0 code, the another one is for renaming. (by Stephen)
> - Created a subdirectory for StarFive reset drivers.
> - Factored out common JH71X0 reset code.
> - Renamed the common clock and reset code from "*starfive*" or
> "*STARFIVE*" to "*jh71x0*" or "*JH71X0*".
> - Combined JH7110 system and always-on clock DT binding headers in one
> file named "include/dt-bindings/clock/starfive-jh7110.h".
> - Renamed clock definitions "JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK" and
> "JH7110_SYSCLK_U2_PCLK_MUX_PCLK" to "JH7110_SYSCLK_PCLK2_MUX_FUNC" and
> "JH7110_SYSCLK_PCLK2_MUX".
> - Rewrote the DT bindings of clock and reset for using auxiliary bus.
> - Registered an auxiliary device for reset controller in clock drivers.
> - Changed clock names "CODAJ*" and "WAVE*" to "codaj*" and "wave*".
> Changed clock names "u2_pclk_mux_func_pclk" and "u2_pclk_mux_pclk" to
> "pclk2_mux_func" and "pclk2_mux".
> - Changed the flags of clock apb0 and noc_bus_isp_axi to CLK_IS_CRITICAL
> as suggested by StarFive SDK group.
> - Registered clock gmac0_gtxc as a gate clock instead of a div clock
> as suggested by StarFive SDK group.
> - Changed the frequency of clock pll2_out to 1188MHz as suggested by
> StarFive SDK group.
> - Fixed the bug that the clock JH7110_AONCLK_GMAC0_GTXCLK was not handled
> in JH7110 always-on clock driver.
> - Registered the reset driver as an auxiliary driver.
> - Reworded the commit messages.
>
> [Device tree]
> - Rebased on tag v6.1-rc5.
> - Added blank line in patch 1. (by Krzysztof)
> - Rebased patch 4 and 6 on the newest code. (by Conor)
> - Dropped patch 5. (by Conor)
> - Removed the quirk of JH7100 in patch 6, considering this patch series
> should only add support for JH7110.
> - For patch 27, added Co-developed-by tag for Jianlong and me. Renamed
> cpu labels to "S76_0", "U74_*" instead of "cpu*" following the style
> of jh7100.dtsi. Moved all "clock-frequency" properties to the board dts.
> Rewrote clock-controller nodes and deleted reset-controller nodes for
> using auxiliary bus. Rewrote gpio nodes following generic pinctrl
> bindings. Removed the redundant second reset entry of uart nodes.
> - For patch 28, added Co-developed-by tag for Jianlong and me. Added a
> chosen node. Removed reserved-memory node. Added fixed frequency clock
> nodes for overriding the "clock-frequency" properties. Rewrote the gpio
> nodes following generic pinctrl bindings.
> - Dropped patch 30. (by Conor)
> - Reworded the commit messages.
>
> v1: https://lore.kernel.org/all/20220929143225.17907-1-hal.feng@linux.starfivetech.com/
>
> Emil Renner Berthing (16):
> clk: starfive: Factor out common JH7100 and JH7110 code
> clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
> clk: starfive: Rename "jh7100" to "jh71x0" for the common code
> reset: Create subdirectory for StarFive drivers
> reset: starfive: Factor out common JH71X0 reset code
> reset: starfive: Extract the common JH71X0 reset code
> reset: starfive: Rename "jh7100" to "jh71x0" for the common code
> reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
> dt-bindings: clock: Add StarFive JH7110 system clock and reset
> generator
> dt-bindings: clock: Add StarFive JH7110 always-on clock and reset
> generator
> clk: starfive: Add StarFive JH7110 system clock driver
> clk: starfive: Add StarFive JH7110 always-on clock driver
> dt-bindings: timer: Add StarFive JH7110 clint
> dt-bindings: interrupt-controller: Add StarFive JH7110 plic
> riscv: dts: starfive: Add initial StarFive JH7110 device tree
> riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device
> tree
>
> Hal Feng (2):
> reset: starfive: Add StarFive JH7110 reset driver
> dt-bindings: riscv: Add SiFive S7 compatible
>
> Jianlong Huang (1):
> riscv: dts: starfive: Add StarFive JH7110 pin function definitions
>
> .../clock/starfive,jh7110-aoncrg.yaml | 76 ++
> .../clock/starfive,jh7110-syscrg.yaml | 80 ++
> .../sifive,plic-1.0.0.yaml | 1 +
> .../devicetree/bindings/riscv/cpus.yaml | 1 +
> .../bindings/timer/sifive,clint.yaml | 1 +
> MAINTAINERS | 16 +-
> arch/riscv/boot/dts/starfive/Makefile | 6 +-
> arch/riscv/boot/dts/starfive/jh7110-pinfunc.h | 308 ++++++++
> .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 +
> .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 +
> .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 507 +++++++++++++
> drivers/clk/starfive/Kconfig | 27 +
> drivers/clk/starfive/Makefile | 6 +-
> .../clk/starfive/clk-starfive-jh7100-audio.c | 74 +-
> drivers/clk/starfive/clk-starfive-jh7100.c | 713 +++++-------------
> drivers/clk/starfive/clk-starfive-jh7100.h | 112 ---
> .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++
> .../clk/starfive/clk-starfive-jh7110-sys.c | 448 +++++++++++
> drivers/clk/starfive/clk-starfive-jh71x0.c | 383 ++++++++++
> drivers/clk/starfive/clk-starfive-jh71x0.h | 122 +++
> drivers/reset/Kconfig | 8 +-
> drivers/reset/Makefile | 2 +-
> drivers/reset/reset-starfive-jh7100.c | 173 -----
> drivers/reset/starfive/Kconfig | 20 +
> drivers/reset/starfive/Makefile | 5 +
> .../reset/starfive/reset-starfive-jh7100.c | 74 ++
> .../reset/starfive/reset-starfive-jh7110.c | 64 ++
> .../reset/starfive/reset-starfive-jh71x0.c | 131 ++++
> .../reset/starfive/reset-starfive-jh71x0.h | 20 +
> .../dt-bindings/clock/starfive,jh7110-crg.h | 225 ++++++
> .../dt-bindings/reset/starfive,jh7110-crg.h | 154 ++++
> 32 files changed, 3296 insertions(+), 858 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
> create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-pinfunc.h
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
> delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
> create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
> create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
> delete mode 100644 drivers/reset/reset-starfive-jh7100.c
> create mode 100644 drivers/reset/starfive/Kconfig
> create mode 100644 drivers/reset/starfive/Makefile
> create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.c
> create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
> create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c
> create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
> create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
> create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h
>
>
> base-commit: c9c3395d5e3dcc6daee66c6908354d47bf98cb0c
> --
> 2.38.1
>
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-03 19:08 ` Tommaso Merciai
@ 2023-03-06 3:29 ` Hal Feng
2023-03-06 10:22 ` Tommaso Merciai
0 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-03-06 3:29 UTC (permalink / raw)
To: Tommaso Merciai
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
On Fri, 3 Mar 2023 20:08:20 +0100, Tommaso Merciai wrote:
> Hello Hal,
> I start to play with jh7110-starfive-visionfive-2-v1.3b I have collect
> your series [3]. Now I'm trying to boot the image with the following
> cmds:
>
> setenv bootfile vmlinuz;
> setenv fileaddr a0000000;
> setenv fdtcontroladdr 0xffffffffffffffff;
> setenv ipaddr 10.0.0.100;
> setenv serverip 10.0.0.1;
> setenv kernel_comp_addr_r 0xb0000000;
> setenv kernel_comp_size 0x10000000;
> tftpboot ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb;
> tftpboot ${kernel_addr_r} Image.gz;
> run chipa_set_linux;
> booti ${kernel_addr_r} - ${fdt_addr_r}
>
>
> This the result:
>
> Bytes transferred = 109443584 (685fa00 hex)
> StarFive # run chipa_set_linux;
> StarFive # printenv file
> fileaddr filesize
> StarFive # printenv filesize
> filesize=685fa00
> StarFive # booti ${kernel_addr_r} - ${fdt_addr_r}
> Uncompressing Kernel Image
> ## Flattened Device Tree blob at 46000000
> Booting using the fdt blob at 0x46000000
> Using Device Tree in place at 0000000046000000, end 0000000046005c14
>
> Starting kernel ...
>
> clk u5_dw_i2c_clk_core already disabled
> clk u5_dw_i2c_clk_apb already disabled
>
> ---------------------------------------------
>
> I'm missing something? Any hints?
> Many thanks in advance! :)
You can try the instructions at the link [1]. The branch [1] is
based on v2 of this series, so you need to change the dtb name
to "jh7110-starfive-visionfive-2-v1.3b.dtb" when using tftpboot.
I will send v5 and update it to [1] this week.
[1] https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_upstream
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-06 3:29 ` Hal Feng
@ 2023-03-06 10:22 ` Tommaso Merciai
0 siblings, 0 replies; 71+ messages in thread
From: Tommaso Merciai @ 2023-03-06 10:22 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, Emil Renner Berthing, linux-kernel
Hi Hal,
On Mon, Mar 06, 2023 at 11:29:48AM +0800, Hal Feng wrote:
> On Fri, 3 Mar 2023 20:08:20 +0100, Tommaso Merciai wrote:
> > Hello Hal,
> > I start to play with jh7110-starfive-visionfive-2-v1.3b I have collect
> > your series [3]. Now I'm trying to boot the image with the following
> > cmds:
> >
> > setenv bootfile vmlinuz;
> > setenv fileaddr a0000000;
> > setenv fdtcontroladdr 0xffffffffffffffff;
> > setenv ipaddr 10.0.0.100;
> > setenv serverip 10.0.0.1;
> > setenv kernel_comp_addr_r 0xb0000000;
> > setenv kernel_comp_size 0x10000000;
> > tftpboot ${fdt_addr_r} jh7110-starfive-visionfive-2-v1.3b.dtb;
> > tftpboot ${kernel_addr_r} Image.gz;
> > run chipa_set_linux;
> > booti ${kernel_addr_r} - ${fdt_addr_r}
> >
> >
> > This the result:
> >
> > Bytes transferred = 109443584 (685fa00 hex)
> > StarFive # run chipa_set_linux;
> > StarFive # printenv file
> > fileaddr filesize
> > StarFive # printenv filesize
> > filesize=685fa00
> > StarFive # booti ${kernel_addr_r} - ${fdt_addr_r}
> > Uncompressing Kernel Image
> > ## Flattened Device Tree blob at 46000000
> > Booting using the fdt blob at 0x46000000
> > Using Device Tree in place at 0000000046000000, end 0000000046005c14
> >
> > Starting kernel ...
> >
> > clk u5_dw_i2c_clk_core already disabled
> > clk u5_dw_i2c_clk_apb already disabled
> >
> > ---------------------------------------------
> >
> > I'm missing something? Any hints?
> > Many thanks in advance! :)
>
> You can try the instructions at the link [1]. The branch [1] is
> based on v2 of this series, so you need to change the dtb name
> to "jh7110-starfive-visionfive-2-v1.3b.dtb" when using tftpboot.
> I will send v5 and update it to [1] this week.
>
> [1] https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_upstream
Thanks for your help!
Collecting your latest 26 patches from [1] I'm able to boot the board
using cmds suggested in your link [2].
In particular I pick the following patches from your repo:
11934a315b67 (HEAD -> visionfive2-minimal, tag: visionfive2-minimal-v4, origin/visionfive2-minimal) riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree
c246291ed2d0 riscv: dts: starfive: Add StarFive JH7110 pin function definitions
53c360e87ee8 riscv: dts: starfive: Add initial StarFive JH7110 device tree
e769528b7cd8 dt-bindings: riscv: Add SiFive S7 compatible
1f4c7408d02a soc: sifive: ccache: Add StarFive JH7110 support
cd1a430b56db dt-bindings: sifive,ccache0: Support StarFive JH7110 SoC
96fcf2e390d3 dt-bindings: interrupt-controller: Add StarFive JH7110 plic
542c43452e08 dt-bindings: timer: Add StarFive JH7110 clint
2b1bb27b0cff dt-bindings: riscv: Add StarFive JH7110 SoC and VisionFive 2 board
328cac9205d2 pinctrl: starfive: Add StarFive JH7110 aon controller driver
dd082f89c4fb pinctrl: starfive: Add StarFive JH7110 sys controller driver
aabf6ba76b81 dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
f2c5025c54f9 dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
7601624bdde0 reset: starfive: Add StarFive JH7110 reset driver
b1a2db0b97f4 clk: starfive: Add StarFive JH7110 always-on clock driver
0b2aaa26d5c8 clk: starfive: Add StarFive JH7110 system clock driver
2959b29a7d80 dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
cfb65ad0957a dt-bindings: clock: Add StarFive JH7110 system clock and reset generator
f9df80901f49 reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
c9400fc69d3a reset: starfive: Rename "jh7100" to "jh71x0" for the common code
8f05fdea85cd reset: starfive: Extract the common JH71X0 reset code
28f5efaa3b06 reset: starfive: Factor out common JH71X0 reset code
aa82ce33f593 reset: Create subdirectory for StarFive drivers
fb87b93f6aa8 clk: starfive: Rename "jh7100" to "jh71x0" for the common code
d73e36277d5f clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h
04611bf6db16 clk: starfive: Factor out common JH7100 and JH7110 code
Hope this can help other peoples that start to play with
jh7110-starfive-visionfive-2-v1.3b :)
Thanks for your work!
Regards,
Tommaso
[1] https://github.com/hal-feng/linux/commits/visionfive2-minimal
[2] https://github.com/starfive-tech/linux/tree/JH7110_VisionFive2_upstream
>
> Best regards,
> Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
` (20 preceding siblings ...)
2023-03-03 19:08 ` Tommaso Merciai
@ 2023-03-07 8:36 ` Hal Feng
2023-03-07 8:51 ` Conor Dooley
21 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-03-07 8:36 UTC (permalink / raw)
To: Conor Dooley, linux-riscv, devicetree, linux-clk
Cc: Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
On Tue, 21 Feb 2023 10:46:26 +0800, Hal Feng wrote:
> This patch series adds basic clock, reset & DT support for StarFive
> JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
> dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
> of VisionFive 2 board and JH7110 SoC.
>
> You can simply review or test the patches at the link [3].
>
> [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/
> [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/
> [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
Hi Conor,
When I tried to rebase these patches on v6.3-rc1, I found the kernel
would crash on the VisionFive 2 board during startup. The logs are as
below. I checkout the branch to the mainline and found that the kernel
would also crash on the VisionFive board which is equipped with JH7100
SoC.
--------------------------------
Unable to handle kernel paging request at virtual address 0000004cccccccd4
Oops [#1]
Modules linked in:
CPU: 3 PID: 87 Comm: udevd Not tainted 6.3.0-rc1-00019-g239e7809f291 #305
Hardware name: StarFive VisionFive 2 v1.3B (DT)
epc : enqueue_timer+0x18/0x90
ra : internal_add_timer+0x2c/0x38
epc : ffffffff8006a714 ra : ffffffff8006a7b8 sp : ffffffc80443bc80
gp : ffffffff80eb5100 tp : ffffffd8c01db200 t0 : 0000000000000000
t1 : 000000000000000f t2 : 0000000038b3ea28 s0 : ffffffc80443bcb0
s1 : ffffffff80813940 a0 : ffffffff80813940 a1 : ffffffc80443bd48
a2 : 000000000000020b a3 : cccccccd0b000000 a4 : cccccccccccccccc
a5 : 000000000000020b a6 : ffffffff80814a08 a7 : 0000000000000001
s2 : ffffffc80443bd48 s3 : 0000000008400040 s4 : ffffffff80813940
s5 : ffffffff80eea0b8 s6 : ffffffff80eb7220 s7 : 0000000000000040
s8 : ffffffff80eb61e0 s9 : 0000002ac84a2548 s10: 0000002ad53e92c0
s11: 0000000000000001 t3 : 000000000000003f t4 : 0000000000000000
t5 : 0000000000000004 t6 : 0000000000000003
status: 0000000200000100 badaddr: 0000004cccccccd4 cause: 000000000000000f
[<ffffffff8006a714>] enqueue_timer+0x18/0x90
[<ffffffff8006aa64>] add_timer_on+0xf0/0x134
[<ffffffff80500f18>] try_to_generate_entropy+0x1ec/0x232
[<ffffffff8035a636>] urandom_read_iter+0x42/0xc2
[<ffffffff800fff16>] vfs_read+0x17c/0x1e4
[<ffffffff801005b6>] ksys_read+0x78/0x98
[<ffffffff801005e4>] sys_read+0xe/0x16
[<ffffffff800035dc>] ret_from_syscall+0x0/0x2
Code: 9381 9713 0037 0813 0705 983a 3703 0008 e198 c311 (e70c) d713
---[ end trace 0000000000000000 ]---
note: udevd[87] exited with irqs disabled
Segmentation fault
FAIL
Saving random seed:
rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=7474
rcu: (detected by 2, t=15005 jiffies, g=-195, q=35 ncpus=4)
Task dump for CPU 1:
task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008
Call Trace:
[<ffffffff80003764>] ret_from_fork+0x0/0xc
rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=29814
rcu: (detected by 2, t=60018 jiffies, g=-195, q=35 ncpus=4)
Task dump for CPU 1:
task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008
Call Trace:
[<ffffffff80003764>] ret_from_fork+0x0/0xc
...
--------------------------------
I used 'git bisect' and found out the commit 9493e6f3ce02 is the
cause. I tried to revert this commit on the tag v6.3-rc1, but it
seems there is no improvement.
Any options I am missing? Could you please give me some suggestions
to adapt to the new changes between 6.2 and 6.3? Thank you in
advance.
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-07 8:36 ` Hal Feng
@ 2023-03-07 8:51 ` Conor Dooley
2023-03-07 10:08 ` Hal Feng
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-03-07 8:51 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, linux-riscv, devicetree, linux-clk, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 4519 bytes --]
On Tue, Mar 07, 2023 at 04:36:41PM +0800, Hal Feng wrote:
> On Tue, 21 Feb 2023 10:46:26 +0800, Hal Feng wrote:
> > This patch series adds basic clock, reset & DT support for StarFive
> > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
> > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
> > of VisionFive 2 board and JH7110 SoC.
> >
> > You can simply review or test the patches at the link [3].
> >
> > [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/
> > [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/
> > [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
>
> Hi Conor,
>
> When I tried to rebase these patches on v6.3-rc1, I found the kernel
> would crash on the VisionFive 2 board during startup. The logs are as
> below. I checkout the branch to the mainline and found that the kernel
> would also crash on the VisionFive board which is equipped with JH7100
> SoC.
>
> --------------------------------
> Unable to handle kernel paging request at virtual address 0000004cccccccd4
> Oops [#1]
> Modules linked in:
> CPU: 3 PID: 87 Comm: udevd Not tainted 6.3.0-rc1-00019-g239e7809f291 #305
> Hardware name: StarFive VisionFive 2 v1.3B (DT)
> epc : enqueue_timer+0x18/0x90
> ra : internal_add_timer+0x2c/0x38
> epc : ffffffff8006a714 ra : ffffffff8006a7b8 sp : ffffffc80443bc80
> gp : ffffffff80eb5100 tp : ffffffd8c01db200 t0 : 0000000000000000
> t1 : 000000000000000f t2 : 0000000038b3ea28 s0 : ffffffc80443bcb0
> s1 : ffffffff80813940 a0 : ffffffff80813940 a1 : ffffffc80443bd48
> a2 : 000000000000020b a3 : cccccccd0b000000 a4 : cccccccccccccccc
> a5 : 000000000000020b a6 : ffffffff80814a08 a7 : 0000000000000001
> s2 : ffffffc80443bd48 s3 : 0000000008400040 s4 : ffffffff80813940
> s5 : ffffffff80eea0b8 s6 : ffffffff80eb7220 s7 : 0000000000000040
> s8 : ffffffff80eb61e0 s9 : 0000002ac84a2548 s10: 0000002ad53e92c0
> s11: 0000000000000001 t3 : 000000000000003f t4 : 0000000000000000
> t5 : 0000000000000004 t6 : 0000000000000003
> status: 0000000200000100 badaddr: 0000004cccccccd4 cause: 000000000000000f
> [<ffffffff8006a714>] enqueue_timer+0x18/0x90
> [<ffffffff8006aa64>] add_timer_on+0xf0/0x134
> [<ffffffff80500f18>] try_to_generate_entropy+0x1ec/0x232
> [<ffffffff8035a636>] urandom_read_iter+0x42/0xc2
> [<ffffffff800fff16>] vfs_read+0x17c/0x1e4
> [<ffffffff801005b6>] ksys_read+0x78/0x98
> [<ffffffff801005e4>] sys_read+0xe/0x16
> [<ffffffff800035dc>] ret_from_syscall+0x0/0x2
> Code: 9381 9713 0037 0813 0705 983a 3703 0008 e198 c311 (e70c) d713
> ---[ end trace 0000000000000000 ]---
> note: udevd[87] exited with irqs disabled
> Segmentation fault
> FAIL
> Saving random seed:
> rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=7474
> rcu: (detected by 2, t=15005 jiffies, g=-195, q=35 ncpus=4)
> Task dump for CPU 1:
> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008
> Call Trace:
> [<ffffffff80003764>] ret_from_fork+0x0/0xc
> rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=29814
> rcu: (detected by 2, t=60018 jiffies, g=-195, q=35 ncpus=4)
> Task dump for CPU 1:
> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008
> Call Trace:
> [<ffffffff80003764>] ret_from_fork+0x0/0xc
> ...
> --------------------------------
>
> I used 'git bisect' and found out the commit 9493e6f3ce02 is the
> cause. I tried to revert this commit on the tag v6.3-rc1, but it
> seems there is no improvement.
Hmm, I'm not entirely sure that that is a good bisect.
This is a fix for my stupidity in the commit you mention:
https://lore.kernel.org/linux-riscv/20230302174154.970746-1-conor@kernel.org/
But the main backtrace there is not from that patch at all, I think it
is Linus' fault.
The HEAD of Linus' tree is currently 8ca09d5fa3549 ("cpumask: fix
incorrect cpumask scanning result checks") should be a fix for the
backtrace that you are seeing above.
> Any options I am missing? Could you please give me some suggestions
> to adapt to the new changes between 6.2 and 6.3? Thank you in
> advance.
LMK if the above two things don't fix it for you & I'll go digging
tonight.
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-07 8:51 ` Conor Dooley
@ 2023-03-07 10:08 ` Hal Feng
2023-03-08 12:28 ` Tommaso Merciai
0 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-03-07 10:08 UTC (permalink / raw)
To: Conor Dooley
Cc: Conor Dooley, linux-riscv, devicetree, linux-clk, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
On Tue, 7 Mar 2023 08:51:49 +0000, Conor Dooley wrote:
> On Tue, Mar 07, 2023 at 04:36:41PM +0800, Hal Feng wrote:
>> On Tue, 21 Feb 2023 10:46:26 +0800, Hal Feng wrote:
>> > This patch series adds basic clock, reset & DT support for StarFive
>> > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
>> > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
>> > of VisionFive 2 board and JH7110 SoC.
>> >
>> > You can simply review or test the patches at the link [3].
>> >
>> > [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/
>> > [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/
>> > [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
>>
>> Hi Conor,
>>
>> When I tried to rebase these patches on v6.3-rc1, I found the kernel
>> would crash on the VisionFive 2 board during startup. The logs are as
>> below. I checkout the branch to the mainline and found that the kernel
>> would also crash on the VisionFive board which is equipped with JH7100
>> SoC.
>>
>> --------------------------------
>> Unable to handle kernel paging request at virtual address 0000004cccccccd4
>> Oops [#1]
>> Modules linked in:
>> CPU: 3 PID: 87 Comm: udevd Not tainted 6.3.0-rc1-00019-g239e7809f291 #305
>> Hardware name: StarFive VisionFive 2 v1.3B (DT)
>> epc : enqueue_timer+0x18/0x90
>> ra : internal_add_timer+0x2c/0x38
>> epc : ffffffff8006a714 ra : ffffffff8006a7b8 sp : ffffffc80443bc80
>> gp : ffffffff80eb5100 tp : ffffffd8c01db200 t0 : 0000000000000000
>> t1 : 000000000000000f t2 : 0000000038b3ea28 s0 : ffffffc80443bcb0
>> s1 : ffffffff80813940 a0 : ffffffff80813940 a1 : ffffffc80443bd48
>> a2 : 000000000000020b a3 : cccccccd0b000000 a4 : cccccccccccccccc
>> a5 : 000000000000020b a6 : ffffffff80814a08 a7 : 0000000000000001
>> s2 : ffffffc80443bd48 s3 : 0000000008400040 s4 : ffffffff80813940
>> s5 : ffffffff80eea0b8 s6 : ffffffff80eb7220 s7 : 0000000000000040
>> s8 : ffffffff80eb61e0 s9 : 0000002ac84a2548 s10: 0000002ad53e92c0
>> s11: 0000000000000001 t3 : 000000000000003f t4 : 0000000000000000
>> t5 : 0000000000000004 t6 : 0000000000000003
>> status: 0000000200000100 badaddr: 0000004cccccccd4 cause: 000000000000000f
>> [<ffffffff8006a714>] enqueue_timer+0x18/0x90
>> [<ffffffff8006aa64>] add_timer_on+0xf0/0x134
>> [<ffffffff80500f18>] try_to_generate_entropy+0x1ec/0x232
>> [<ffffffff8035a636>] urandom_read_iter+0x42/0xc2
>> [<ffffffff800fff16>] vfs_read+0x17c/0x1e4
>> [<ffffffff801005b6>] ksys_read+0x78/0x98
>> [<ffffffff801005e4>] sys_read+0xe/0x16
>> [<ffffffff800035dc>] ret_from_syscall+0x0/0x2
>> Code: 9381 9713 0037 0813 0705 983a 3703 0008 e198 c311 (e70c) d713
>> ---[ end trace 0000000000000000 ]---
>> note: udevd[87] exited with irqs disabled
>> Segmentation fault
>> FAIL
>> Saving random seed:
>> rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
>> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=7474
>> rcu: (detected by 2, t=15005 jiffies, g=-195, q=35 ncpus=4)
>> Task dump for CPU 1:
>> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008
>> Call Trace:
>> [<ffffffff80003764>] ret_from_fork+0x0/0xc
>> rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
>> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=29814
>> rcu: (detected by 2, t=60018 jiffies, g=-195, q=35 ncpus=4)
>> Task dump for CPU 1:
>> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008
>> Call Trace:
>> [<ffffffff80003764>] ret_from_fork+0x0/0xc
>> ...
>> --------------------------------
>>
>> I used 'git bisect' and found out the commit 9493e6f3ce02 is the
>> cause. I tried to revert this commit on the tag v6.3-rc1, but it
>> seems there is no improvement.
>
> Hmm, I'm not entirely sure that that is a good bisect.
> This is a fix for my stupidity in the commit you mention:
> https://lore.kernel.org/linux-riscv/20230302174154.970746-1-conor@kernel.org/
>
> But the main backtrace there is not from that patch at all, I think it
> is Linus' fault.
> The HEAD of Linus' tree is currently 8ca09d5fa3549 ("cpumask: fix
> incorrect cpumask scanning result checks") should be a fix for the
> backtrace that you are seeing above.
>
>> Any options I am missing? Could you please give me some suggestions
>> to adapt to the new changes between 6.2 and 6.3? Thank you in
>> advance.
>
> LMK if the above two things don't fix it for you & I'll go digging
> tonight.
The above two methods can fix the problem. Here are my test results.
The VisionFive board can boot up successfully if and only if all above
two applied.
The VisionFive 2 board can boot up successfully if I merge Linus's new
changes.
Hope your fix will be merged in rc2. Thank you for your reply.
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-07 10:08 ` Hal Feng
@ 2023-03-08 12:28 ` Tommaso Merciai
2023-03-08 13:36 ` Conor Dooley
0 siblings, 1 reply; 71+ messages in thread
From: Tommaso Merciai @ 2023-03-08 12:28 UTC (permalink / raw)
To: Hal Feng
Cc: Conor Dooley, Conor Dooley, linux-riscv, devicetree, linux-clk,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
Hello Hal/Conor,
On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote:
> On Tue, 7 Mar 2023 08:51:49 +0000, Conor Dooley wrote:
> > On Tue, Mar 07, 2023 at 04:36:41PM +0800, Hal Feng wrote:
> >> On Tue, 21 Feb 2023 10:46:26 +0800, Hal Feng wrote:
> >> > This patch series adds basic clock, reset & DT support for StarFive
> >> > JH7110 SoC. Patch 17 depends on series [1] which provides pinctrl
> >> > dt-bindings. Patch 19 depends on series [2] which provides dt-bindings
> >> > of VisionFive 2 board and JH7110 SoC.
> >> >
> >> > You can simply review or test the patches at the link [3].
> >> >
> >> > [1]: https://lore.kernel.org/all/20230209143702.44408-1-hal.feng@starfivetech.com/
> >> > [2]: https://lore.kernel.org/all/20230216131511.3327943-1-conor.dooley@microchip.com/
> >> > [3]: https://github.com/hal-feng/linux/commits/visionfive2-minimal
> >>
> >> Hi Conor,
> >>
> >> When I tried to rebase these patches on v6.3-rc1, I found the kernel
> >> would crash on the VisionFive 2 board during startup. The logs are as
> >> below. I checkout the branch to the mainline and found that the kernel
> >> would also crash on the VisionFive board which is equipped with JH7100
> >> SoC.
> >>
> >> --------------------------------
> >> Unable to handle kernel paging request at virtual address 0000004cccccccd4
> >> Oops [#1]
> >> Modules linked in:
> >> CPU: 3 PID: 87 Comm: udevd Not tainted 6.3.0-rc1-00019-g239e7809f291 #305
> >> Hardware name: StarFive VisionFive 2 v1.3B (DT)
> >> epc : enqueue_timer+0x18/0x90
> >> ra : internal_add_timer+0x2c/0x38
> >> epc : ffffffff8006a714 ra : ffffffff8006a7b8 sp : ffffffc80443bc80
> >> gp : ffffffff80eb5100 tp : ffffffd8c01db200 t0 : 0000000000000000
> >> t1 : 000000000000000f t2 : 0000000038b3ea28 s0 : ffffffc80443bcb0
> >> s1 : ffffffff80813940 a0 : ffffffff80813940 a1 : ffffffc80443bd48
> >> a2 : 000000000000020b a3 : cccccccd0b000000 a4 : cccccccccccccccc
> >> a5 : 000000000000020b a6 : ffffffff80814a08 a7 : 0000000000000001
> >> s2 : ffffffc80443bd48 s3 : 0000000008400040 s4 : ffffffff80813940
> >> s5 : ffffffff80eea0b8 s6 : ffffffff80eb7220 s7 : 0000000000000040
> >> s8 : ffffffff80eb61e0 s9 : 0000002ac84a2548 s10: 0000002ad53e92c0
> >> s11: 0000000000000001 t3 : 000000000000003f t4 : 0000000000000000
> >> t5 : 0000000000000004 t6 : 0000000000000003
> >> status: 0000000200000100 badaddr: 0000004cccccccd4 cause: 000000000000000f
> >> [<ffffffff8006a714>] enqueue_timer+0x18/0x90
> >> [<ffffffff8006aa64>] add_timer_on+0xf0/0x134
> >> [<ffffffff80500f18>] try_to_generate_entropy+0x1ec/0x232
> >> [<ffffffff8035a636>] urandom_read_iter+0x42/0xc2
> >> [<ffffffff800fff16>] vfs_read+0x17c/0x1e4
> >> [<ffffffff801005b6>] ksys_read+0x78/0x98
> >> [<ffffffff801005e4>] sys_read+0xe/0x16
> >> [<ffffffff800035dc>] ret_from_syscall+0x0/0x2
> >> Code: 9381 9713 0037 0813 0705 983a 3703 0008 e198 c311 (e70c) d713
> >> ---[ end trace 0000000000000000 ]---
> >> note: udevd[87] exited with irqs disabled
> >> Segmentation fault
> >> FAIL
> >> Saving random seed:
> >> rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
> >> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=7474
> >> rcu: (detected by 2, t=15005 jiffies, g=-195, q=35 ncpus=4)
> >> Task dump for CPU 1:
> >> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008
> >> Call Trace:
> >> [<ffffffff80003764>] ret_from_fork+0x0/0xc
> >> rcu: INFO: rcu_sched detected stalls on CPUs/tasks:
> >> rcu: 1-...0: (0 ticks this GP) idle=19c4/1/0x4000000000000000 softirq=42/42 fqs=29814
> >> rcu: (detected by 2, t=60018 jiffies, g=-195, q=35 ncpus=4)
> >> Task dump for CPU 1:
> >> task:dd state:R running task stack:0 pid:92 ppid:88 flags:0x00000008
> >> Call Trace:
> >> [<ffffffff80003764>] ret_from_fork+0x0/0xc
> >> ...
> >> --------------------------------
> >>
> >> I used 'git bisect' and found out the commit 9493e6f3ce02 is the
> >> cause. I tried to revert this commit on the tag v6.3-rc1, but it
> >> seems there is no improvement.
> >
> > Hmm, I'm not entirely sure that that is a good bisect.
> > This is a fix for my stupidity in the commit you mention:
> > https://lore.kernel.org/linux-riscv/20230302174154.970746-1-conor@kernel.org/
> >
> > But the main backtrace there is not from that patch at all, I think it
> > is Linus' fault.
> > The HEAD of Linus' tree is currently 8ca09d5fa3549 ("cpumask: fix
> > incorrect cpumask scanning result checks") should be a fix for the
> > backtrace that you are seeing above.
> >
> >> Any options I am missing? Could you please give me some suggestions
> >> to adapt to the new changes between 6.2 and 6.3? Thank you in
> >> advance.
> >
> > LMK if the above two things don't fix it for you & I'll go digging
> > tonight.
>
> The above two methods can fix the problem. Here are my test results.
> The VisionFive board can boot up successfully if and only if all above
> two applied.
> The VisionFive 2 board can boot up successfully if I merge Linus's new
> changes.
Tested also on my side. Hope this can be helpfull.
>
> Hope your fix will be merged in rc2. Thank you for your reply.
Fully agree.
Regards,
Tommaso
>
> Best regards,
> Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-08 12:28 ` Tommaso Merciai
@ 2023-03-08 13:36 ` Conor Dooley
2023-03-09 16:49 ` Tommaso Merciai
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-03-08 13:36 UTC (permalink / raw)
To: Tommaso Merciai
Cc: Hal Feng, Conor Dooley, linux-riscv, devicetree, linux-clk,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 959 bytes --]
On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote:
> On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote:
> > The above two methods can fix the problem. Here are my test results.
> > The VisionFive board can boot up successfully if and only if all above
> > two applied.
> > The VisionFive 2 board can boot up successfully if I merge Linus's new
> > changes.
>
> Tested also on my side. Hope this can be helpfull.
>
> > Hope your fix will be merged in rc2. Thank you for your reply.
>
> Fully agree.
If you only have a VisionFive 2, it shouldn't matter to you, as you
don't need to fix up any SiFive errata (at the moment at least).
Linus' fix is already in his tree, so should be in -rc2!
The fix for the VisionFive was applied to Palmer's RISC-V fixes tree
last night:
https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b
Thanks,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
2023-02-28 2:42 ` Hal Feng
@ 2023-03-09 9:43 ` Hal Feng
2023-03-09 14:06 ` Emil Renner Berthing
0 siblings, 1 reply; 71+ messages in thread
From: Hal Feng @ 2023-03-09 9:43 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Tue, 28 Feb 2023 10:42:35 +0800, Hal Feng wrote:
> On Sun, 26 Feb 2023 18:34:52 +0100, Emil Renner Berthing wrote:
>> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
>>> From: Emil Renner Berthing <kernel@esmil.dk>
>>>
>>> Add driver for the StarFive JH7110 always-on clock controller
>>> and register an auxiliary device for always-on reset controller
>>> which is named as "reset-aon".
>>>
>>> Reported-by: kernel test robot <lkp@intel.com>
>>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
>>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>>> ---
>>> drivers/clk/starfive/Kconfig | 11 ++
>>> drivers/clk/starfive/Makefile | 1 +
>>> .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++++++++++++++++
>>> 3 files changed, 168 insertions(+)
>>> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
>>>
>>> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
>>> index 4640d0665d1c..2aa664f2cdee 100644
>>> --- a/drivers/clk/starfive/Kconfig
>>> +++ b/drivers/clk/starfive/Kconfig
>>> @@ -31,3 +31,14 @@ config CLK_STARFIVE_JH7110_SYS
>>> help
>>> Say yes here to support the system clock controller on the
>>> StarFive JH7110 SoC.
>>> +
>>> +config CLK_STARFIVE_JH7110_AON
>>> + tristate "StarFive JH7110 always-on clock support"
>>> + depends on CLK_STARFIVE_JH7110_SYS
>>> + select AUXILIARY_BUS
>>> + select CLK_STARFIVE_JH71X0
>>> + select RESET_STARFIVE_JH7110
>>> + default CLK_STARFIVE_JH7110_SYS
>>
>> As far as I can tell the JH7110 boots fine without this driver and it
>> already depends on the _SYS driver above, so please do
>>
>> default m if SOC_STARFIVE
>
> OK. Will fix it.
Hi, Emil,
The AON clock driver provides clocks for gmac0 which is used frequently.
So I think it would be more convenient if we set "default y" here.
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
2023-03-09 9:43 ` Hal Feng
@ 2023-03-09 14:06 ` Emil Renner Berthing
2023-03-09 18:11 ` Conor Dooley
0 siblings, 1 reply; 71+ messages in thread
From: Emil Renner Berthing @ 2023-03-09 14:06 UTC (permalink / raw)
To: Hal Feng
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Thu, 9 Mar 2023 at 10:44, Hal Feng <hal.feng@starfivetech.com> wrote:
> On Tue, 28 Feb 2023 10:42:35 +0800, Hal Feng wrote:
> > On Sun, 26 Feb 2023 18:34:52 +0100, Emil Renner Berthing wrote:
> >> On Tue, 21 Feb 2023 at 03:47, Hal Feng <hal.feng@starfivetech.com> wrote:
> >>> From: Emil Renner Berthing <kernel@esmil.dk>
> >>>
> >>> Add driver for the StarFive JH7110 always-on clock controller
> >>> and register an auxiliary device for always-on reset controller
> >>> which is named as "reset-aon".
> >>>
> >>> Reported-by: kernel test robot <lkp@intel.com>
> >>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> >>> Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
> >>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
> >>> ---
> >>> drivers/clk/starfive/Kconfig | 11 ++
> >>> drivers/clk/starfive/Makefile | 1 +
> >>> .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++++++++++++++++
> >>> 3 files changed, 168 insertions(+)
> >>> create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
> >>>
> >>> diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
> >>> index 4640d0665d1c..2aa664f2cdee 100644
> >>> --- a/drivers/clk/starfive/Kconfig
> >>> +++ b/drivers/clk/starfive/Kconfig
> >>> @@ -31,3 +31,14 @@ config CLK_STARFIVE_JH7110_SYS
> >>> help
> >>> Say yes here to support the system clock controller on the
> >>> StarFive JH7110 SoC.
> >>> +
> >>> +config CLK_STARFIVE_JH7110_AON
> >>> + tristate "StarFive JH7110 always-on clock support"
> >>> + depends on CLK_STARFIVE_JH7110_SYS
> >>> + select AUXILIARY_BUS
> >>> + select CLK_STARFIVE_JH71X0
> >>> + select RESET_STARFIVE_JH7110
> >>> + default CLK_STARFIVE_JH7110_SYS
> >>
> >> As far as I can tell the JH7110 boots fine without this driver and it
> >> already depends on the _SYS driver above, so please do
> >>
> >> default m if SOC_STARFIVE
> >
> > OK. Will fix it.
>
> Hi, Emil,
>
> The AON clock driver provides clocks for gmac0 which is used frequently.
> So I think it would be more convenient if we set "default y" here.
You're right that if we default y for the ethernet driver then the aon
clock/reset should also default y. Personally I don't think we should
default y for every ethernet driver that might be used on some
supported risc-v platform, but I see now that
arch/riscv/config/defconfig already contains CONFIG_MACB=y,
CONFIG_E1000E=y, CONFIG_R8169=y and CONFIG_MICROSEMI_PHY=y, so maybe
I'm wrong or just too late.
> Best regards,
> Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
2023-02-21 2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-02-21 17:26 ` Conor Dooley
@ 2023-03-09 14:22 ` Geert Uytterhoeven
2023-03-13 2:29 ` Hal Feng
1 sibling, 1 reply; 71+ messages in thread
From: Geert Uytterhoeven @ 2023-03-09 14:22 UTC (permalink / raw)
To: Hal Feng, Emil Renner Berthing
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
Hi Hal, Esmil,
On Tue, 21 Feb 2023, Hal Feng wrote:
> From: Emil Renner Berthing <kernel@esmil.dk>
>
> Add bindings for the always-on clock and reset generator (AONCRG) on the
> JH7110 RISC-V SoC by StarFive Ltd.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Thanks for your patch!
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
> @@ -0,0 +1,76 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 Always-On Clock and Reset Generator
> +
> +maintainers:
> + - Emil Renner Berthing <kernel@esmil.dk>
> +
This lacks a top-level "description" section, to anwer the question:
What is an "Always-On Clock and Reset Generator"?
To me, "always-on" sounds like it's critical, and thus the driver
must always be built-in?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-08 13:36 ` Conor Dooley
@ 2023-03-09 16:49 ` Tommaso Merciai
2023-03-09 17:52 ` Conor Dooley
0 siblings, 1 reply; 71+ messages in thread
From: Tommaso Merciai @ 2023-03-09 16:49 UTC (permalink / raw)
To: Conor Dooley
Cc: Hal Feng, Conor Dooley, linux-riscv, devicetree, linux-clk,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
On Wed, Mar 08, 2023 at 01:36:41PM +0000, Conor Dooley wrote:
> On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote:
> > On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote:
>
> > > The above two methods can fix the problem. Here are my test results.
> > > The VisionFive board can boot up successfully if and only if all above
> > > two applied.
> > > The VisionFive 2 board can boot up successfully if I merge Linus's new
> > > changes.
> >
> > Tested also on my side. Hope this can be helpfull.
> >
> > > Hope your fix will be merged in rc2. Thank you for your reply.
> >
> > Fully agree.
>
> If you only have a VisionFive 2, it shouldn't matter to you, as you
> don't need to fix up any SiFive errata (at the moment at least).
> Linus' fix is already in his tree, so should be in -rc2!
> The fix for the VisionFive was applied to Palmer's RISC-V fixes tree
> last night:
> https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b
>
> Thanks,
> Conor.
Hi Conor,
Thanks for the info.
Playing with this series I got the following error:
[ 6.278182] BUG: spinlock bad magic on CPU#0, udevd/136
[ 6.283414] lock: 0xffffffd84135e6c0, .magic: ffffffff, .owner: <none>/-1, .owner_cpu: -1
[ 6.291677] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14
[ 6.299502] Hardware name: StarFive VisionFive 2 v1.3B (DT)
[ 6.305069] Call Trace:
[ 6.307517] [<ffffffff80005530>] dump_backtrace+0x1c/0x24
[ 6.312921] [<ffffffff80844b4e>] show_stack+0x2c/0x38
[ 6.317976] [<ffffffff8085032c>] dump_stack_lvl+0x3c/0x54
[ 6.323377] [<ffffffff80850358>] dump_stack+0x14/0x1c
[ 6.328429] [<ffffffff80845668>] spin_dump+0x64/0x70
[ 6.333394] [<ffffffff80058f26>] do_raw_spin_lock+0xb4/0xf2
[ 6.338970] [<ffffffff80857d04>] _raw_spin_lock+0x1a/0x22
[ 6.344370] [<ffffffff8008153c>] add_timer_on+0x8a/0x132
[ 6.349684] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278
[ 6.356037] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8
[ 6.361697] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8
[ 6.366752] [<ffffffff801a1986>] ksys_read+0x5e/0xc8
[ 6.371710] [<ffffffff801a19fe>] sys_read+0xe/0x16
[ 6.376503] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2
[ 6.381905] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000007
[ 6.390683] Oops [#1]
[ 6.392956] Modules linked in:
[ 6.396011] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14
[ 6.403835] Hardware name: StarFive VisionFive 2 v1.3B (DT)
[ 6.409401] epc : enqueue_timer+0x1a/0x90
[ 6.413414] ra : add_timer_on+0xe2/0x132
[ 6.417425] epc : ffffffff80080c60 ra : ffffffff80081594 sp : ffffffc8044dbc60
[ 6.424640] gp : ffffffff814ffe50 tp : ffffffd8c171ad00 t0 : 6666666666663c5b
[ 6.431855] t1 : 000000000000005b t2 : 666666666666663c s0 : ffffffc8044dbcc0
[ 6.439070] s1 : ffffffc8044dbd08 a0 : ffffffd84135e6c0 a1 : ffffffc8044dbd08
[ 6.446284] a2 : ffffffffffffffff a3 : 000000003e000000 a4 : 000000000000023e
[ 6.453498] a5 : 000000000000023e a6 : ffffffd84135f930 a7 : 0000000000000038
[ 6.460712] s2 : ffffffd84135e6c0 s3 : 0000000000000040 s4 : ffffffff81501080
[ 6.467926] s5 : ffffffd84135e6c0 s6 : ffffffff815011b8 s7 : ffffffffffffffff
[ 6.475141] s8 : ffffffff81502820 s9 : 0000000000000040 s10: 0000002ab0a49320
[ 6.482355] s11: 0000000000000001 t3 : ffffffff81512e97 t4 : ffffffff81512e97
[ 6.489569] t5 : ffffffff81512e98 t6 : ffffffc8044db948
[ 6.494875] status: 0000000200000100 badaddr: 0000000000000007 cause: 000000000000000f
[ 6.502783] [<ffffffff80080c60>] enqueue_timer+0x1a/0x90
[ 6.508095] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278
[ 6.514448] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8
[ 6.520107] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8
[ 6.525160] [<ffffffff801a1986>] ksys_read+0x5e/0xc8
[ 6.530126] [<ffffffff801a19fe>] sys_read+0xe/0x16
[ 6.534918] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2
[ 6.540322] Code: 87b2 0813 0805 1613 0037 9832 3603 0008 e190 c211 (e60c) 5613
[ 6.547711] ---[ end trace 0000000000000000 ]---
[ 6.552325] note: udevd[136] exited with irqs disabled
[ 6.557531] note: udevd[136] exited with preempt_count 2
I'm working on top of Linux version 6.3.0-rc1-g92569901a7f.
Did you already see this crash?
Let me know.
Thanks,
Tommaso
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-09 16:49 ` Tommaso Merciai
@ 2023-03-09 17:52 ` Conor Dooley
2023-03-09 18:58 ` Tommaso Merciai
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-03-09 17:52 UTC (permalink / raw)
To: Tommaso Merciai
Cc: Hal Feng, Conor Dooley, linux-riscv, devicetree, linux-clk,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 5033 bytes --]
On Thu, Mar 09, 2023 at 05:49:48PM +0100, Tommaso Merciai wrote:
> On Wed, Mar 08, 2023 at 01:36:41PM +0000, Conor Dooley wrote:
> > On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote:
> > > On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote:
> >
> > > > The above two methods can fix the problem. Here are my test results.
> > > > The VisionFive board can boot up successfully if and only if all above
> > > > two applied.
> > > > The VisionFive 2 board can boot up successfully if I merge Linus's new
> > > > changes.
> > >
> > > Tested also on my side. Hope this can be helpfull.
> > >
> > > > Hope your fix will be merged in rc2. Thank you for your reply.
> > >
> > > Fully agree.
> >
> > If you only have a VisionFive 2, it shouldn't matter to you, as you
> > don't need to fix up any SiFive errata (at the moment at least).
> > Linus' fix is already in his tree, so should be in -rc2!
> > The fix for the VisionFive was applied to Palmer's RISC-V fixes tree
> > last night:
> > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b
> >
> > Thanks,
> > Conor.
>
>
> Hi Conor,
> Thanks for the info.
> Playing with this series I got the following error:
>
> [ 6.278182] BUG: spinlock bad magic on CPU#0, udevd/136
> [ 6.283414] lock: 0xffffffd84135e6c0, .magic: ffffffff, .owner: <none>/-1, .owner_cpu: -1
> [ 6.291677] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14
> [ 6.299502] Hardware name: StarFive VisionFive 2 v1.3B (DT)
> [ 6.305069] Call Trace:
> [ 6.307517] [<ffffffff80005530>] dump_backtrace+0x1c/0x24
> [ 6.312921] [<ffffffff80844b4e>] show_stack+0x2c/0x38
> [ 6.317976] [<ffffffff8085032c>] dump_stack_lvl+0x3c/0x54
> [ 6.323377] [<ffffffff80850358>] dump_stack+0x14/0x1c
> [ 6.328429] [<ffffffff80845668>] spin_dump+0x64/0x70
> [ 6.333394] [<ffffffff80058f26>] do_raw_spin_lock+0xb4/0xf2
> [ 6.338970] [<ffffffff80857d04>] _raw_spin_lock+0x1a/0x22
> [ 6.344370] [<ffffffff8008153c>] add_timer_on+0x8a/0x132
> [ 6.349684] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278
> [ 6.356037] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8
> [ 6.361697] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8
> [ 6.366752] [<ffffffff801a1986>] ksys_read+0x5e/0xc8
> [ 6.371710] [<ffffffff801a19fe>] sys_read+0xe/0x16
> [ 6.376503] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2
> [ 6.381905] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000007
> [ 6.390683] Oops [#1]
> [ 6.392956] Modules linked in:
> [ 6.396011] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14
> [ 6.403835] Hardware name: StarFive VisionFive 2 v1.3B (DT)
> [ 6.409401] epc : enqueue_timer+0x1a/0x90
> [ 6.413414] ra : add_timer_on+0xe2/0x132
> [ 6.417425] epc : ffffffff80080c60 ra : ffffffff80081594 sp : ffffffc8044dbc60
> [ 6.424640] gp : ffffffff814ffe50 tp : ffffffd8c171ad00 t0 : 6666666666663c5b
> [ 6.431855] t1 : 000000000000005b t2 : 666666666666663c s0 : ffffffc8044dbcc0
> [ 6.439070] s1 : ffffffc8044dbd08 a0 : ffffffd84135e6c0 a1 : ffffffc8044dbd08
> [ 6.446284] a2 : ffffffffffffffff a3 : 000000003e000000 a4 : 000000000000023e
> [ 6.453498] a5 : 000000000000023e a6 : ffffffd84135f930 a7 : 0000000000000038
> [ 6.460712] s2 : ffffffd84135e6c0 s3 : 0000000000000040 s4 : ffffffff81501080
> [ 6.467926] s5 : ffffffd84135e6c0 s6 : ffffffff815011b8 s7 : ffffffffffffffff
> [ 6.475141] s8 : ffffffff81502820 s9 : 0000000000000040 s10: 0000002ab0a49320
> [ 6.482355] s11: 0000000000000001 t3 : ffffffff81512e97 t4 : ffffffff81512e97
> [ 6.489569] t5 : ffffffff81512e98 t6 : ffffffc8044db948
> [ 6.494875] status: 0000000200000100 badaddr: 0000000000000007 cause: 000000000000000f
> [ 6.502783] [<ffffffff80080c60>] enqueue_timer+0x1a/0x90
> [ 6.508095] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278
> [ 6.514448] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8
> [ 6.520107] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8
> [ 6.525160] [<ffffffff801a1986>] ksys_read+0x5e/0xc8
> [ 6.530126] [<ffffffff801a19fe>] sys_read+0xe/0x16
> [ 6.534918] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2
> [ 6.540322] Code: 87b2 0813 0805 1613 0037 9832 3603 0008 e190 c211 (e60c) 5613
> [ 6.547711] ---[ end trace 0000000000000000 ]---
> [ 6.552325] note: udevd[136] exited with irqs disabled
> [ 6.557531] note: udevd[136] exited with preempt_count 2
>
>
> I'm working on top of Linux version 6.3.0-rc1-g92569901a7f.
Unfortunately, this g<sha> bit doesn't mean anything outside of your
repo so it's hard to infer anything from that.
This looks exactly like a bug is in v6.3-rc1, but Linus fixed in like
the second commit *after* -rc1.
What branch/commit/tag did you apply the series on top of?
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
2023-03-09 14:06 ` Emil Renner Berthing
@ 2023-03-09 18:11 ` Conor Dooley
2023-03-09 18:19 ` Emil Renner Berthing
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-03-09 18:11 UTC (permalink / raw)
To: Emil Renner Berthing
Cc: Hal Feng, linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
linux-kernel
[-- Attachment #1: Type: text/plain, Size: 1557 bytes --]
On Thu, Mar 09, 2023 at 03:06:13PM +0100, Emil Renner Berthing wrote:
> On Thu, 9 Mar 2023 at 10:44, Hal Feng <hal.feng@starfivetech.com> wrote:
> > The AON clock driver provides clocks for gmac0 which is used frequently.
> > So I think it would be more convenient if we set "default y" here.
> You're right that if we default y for the ethernet driver then the aon
> clock/reset should also default y. Personally I don't think we should
> default y for every ethernet driver that might be used on some
> supported risc-v platform, but I see now that
> arch/riscv/config/defconfig already contains CONFIG_MACB=y,
> CONFIG_E1000E=y, CONFIG_R8169=y and CONFIG_MICROSEMI_PHY=y, so maybe
> I'm wrong or just too late.
The defconfig really needs a good bit of cleanup (one of the many things
that I am telling myself I will do as part of kconfig.socs cleanup).
w.r.t defconfig Palmer said it pretty well earlier on IRC: "defconfig
should be useful for kernel devs, which means it should boot on the
common dev boards".
IMO, that means enough to boot an initramfs and poke the thing to see
that it is alive, so: ethernet & serial, and the clocks/resets/pinctrl
stuff required to get those going can all be set to y in defconfig.
In the driver Kconfig entries, to me, it's more or less the same.
I guess, answer the question "Will your customer's board get to the
point where it can load a module ithout building this into the kernel?".
If the answer to that question is yes, then don't make it default y.
That's my €0.02!
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
2023-03-09 18:11 ` Conor Dooley
@ 2023-03-09 18:19 ` Emil Renner Berthing
2023-03-09 19:32 ` Palmer Dabbelt
0 siblings, 1 reply; 71+ messages in thread
From: Emil Renner Berthing @ 2023-03-09 18:19 UTC (permalink / raw)
To: Conor Dooley
Cc: Hal Feng, linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
linux-kernel
On Thu, 9 Mar 2023 at 19:11, Conor Dooley <conor@kernel.org> wrote:
>
> On Thu, Mar 09, 2023 at 03:06:13PM +0100, Emil Renner Berthing wrote:
> > On Thu, 9 Mar 2023 at 10:44, Hal Feng <hal.feng@starfivetech.com> wrote:
>
> > > The AON clock driver provides clocks for gmac0 which is used frequently.
> > > So I think it would be more convenient if we set "default y" here.
>
> > You're right that if we default y for the ethernet driver then the aon
> > clock/reset should also default y. Personally I don't think we should
> > default y for every ethernet driver that might be used on some
> > supported risc-v platform, but I see now that
> > arch/riscv/config/defconfig already contains CONFIG_MACB=y,
> > CONFIG_E1000E=y, CONFIG_R8169=y and CONFIG_MICROSEMI_PHY=y, so maybe
> > I'm wrong or just too late.
>
> The defconfig really needs a good bit of cleanup (one of the many things
> that I am telling myself I will do as part of kconfig.socs cleanup).
>
> w.r.t defconfig Palmer said it pretty well earlier on IRC: "defconfig
> should be useful for kernel devs, which means it should boot on the
> common dev boards".
>
> IMO, that means enough to boot an initramfs and poke the thing to see
> that it is alive, so: ethernet & serial, and the clocks/resets/pinctrl
> stuff required to get those going can all be set to y in defconfig.
>
> In the driver Kconfig entries, to me, it's more or less the same.
> I guess, answer the question "Will your customer's board get to the
> point where it can load a module ithout building this into the kernel?".
> If the answer to that question is yes, then don't make it default y.
>
> That's my €0.02!
Cool. Defaulting to m in the Kconfig for anything that can be loaded
later is exactly what I was trying to say, except I mixed in the
defconfig for no good reason. That means both the aon clocks and
dwmac-starfive should default to m in Kconfig. The JH7110 (VisionFive
2) boots just fine like that and brings up aon clocks and ethernet
after loading the modules.
/Emil
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-09 17:52 ` Conor Dooley
@ 2023-03-09 18:58 ` Tommaso Merciai
2023-03-09 19:03 ` Conor Dooley
0 siblings, 1 reply; 71+ messages in thread
From: Tommaso Merciai @ 2023-03-09 18:58 UTC (permalink / raw)
To: Conor Dooley
Cc: Hal Feng, Conor Dooley, linux-riscv, devicetree, linux-clk,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
On Thu, Mar 09, 2023 at 05:52:49PM +0000, Conor Dooley wrote:
> On Thu, Mar 09, 2023 at 05:49:48PM +0100, Tommaso Merciai wrote:
> > On Wed, Mar 08, 2023 at 01:36:41PM +0000, Conor Dooley wrote:
> > > On Wed, Mar 08, 2023 at 01:28:01PM +0100, Tommaso Merciai wrote:
> > > > On Tue, Mar 07, 2023 at 06:08:53PM +0800, Hal Feng wrote:
> > >
> > > > > The above two methods can fix the problem. Here are my test results.
> > > > > The VisionFive board can boot up successfully if and only if all above
> > > > > two applied.
> > > > > The VisionFive 2 board can boot up successfully if I merge Linus's new
> > > > > changes.
> > > >
> > > > Tested also on my side. Hope this can be helpfull.
> > > >
> > > > > Hope your fix will be merged in rc2. Thank you for your reply.
> > > >
> > > > Fully agree.
> > >
> > > If you only have a VisionFive 2, it shouldn't matter to you, as you
> > > don't need to fix up any SiFive errata (at the moment at least).
> > > Linus' fix is already in his tree, so should be in -rc2!
> > > The fix for the VisionFive was applied to Palmer's RISC-V fixes tree
> > > last night:
> > > https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git/commit/?h=fixes&id=bf89b7ee52af5a5944fa3539e86089f72475055b
> > >
> > > Thanks,
> > > Conor.
> >
> >
> > Hi Conor,
> > Thanks for the info.
> > Playing with this series I got the following error:
> >
> > [ 6.278182] BUG: spinlock bad magic on CPU#0, udevd/136
> > [ 6.283414] lock: 0xffffffd84135e6c0, .magic: ffffffff, .owner: <none>/-1, .owner_cpu: -1
> > [ 6.291677] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14
> > [ 6.299502] Hardware name: StarFive VisionFive 2 v1.3B (DT)
> > [ 6.305069] Call Trace:
> > [ 6.307517] [<ffffffff80005530>] dump_backtrace+0x1c/0x24
> > [ 6.312921] [<ffffffff80844b4e>] show_stack+0x2c/0x38
> > [ 6.317976] [<ffffffff8085032c>] dump_stack_lvl+0x3c/0x54
> > [ 6.323377] [<ffffffff80850358>] dump_stack+0x14/0x1c
> > [ 6.328429] [<ffffffff80845668>] spin_dump+0x64/0x70
> > [ 6.333394] [<ffffffff80058f26>] do_raw_spin_lock+0xb4/0xf2
> > [ 6.338970] [<ffffffff80857d04>] _raw_spin_lock+0x1a/0x22
> > [ 6.344370] [<ffffffff8008153c>] add_timer_on+0x8a/0x132
> > [ 6.349684] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278
> > [ 6.356037] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8
> > [ 6.361697] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8
> > [ 6.366752] [<ffffffff801a1986>] ksys_read+0x5e/0xc8
> > [ 6.371710] [<ffffffff801a19fe>] sys_read+0xe/0x16
> > [ 6.376503] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2
> > [ 6.381905] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000007
> > [ 6.390683] Oops [#1]
> > [ 6.392956] Modules linked in:
> > [ 6.396011] CPU: 0 PID: 136 Comm: udevd Not tainted 6.3.0-rc1-g92569901a7f9-dirty #14
> > [ 6.403835] Hardware name: StarFive VisionFive 2 v1.3B (DT)
> > [ 6.409401] epc : enqueue_timer+0x1a/0x90
> > [ 6.413414] ra : add_timer_on+0xe2/0x132
> > [ 6.417425] epc : ffffffff80080c60 ra : ffffffff80081594 sp : ffffffc8044dbc60
> > [ 6.424640] gp : ffffffff814ffe50 tp : ffffffd8c171ad00 t0 : 6666666666663c5b
> > [ 6.431855] t1 : 000000000000005b t2 : 666666666666663c s0 : ffffffc8044dbcc0
> > [ 6.439070] s1 : ffffffc8044dbd08 a0 : ffffffd84135e6c0 a1 : ffffffc8044dbd08
> > [ 6.446284] a2 : ffffffffffffffff a3 : 000000003e000000 a4 : 000000000000023e
> > [ 6.453498] a5 : 000000000000023e a6 : ffffffd84135f930 a7 : 0000000000000038
> > [ 6.460712] s2 : ffffffd84135e6c0 s3 : 0000000000000040 s4 : ffffffff81501080
> > [ 6.467926] s5 : ffffffd84135e6c0 s6 : ffffffff815011b8 s7 : ffffffffffffffff
> > [ 6.475141] s8 : ffffffff81502820 s9 : 0000000000000040 s10: 0000002ab0a49320
> > [ 6.482355] s11: 0000000000000001 t3 : ffffffff81512e97 t4 : ffffffff81512e97
> > [ 6.489569] t5 : ffffffff81512e98 t6 : ffffffc8044db948
> > [ 6.494875] status: 0000000200000100 badaddr: 0000000000000007 cause: 000000000000000f
> > [ 6.502783] [<ffffffff80080c60>] enqueue_timer+0x1a/0x90
> > [ 6.508095] [<ffffffff8084b9fa>] try_to_generate_entropy+0x216/0x278
> > [ 6.514448] [<ffffffff804ebfdc>] urandom_read_iter+0x40/0xb8
> > [ 6.520107] [<ffffffff801a1216>] vfs_read+0x17e/0x1f8
> > [ 6.525160] [<ffffffff801a1986>] ksys_read+0x5e/0xc8
> > [ 6.530126] [<ffffffff801a19fe>] sys_read+0xe/0x16
> > [ 6.534918] [<ffffffff8000357a>] ret_from_syscall+0x0/0x2
> > [ 6.540322] Code: 87b2 0813 0805 1613 0037 9832 3603 0008 e190 c211 (e60c) 5613
> > [ 6.547711] ---[ end trace 0000000000000000 ]---
> > [ 6.552325] note: udevd[136] exited with irqs disabled
> > [ 6.557531] note: udevd[136] exited with preempt_count 2
> >
> >
> > I'm working on top of Linux version 6.3.0-rc1-g92569901a7f.
Hi Conor,
>
> Unfortunately, this g<sha> bit doesn't mean anything outside of your
> repo so it's hard to infer anything from that.
> This looks exactly like a bug is in v6.3-rc1, but Linus fixed in like
> the second commit *after* -rc1.
Thanks for the tips.
I rebase my working branch on top of:
6a98c9cae232 (origin/master, origin/HEAD) Merge tag 'fs_for_v6.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs
https://github.com/Scott31393/linux/tree/tm/master_visionv2_v1.3b_vf2-6.2-gmac
I'm able to boot the board using nfs ;)
(without issue)
[ 0.000000] Linux version 6.3.0-rc1-gcf4a201af313 (tom@tom-HP-ZBook-Fury-15-G7-Mobile-Workstation) (riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot VF2_v2.10.4) 10.3.0, GNU ld (GNU Binutils) 2.36.1) #16 SM
P Thu Mar 9 19:31:50 CET 2023
[ 0.000000] OF: fdt: Ignoring memory range 0x40000000 - 0x40200000
[ 0.000000] Machine model: StarFive VisionFive 2 v1.3B
[ 0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
[ 0.000000] printk: bootconsole [sbi0] enabled
[ 0.000000] efi: UEFI not found.
[ 0.000000] Zone ranges:
[ 0.000000] DMA32 [mem 0x0000000040200000-0x00000000ffffffff]
[ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
[ 0.000000] Movable zone start for each node
>
> What branch/commit/tag did you apply the series on top of?
Thanks again,
Tommaso
>
> Cheers,
> Conor.
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-09 18:58 ` Tommaso Merciai
@ 2023-03-09 19:03 ` Conor Dooley
2023-03-10 7:48 ` Tommaso Merciai
0 siblings, 1 reply; 71+ messages in thread
From: Conor Dooley @ 2023-03-09 19:03 UTC (permalink / raw)
To: Tommaso Merciai
Cc: Hal Feng, Conor Dooley, linux-riscv, devicetree, linux-clk,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
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On Thu, Mar 09, 2023 at 07:58:21PM +0100, Tommaso Merciai wrote:
> I'm able to boot the board using nfs ;)
> (without issue)
Sweet, glad you got it working. If you'd like to provide a Tested-by:
for the series that'd be wonderful too :) No pressure haha
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on clock driver
2023-03-09 18:19 ` Emil Renner Berthing
@ 2023-03-09 19:32 ` Palmer Dabbelt
0 siblings, 0 replies; 71+ messages in thread
From: Palmer Dabbelt @ 2023-03-09 19:32 UTC (permalink / raw)
To: emil.renner.berthing
Cc: Conor Dooley, hal.feng, linux-clk, devicetree, linux-riscv,
sboyd, mturquette, p.zabel, robh+dt, krzysztof.kozlowski+dt,
Paul Walmsley, aou, ben.dooks, daniel.lezcano, tglx,
Marc Zyngier, linux-kernel
On Thu, 09 Mar 2023 10:19:06 PST (-0800), emil.renner.berthing@canonical.com wrote:
> On Thu, 9 Mar 2023 at 19:11, Conor Dooley <conor@kernel.org> wrote:
>>
>> On Thu, Mar 09, 2023 at 03:06:13PM +0100, Emil Renner Berthing wrote:
>> > On Thu, 9 Mar 2023 at 10:44, Hal Feng <hal.feng@starfivetech.com> wrote:
>>
>> > > The AON clock driver provides clocks for gmac0 which is used frequently.
>> > > So I think it would be more convenient if we set "default y" here.
>>
>> > You're right that if we default y for the ethernet driver then the aon
>> > clock/reset should also default y. Personally I don't think we should
>> > default y for every ethernet driver that might be used on some
>> > supported risc-v platform, but I see now that
>> > arch/riscv/config/defconfig already contains CONFIG_MACB=y,
>> > CONFIG_E1000E=y, CONFIG_R8169=y and CONFIG_MICROSEMI_PHY=y, so maybe
>> > I'm wrong or just too late.
>>
>> The defconfig really needs a good bit of cleanup (one of the many things
>> that I am telling myself I will do as part of kconfig.socs cleanup).
>>
>> w.r.t defconfig Palmer said it pretty well earlier on IRC: "defconfig
>> should be useful for kernel devs, which means it should boot on the
>> common dev boards".
>>
>> IMO, that means enough to boot an initramfs and poke the thing to see
>> that it is alive, so: ethernet & serial, and the clocks/resets/pinctrl
>> stuff required to get those going can all be set to y in defconfig.
>>
>> In the driver Kconfig entries, to me, it's more or less the same.
>> I guess, answer the question "Will your customer's board get to the
>> point where it can load a module ithout building this into the kernel?".
>> If the answer to that question is yes, then don't make it default y.
>>
>> That's my €0.02!
>
> Cool. Defaulting to m in the Kconfig for anything that can be loaded
> later is exactly what I was trying to say, except I mixed in the
> defconfig for no good reason. That means both the aon clocks and
> dwmac-starfive should default to m in Kconfig. The JH7110 (VisionFive
> 2) boots just fine like that and brings up aon clocks and ethernet
> after loading the modules.
That seems pretty reasonable to me. It's not like defconfig or Kconfig
defaults or whatever are the only things we're going to test, but it's
way easier for folks trying poke around with these dev boards if they
boot defconfig.
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC
2023-03-09 19:03 ` Conor Dooley
@ 2023-03-10 7:48 ` Tommaso Merciai
0 siblings, 0 replies; 71+ messages in thread
From: Tommaso Merciai @ 2023-03-10 7:48 UTC (permalink / raw)
To: Conor Dooley
Cc: Hal Feng, Conor Dooley, linux-riscv, devicetree, linux-clk,
Stephen Boyd, Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Palmer Dabbelt, Paul Walmsley, Albert Ou,
Ben Dooks, Daniel Lezcano, Thomas Gleixner, Marc Zyngier,
Emil Renner Berthing, linux-kernel
Hello Conor,
On Thu, Mar 09, 2023 at 07:03:47PM +0000, Conor Dooley wrote:
> On Thu, Mar 09, 2023 at 07:58:21PM +0100, Tommaso Merciai wrote:
>
> > I'm able to boot the board using nfs ;)
> > (without issue)
>
> Sweet, glad you got it working. If you'd like to provide a Tested-by:
> for the series that'd be wonderful too :) No pressure haha
>
Yes ofc I provide my Tested-by ;)
I collect some other series like gmac integration.
I need to clarify.
btw below my tag on this series :)
Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
Thanks & Regards,
Tommaso
^ permalink raw reply [flat|nested] 71+ messages in thread
* Re: [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on clock and reset generator
2023-03-09 14:22 ` Geert Uytterhoeven
@ 2023-03-13 2:29 ` Hal Feng
0 siblings, 0 replies; 71+ messages in thread
From: Hal Feng @ 2023-03-13 2:29 UTC (permalink / raw)
To: Geert Uytterhoeven, Emil Renner Berthing
Cc: linux-clk, devicetree, linux-riscv, Stephen Boyd,
Michael Turquette, Philipp Zabel, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Palmer Dabbelt, Paul Walmsley,
Albert Ou, Ben Dooks, Daniel Lezcano, Thomas Gleixner,
Marc Zyngier, linux-kernel
On Thu, 9 Mar 2023 15:22:54 +0100, Geert Uytterhoeven wrote:
> Hi Hal, Esmil,
>
> On Tue, 21 Feb 2023, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@esmil.dk>
>>
>> Add bindings for the always-on clock and reset generator (AONCRG) on the
>> JH7110 RISC-V SoC by StarFive Ltd.
>>
>> Reviewed-by: Rob Herring <robh@kernel.org>
>> Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
>> Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
>
> Thanks for your patch!
>
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
>> @@ -0,0 +1,76 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive JH7110 Always-On Clock and Reset Generator
>> +
>> +maintainers:
>> + - Emil Renner Berthing <kernel@esmil.dk>
>> +
>
> This lacks a top-level "description" section, to anwer the question:
> What is an "Always-On Clock and Reset Generator"?
>
> To me, "always-on" sounds like it's critical, and thus the driver
> must always be built-in?
AON is a part of JH7110 circuit which is always powered on, but the
AON clocks can be turned off if not used. The JH7110 can boot up
successfully without the AON clock driver, so it's fine to build it
as a module. Thanks.
Best regards,
Hal
^ permalink raw reply [flat|nested] 71+ messages in thread
end of thread, other threads:[~2023-03-13 3:03 UTC | newest]
Thread overview: 71+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-21 2:46 [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC Hal Feng
2023-02-21 2:46 ` [PATCH v4 01/19] clk: starfive: Factor out common JH7100 and JH7110 code Hal Feng
2023-02-21 2:46 ` [PATCH v4 02/19] clk: starfive: Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h Hal Feng
2023-02-21 2:46 ` [PATCH v4 03/19] clk: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-02-21 2:46 ` [PATCH v4 04/19] reset: Create subdirectory for StarFive drivers Hal Feng
2023-02-21 2:46 ` [PATCH v4 05/19] reset: starfive: Factor out common JH71X0 reset code Hal Feng
2023-02-21 17:10 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 06/19] reset: starfive: Extract the " Hal Feng
2023-02-21 17:13 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 07/19] reset: starfive: Rename "jh7100" to "jh71x0" for the common code Hal Feng
2023-02-21 17:17 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 08/19] reset: starfive: jh71x0: Use 32bit I/O on 32bit registers Hal Feng
2023-02-21 2:46 ` [PATCH v4 09/19] dt-bindings: clock: Add StarFive JH7110 system clock and reset generator Hal Feng
2023-02-21 17:23 ` Conor Dooley
2023-02-23 3:40 ` Hal Feng
2023-02-22 9:13 ` Krzysztof Kozlowski
2023-02-22 10:40 ` Conor Dooley
2023-02-23 10:22 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 10/19] dt-bindings: clock: Add StarFive JH7110 always-on " Hal Feng
2023-02-21 17:26 ` Conor Dooley
2023-02-23 5:52 ` Hal Feng
2023-03-09 14:22 ` Geert Uytterhoeven
2023-03-13 2:29 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 11/19] clk: starfive: Add StarFive JH7110 system clock driver Hal Feng
2023-02-21 15:12 ` Conor Dooley
2023-02-23 6:17 ` Hal Feng
2023-02-26 16:07 ` Emil Renner Berthing
2023-02-28 2:30 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 12/19] clk: starfive: Add StarFive JH7110 always-on " Hal Feng
2023-02-26 17:34 ` Emil Renner Berthing
2023-02-28 2:42 ` Hal Feng
2023-03-09 9:43 ` Hal Feng
2023-03-09 14:06 ` Emil Renner Berthing
2023-03-09 18:11 ` Conor Dooley
2023-03-09 18:19 ` Emil Renner Berthing
2023-03-09 19:32 ` Palmer Dabbelt
2023-02-21 2:46 ` [PATCH v4 13/19] reset: starfive: Add StarFive JH7110 reset driver Hal Feng
2023-02-21 15:33 ` Emil Renner Berthing
2023-02-21 16:34 ` Conor Dooley
2023-02-23 6:48 ` Hal Feng
2023-02-23 6:29 ` Hal Feng
2023-02-21 2:46 ` [PATCH v4 14/19] dt-bindings: timer: Add StarFive JH7110 clint Hal Feng
2023-02-21 2:46 ` [PATCH v4 15/19] dt-bindings: interrupt-controller: Add StarFive JH7110 plic Hal Feng
2023-02-21 2:46 ` [PATCH v4 16/19] dt-bindings: riscv: Add SiFive S7 compatible Hal Feng
2023-02-21 11:38 ` Krzysztof Kozlowski
2023-02-21 15:10 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 17/19] riscv: dts: starfive: Add initial StarFive JH7110 device tree Hal Feng
2023-02-21 17:03 ` Conor Dooley
2023-02-23 7:16 ` Hal Feng
2023-02-27 18:10 ` Conor Dooley
2023-02-21 2:46 ` [PATCH v4 18/19] riscv: dts: starfive: Add StarFive JH7110 pin function definitions Hal Feng
2023-02-21 2:46 ` [PATCH v4 19/19] riscv: dts: starfive: Add StarFive JH7110 VisionFive 2 board device tree Hal Feng
2023-02-21 15:03 ` Emil Renner Berthing
2023-02-23 8:50 ` Hal Feng
2023-02-27 18:12 ` Conor Dooley
2023-02-27 20:00 ` Conor Dooley
2023-02-28 2:58 ` Hal Feng
2023-02-22 15:00 ` [PATCH v4 00/19] Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC patchwork-bot+linux-riscv
2023-03-03 19:08 ` Tommaso Merciai
2023-03-06 3:29 ` Hal Feng
2023-03-06 10:22 ` Tommaso Merciai
2023-03-07 8:36 ` Hal Feng
2023-03-07 8:51 ` Conor Dooley
2023-03-07 10:08 ` Hal Feng
2023-03-08 12:28 ` Tommaso Merciai
2023-03-08 13:36 ` Conor Dooley
2023-03-09 16:49 ` Tommaso Merciai
2023-03-09 17:52 ` Conor Dooley
2023-03-09 18:58 ` Tommaso Merciai
2023-03-09 19:03 ` Conor Dooley
2023-03-10 7:48 ` Tommaso Merciai
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