* [PATCH 0/7] riscv: add Bouffalolab bl808 support @ 2022-11-20 8:21 Jisheng Zhang 2022-11-20 8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang ` (6 more replies) 0 siblings, 7 replies; 27+ messages in thread From: Jisheng Zhang @ 2022-11-20 8:21 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv This series adds Bouffalolab uart driver and basic devicetrees for Bouffalolab bl808 SoC and Sipeed M1S dock board. It's too late for v6.2-rc1, but I hope I can catch up the v6.3-rc1 window. Jisheng Zhang (7): dt-bindings: serial: add bindings doc for Bouffalolab serial: bflb_uart: add Bouffalolab UART Driver MAINTAINERS: add myself as a reviewer for Bouffalolab uart driver riscv: add the Bouffalolab SoC family Kconfig option riscv: dts: bouffalolab: add the bl808 SoC base device tree riscv: dts: bouffalolab: add Sipeed M1S dock devicetree MAINTAINERS: add myself as Bouffalolab SoC entry maintainer .../bindings/serial/bouffalolab,uart.yaml | 50 ++ MAINTAINERS | 12 + arch/riscv/Kconfig.socs | 6 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/bouffalolab/Makefile | 2 + .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 30 + arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++ drivers/tty/serial/Kconfig | 18 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/bflb_uart.c | 659 ++++++++++++++++++ include/uapi/linux/serial_core.h | 3 + 11 files changed, 856 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi create mode 100644 drivers/tty/serial/bflb_uart.c -- 2.37.2 ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang @ 2022-11-20 8:21 ` Jisheng Zhang 2022-11-21 10:08 ` Krzysztof Kozlowski 2022-11-30 18:04 ` Rob Herring 2022-11-20 8:21 ` [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver Jisheng Zhang ` (5 subsequent siblings) 6 siblings, 2 replies; 27+ messages in thread From: Jisheng Zhang @ 2022-11-20 8:21 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv Add bindings doc for Bouffalolab UART Driver Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- .../bindings/serial/bouffalolab,uart.yaml | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml diff --git a/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml new file mode 100644 index 000000000000..6cef956d33d2 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/serial/bouffalolab,uart.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Bouffalolab UART Controller + +maintainers: + - Jisheng Zhang <jszhang@kernel.org> + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: bouffalolab,uart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + aliases { + serial0 = &uart0; + }; + + uart0: serial@30002000 { + compatible = "bouffalolab,uart"; + reg = <0x30002000 0x1000>; + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + }; +... -- 2.37.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver 2022-11-20 8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang @ 2022-11-21 10:08 ` Krzysztof Kozlowski 2022-11-30 18:04 ` Rob Herring 1 sibling, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2022-11-21 10:08 UTC (permalink / raw) To: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv On 20/11/2022 09:21, Jisheng Zhang wrote: > Add bindings doc for Bouffalolab UART Driver Subject: drop second, redundant "bindings doc". > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > .../bindings/serial/bouffalolab,uart.yaml | 50 +++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml > > diff --git a/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml > new file mode 100644 > index 000000000000..6cef956d33d2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml > @@ -0,0 +1,50 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/serial/bouffalolab,uart.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" Drop quotes from both lines. > + > +title: Bouffalolab UART Controller > + > +maintainers: > + - Jisheng Zhang <jszhang@kernel.org> > + > +allOf: > + - $ref: serial.yaml# > + > +properties: > + compatible: > + const: bouffalolab,uart No model number? From bouffalolab there will be only one, exactly UART model? No new models in next 5, 10, 100 years? > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + aliases { > + serial0 = &uart0; > + }; Drop aliases, not related. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver 2022-11-20 8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang 2022-11-21 10:08 ` Krzysztof Kozlowski @ 2022-11-30 18:04 ` Rob Herring 1 sibling, 0 replies; 27+ messages in thread From: Rob Herring @ 2022-11-30 18:04 UTC (permalink / raw) To: Jisheng Zhang Cc: Greg Kroah-Hartman, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, Nov 20, 2022 at 04:21:08PM +0800, Jisheng Zhang wrote: > Add bindings doc for Bouffalolab UART Driver > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > .../bindings/serial/bouffalolab,uart.yaml | 50 +++++++++++++++++++ > 1 file changed, 50 insertions(+) > create mode 100644 Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml > > diff --git a/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml > new file mode 100644 > index 000000000000..6cef956d33d2 > --- /dev/null > +++ b/Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml > @@ -0,0 +1,50 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/serial/bouffalolab,uart.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Bouffalolab UART Controller > + > +maintainers: > + - Jisheng Zhang <jszhang@kernel.org> > + > +allOf: > + - $ref: serial.yaml# > + > +properties: > + compatible: > + const: bouffalolab,uart 'bouffalolab' needs to be documented in vendor-prefixes.yaml. > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + aliases { Drop, not relevant to the binding. > + serial0 = &uart0; > + }; > + > + uart0: serial@30002000 { > + compatible = "bouffalolab,uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <53 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; > + }; > +... > -- > 2.37.2 > > ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang 2022-11-20 8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang @ 2022-11-20 8:21 ` Jisheng Zhang 2022-11-21 8:09 ` Jiri Slaby 2022-11-21 13:59 ` Ilpo Järvinen 2022-11-20 8:21 ` [PATCH 3/7] MAINTAINERS: add myself as a reviewer for Bouffalolab uart driver Jisheng Zhang ` (4 subsequent siblings) 6 siblings, 2 replies; 27+ messages in thread From: Jisheng Zhang @ 2022-11-20 8:21 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv Add the driver for Bouffalolab UART IP which is found in Bouffalolab SoCs such as bl808. UART driver probe will create path named "/dev/ttySx". Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- drivers/tty/serial/Kconfig | 18 + drivers/tty/serial/Makefile | 1 + drivers/tty/serial/bflb_uart.c | 659 +++++++++++++++++++++++++++++++ include/uapi/linux/serial_core.h | 3 + 4 files changed, 681 insertions(+) create mode 100644 drivers/tty/serial/bflb_uart.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 434f83168546..056a8144e2cc 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -179,6 +179,24 @@ config SERIAL_ATMEL_TTYAT Say Y if you have an external 8250/16C550 UART. If unsure, say N. +config SERIAL_BFLB + tristate "Bouffalolab serial port support" + select SERIAL_CORE + depends on COMMON_CLK + help + This enables the driver for the Bouffalolab's serial. + +config SERIAL_BFLB_CONSOLE + bool "Support for console on Bouffalolab serial port" + depends on SERIAL_BFLB + select SERIAL_CORE_CONSOLE + select SERIAL_EARLYCON + help + Say Y here if you wish to use a Bouffalolab UART as the + system console (the system console is the device which + receives all kernel messages and warnings and which allows + logins in single user mode) as /dev/ttySn. + config SERIAL_KGDB_NMI bool "Serial console over KGDB NMI debugger port" depends on KGDB_SERIAL_CONSOLE diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 238a9557b487..8509cdc11d87 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250/ obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o +obj-$(CONFIG_SERIAL_BFLB) += bflb_uart.o obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o diff --git a/drivers/tty/serial/bflb_uart.c b/drivers/tty/serial/bflb_uart.c new file mode 100644 index 000000000000..65f98ccf8fa8 --- /dev/null +++ b/drivers/tty/serial/bflb_uart.c @@ -0,0 +1,659 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Based on bflb_uart.c, by Bouffalolab team + * + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> + */ + +#include <linux/clk.h> +#include <linux/console.h> +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/serial.h> +#include <linux/serial_core.h> +#include <linux/tty.h> +#include <linux/tty_flip.h> + +#define UART_UTX_CONFIG 0x00 +#define UART_CR_UTX_EN BIT(0) +#define UART_CR_UTX_CTS_EN BIT(1) +#define UART_CR_UTX_FRM_EN BIT(2) +#define UART_CR_UTX_PRT_EN BIT(4) +#define UART_CR_UTX_PRT_SEL BIT(5) +#define UART_CR_UTX_BIT_CNT_D_SFT 8 +#define UART_CR_UTX_BIT_CNT_D_MSK GENMASK(10, 8) +#define UART_CR_UTX_BIT_CNT_P_SFT 11 +#define UART_CR_UTX_BIT_CNT_P_MSK GENMASK(12, 11) +#define UART_URX_CONFIG 0x04 +#define UART_CR_URX_EN BIT(0) +#define UART_CR_URX_PRT_EN BIT(4) +#define UART_CR_URX_PRT_SEL BIT(5) +#define UART_CR_URX_BIT_CNT_D_SFT 8 +#define UART_CR_URX_BIT_CNT_D_MSK GENMASK(10, 8) +#define UART_BIT_PRD 0x08 +#define UART_CR_UTX_BIT_PRD GENMASK(15, 0) +#define UART_CR_URX_BIT_PRD GENMASK(31, 16) +#define UART_DATA_CONFIG 0x0c +#define UART_CR_UART_BIT_INV BIT(0) +#define UART_URX_RTO_TIMER 0x18 +#define UART_CR_URX_RTO_VALUE_MSK GENMASK(7, 0) +#define UART_SW_MODE 0x1c +#define UART_INT_STS (0x20) +#define UART_UTX_END_INT BIT(0) +#define UART_URX_END_INT BIT(1) +#define UART_UTX_FIFO_INT BIT(2) +#define UART_URX_FIFO_INT BIT(3) +#define UART_URX_RTO_INT BIT(4) +#define UART_URX_PCE_INT BIT(5) +#define UART_UTX_FER_INT BIT(6) +#define UART_URX_FER_INT BIT(7) +#define UART_URX_LSE_INT BIT(8) +#define UART_INT_MASK 0x24 +#define UART_INT_CLEAR 0x28 +#define UART_INT_EN 0x2c +#define UART_STATUS 0x30 +#define UART_STS_UTX_BUS_BUSY BIT(0) +#define UART_FIFO_CONFIG_0 (0x80) +#define UART_DMA_TX_EN BIT(0) +#define UART_DMA_RX_EN BIT(1) +#define UART_TX_FIFO_CLR BIT(2) +#define UART_RX_FIFO_CLR BIT(3) +#define UART_TX_FIFO_OVERFLOW BIT(4) +#define UART_TX_FIFO_UNDERFLOW BIT(5) +#define UART_RX_FIFO_OVERFLOW BIT(6) +#define UART_RX_FIFO_UNDERFLOW BIT(7) +#define UART_FIFO_CONFIG_1 (0x84) +#define UART_TX_FIFO_CNT_SFT 0 +#define UART_TX_FIFO_CNT_MSK GENMASK(5, 0) +#define UART_RX_FIFO_CNT_MSK GENMASK(13, 8) +#define UART_TX_FIFO_TH_SFT 16 +#define UART_TX_FIFO_TH_MSK GENMASK(20, 16) +#define UART_RX_FIFO_TH_SFT 24 +#define UART_RX_FIFO_TH_MSK GENMASK(28, 24) +#define UART_FIFO_WDATA 0x88 +#define UART_FIFO_RDATA 0x8c +#define UART_FIFO_RDATA_MSK GENMASK(7, 0) + +#define BFLB_UART_MAXPORTS 8 +#define BFLB_UART_BAUD 2000000 +#define BFLB_UART_RX_FIFO_TH 7 + +struct bflb_uart_port { + struct uart_port port; + struct clk *clk; +}; + +static struct bflb_uart_port *bflb_uart_ports[BFLB_UART_MAXPORTS]; + +static inline u32 rdl(struct uart_port *port, u32 reg) +{ + return readl_relaxed(port->membase + reg); +} + +static inline void wrl(struct uart_port *port, u32 reg, u32 value) +{ + writel_relaxed(value, port->membase + reg); +} + +static inline void wrb(struct uart_port *port, u32 reg, u8 value) +{ + writeb_relaxed(value, port->membase + reg); +} + +static unsigned int bflb_uart_tx_empty(struct uart_port *port) +{ + return (rdl(port, UART_FIFO_CONFIG_1) & UART_TX_FIFO_CNT_MSK) ? TIOCSER_TEMT : 0; +} + +static unsigned int bflb_uart_get_mctrl(struct uart_port *port) +{ + return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS; +} + +static void bflb_uart_set_mctrl(struct uart_port *port, unsigned int sigs) +{ +} + +static void bflb_uart_start_tx(struct uart_port *port) +{ + u32 val; + + val = rdl(port, UART_UTX_CONFIG); + val |= UART_CR_UTX_EN; + wrl(port, UART_UTX_CONFIG, val); + + val = rdl(port, UART_INT_MASK); + val &= ~UART_UTX_END_INT; + wrl(port, UART_INT_MASK, val); + + val = rdl(port, UART_FIFO_CONFIG_1); + val &= ~UART_TX_FIFO_TH_MSK; + val |= 15 << UART_TX_FIFO_TH_SFT; + wrl(port, UART_FIFO_CONFIG_1, val); + + val = rdl(port, UART_INT_MASK); + val &= ~UART_UTX_FIFO_INT; + wrl(port, UART_INT_MASK, val); +} + +static void bflb_uart_stop_tx(struct uart_port *port) +{ + u32 val; + + val = rdl(port, UART_INT_MASK); + val |= UART_UTX_END_INT | UART_UTX_FIFO_INT; + wrl(port, UART_INT_MASK, val); +} + +static void bflb_uart_stop_rx(struct uart_port *port) +{ + u32 val; + + val = rdl(port, UART_URX_CONFIG); + val &= ~UART_CR_URX_EN; + wrl(port, UART_URX_CONFIG, val); + + val = rdl(port, UART_INT_MASK); + val |= UART_URX_FIFO_INT | UART_URX_RTO_INT | + UART_URX_FER_INT; + wrl(port, UART_INT_MASK, val); +} + +static void bflb_uart_break_ctl(struct uart_port *port, int break_state) +{ +} + +static void bflb_uart_set_termios(struct uart_port *port, + struct ktermios *termios, + const struct ktermios *old) +{ + unsigned long flags; + u32 valt, valr, val; + unsigned int baud, min; + + valt = valr = 0; + + spin_lock_irqsave(&port->lock, flags); + + /* set data length */ + val = tty_get_char_size(termios->c_cflag) - 1; + valt |= (val << UART_CR_UTX_BIT_CNT_D_SFT); + + /* calculate parity */ + termios->c_cflag &= ~CMSPAR; /* no support mark/space */ + if (termios->c_cflag & PARENB) { + valt |= UART_CR_UTX_PRT_EN; + if (termios->c_cflag & PARODD) + valr |= UART_CR_UTX_PRT_SEL; + } + + valr = valt; + + /* calculate stop bits */ + if (termios->c_cflag & CSTOPB) + val = 2; + else + val = 1; + valt |= (val << UART_CR_UTX_BIT_CNT_P_SFT); + + /* flow control */ + if (termios->c_cflag & CRTSCTS) + valt |= UART_CR_UTX_CTS_EN; + + /* enable TX freerunning mode */ + valt |= UART_CR_UTX_FRM_EN; + + valt |= UART_CR_UTX_EN; + valr |= UART_CR_URX_EN; + + wrl(port, UART_UTX_CONFIG, valt); + wrl(port, UART_URX_CONFIG, valr); + + min = port->uartclk / (UART_CR_UTX_BIT_PRD + 1); + baud = uart_get_baud_rate(port, termios, old, min, 4000000); + + val = DIV_ROUND_CLOSEST(port->uartclk, baud) - 1; + val &= UART_CR_UTX_BIT_PRD; + val |= (val << 16); + wrl(port, UART_BIT_PRD, val); + + uart_update_timeout(port, termios->c_cflag, baud); + + spin_unlock_irqrestore(&port->lock, flags); +} + +static void bflb_uart_rx_chars(struct uart_port *port) +{ + unsigned char ch, flag; + unsigned long status; + + while ((status = rdl(port, UART_FIFO_CONFIG_1)) & UART_RX_FIFO_CNT_MSK) { + ch = rdl(port, UART_FIFO_RDATA) & UART_FIFO_RDATA_MSK; + flag = TTY_NORMAL; + port->icount.rx++; + + if (uart_handle_sysrq_char(port, ch)) + continue; + uart_insert_char(port, 0, 0, ch, flag); + } + + spin_unlock(&port->lock); + tty_flip_buffer_push(&port->state->port); + spin_lock(&port->lock); +} + +static void bflb_uart_tx_chars(struct uart_port *port) +{ + struct circ_buf *xmit = &port->state->xmit; + unsigned int pending, count; + + if (port->x_char) { + /* Send special char - probably flow control */ + wrl(port, UART_FIFO_WDATA, port->x_char); + port->x_char = 0; + port->icount.tx++; + return; + } + + pending = uart_circ_chars_pending(xmit); + if (pending > 0) { + count = (rdl(port, UART_FIFO_CONFIG_1) & + UART_TX_FIFO_CNT_MSK) >> UART_TX_FIFO_CNT_SFT; + if (count > pending) + count = pending; + if (count > 0) { + pending -= count; + while (count--) { + wrl(port, UART_FIFO_WDATA, xmit->buf[xmit->tail]); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + } + if (pending < WAKEUP_CHARS) + uart_write_wakeup(port); + } + } + + if (pending == 0) + bflb_uart_stop_tx(port); +} + +static irqreturn_t bflb_uart_interrupt(int irq, void *data) +{ + struct uart_port *port = data; + u32 isr, val; + + isr = rdl(port, UART_INT_STS); + wrl(port, UART_INT_CLEAR, isr); + + isr &= ~rdl(port, UART_INT_MASK); + + spin_lock(&port->lock); + + if (isr & UART_URX_FER_INT) { + /* RX FIFO error interrupt */ + val = rdl(port, UART_FIFO_CONFIG_0); + if (val & UART_RX_FIFO_OVERFLOW) + port->icount.overrun++; + + val |= UART_RX_FIFO_CLR; + wrl(port, UART_FIFO_CONFIG_0, val); + } + + if (isr & (UART_URX_FIFO_INT | UART_URX_RTO_INT)) { + bflb_uart_rx_chars(port); + } + if (isr & (UART_UTX_FIFO_INT | UART_UTX_END_INT)) { + bflb_uart_tx_chars(port); + } + + spin_unlock(&port->lock); + + return IRQ_RETVAL(isr); +} + +static void bflb_uart_config_port(struct uart_port *port, int flags) +{ + u32 val; + + port->type = PORT_BFLB; + + /* Clear mask, so no surprise interrupts. */ + val = rdl(port, UART_INT_MASK); + val |= UART_UTX_END_INT; + val |= UART_UTX_FIFO_INT; + val |= UART_URX_FIFO_INT; + val |= UART_URX_RTO_INT; + val |= UART_URX_FER_INT; + wrl(port, UART_INT_MASK, val); +} + +static int bflb_uart_startup(struct uart_port *port) +{ + unsigned long flags; + int ret; + u32 val; + + ret = devm_request_irq(port->dev, port->irq, bflb_uart_interrupt, + IRQF_SHARED, port->name, port); + if (ret) { + dev_err(port->dev, "fail to request serial irq %d, ret=%d\n", + port->irq, ret); + return ret; + } + + spin_lock_irqsave(&port->lock, flags); + + val = rdl(port, UART_INT_MASK); + val |= 0xfff; + wrl(port, UART_INT_MASK, val); + + wrl(port, UART_DATA_CONFIG, 0); + wrl(port, UART_SW_MODE, 0); + wrl(port, UART_URX_RTO_TIMER, 0x4f); + + val = rdl(port, UART_FIFO_CONFIG_1); + val &= ~UART_RX_FIFO_TH_MSK; + val |= BFLB_UART_RX_FIFO_TH << UART_RX_FIFO_TH_SFT; + wrl(port, UART_FIFO_CONFIG_1, val); + + /* Unmask RX interrupts now */ + val = rdl(port, UART_INT_MASK); + val &= ~UART_URX_FIFO_INT; + val &= ~UART_URX_RTO_INT; + val &= ~UART_URX_FER_INT; + wrl(port, UART_INT_MASK, val); + + val = rdl(port, UART_UTX_CONFIG); + val |= UART_CR_UTX_EN; + wrl(port, UART_UTX_CONFIG, val); + val = rdl(port, UART_URX_CONFIG); + val |= UART_CR_URX_EN; + wrl(port, UART_URX_CONFIG, val); + + spin_unlock_irqrestore(&port->lock, flags); + + return 0; +} + +static void bflb_uart_shutdown(struct uart_port *port) +{ + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + /* mask all interrupts now */ + wrl(port, UART_INT_MASK, UART_UTX_END_INT | UART_URX_END_INT); + spin_unlock_irqrestore(&port->lock, flags); +} + +static const char *bflb_uart_type(struct uart_port *port) +{ + return (port->type == PORT_BFLB) ? "BFLB UART" : NULL; +} + +static int bflb_uart_request_port(struct uart_port *port) +{ + /* UARTs always present */ + return 0; +} + +static void bflb_uart_release_port(struct uart_port *port) +{ + /* Nothing to release... */ +} + +static int bflb_uart_verify_port(struct uart_port *port, + struct serial_struct *ser) +{ + if (ser->type != PORT_UNKNOWN && ser->type != PORT_BFLB) + return -EINVAL; + return 0; +} + +static const struct uart_ops bflb_uart_ops = { + .tx_empty = bflb_uart_tx_empty, + .get_mctrl = bflb_uart_get_mctrl, + .set_mctrl = bflb_uart_set_mctrl, + .start_tx = bflb_uart_start_tx, + .stop_tx = bflb_uart_stop_tx, + .stop_rx = bflb_uart_stop_rx, + .break_ctl = bflb_uart_break_ctl, + .startup = bflb_uart_startup, + .shutdown = bflb_uart_shutdown, + .set_termios = bflb_uart_set_termios, + .type = bflb_uart_type, + .request_port = bflb_uart_request_port, + .release_port = bflb_uart_release_port, + .config_port = bflb_uart_config_port, + .verify_port = bflb_uart_verify_port, +}; + +#ifdef CONFIG_SERIAL_BFLB_CONSOLE +static void bflb_console_putchar(struct uart_port *port, unsigned char ch) +{ + while (!(rdl(port, UART_FIFO_CONFIG_1) & UART_TX_FIFO_CNT_MSK)) + cpu_relax(); + wrb(port, UART_FIFO_WDATA, ch); +} + +/* + * Interrupts are disabled on entering + */ +static void bflb_uart_console_write(struct console *co, const char *s, + u_int count) +{ + struct uart_port *port = &bflb_uart_ports[co->index]->port; + u32 status, reg, mask; + + /* save then disable interrupts */ + mask = rdl(port, UART_INT_MASK); + reg = -1; + wrl(port, UART_INT_MASK, reg); + + /* Make sure that tx is enabled */ + reg = rdl(port, UART_UTX_CONFIG); + reg |= UART_CR_UTX_EN; + wrl(port, UART_UTX_CONFIG, reg); + + uart_console_write(port, s, count, bflb_console_putchar); + + /* wait for TX done */ + do { + status = rdl(port, UART_STATUS); + } while ((status & UART_STS_UTX_BUS_BUSY)); + + /* restore IRQ mask */ + wrl(port, UART_INT_MASK, mask); +} + +static int bflb_uart_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + struct bflb_uart_port *bp; + int baud = BFLB_UART_BAUD; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + u32 val; + + if (co->index >= BFLB_UART_MAXPORTS || co->index < 0) + return -EINVAL; + + bp = bflb_uart_ports[co->index]; + if (!bp) + /* Port not initialized yet - delay setup */ + return -ENODEV; + + port = &bp->port; + + val = rdl(port, UART_UTX_CONFIG); + val |= UART_CR_UTX_EN; + wrl(port, UART_UTX_CONFIG, val); + + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct uart_driver bflb_uart_driver; +static struct console bflb_uart_console = { + .name = "ttyS", + .write = bflb_uart_console_write, + .device = uart_console_device, + .setup = bflb_uart_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &bflb_uart_driver, +}; + +static int __init bflb_uart_console_init(void) +{ + register_console(&bflb_uart_console); + return 0; +} +console_initcall(bflb_uart_console_init); + +#define BFLB_UART_CONSOLE (&bflb_uart_console) + +static void bflb_uart_earlycon_write(struct console *co, const char *s, + unsigned int count) +{ + struct earlycon_device *dev = co->data; + + uart_console_write(&dev->port, s, count, bflb_console_putchar); +} + +static int __init bflb_uart_earlycon_setup(struct earlycon_device *dev, + const char *options) +{ + if (!dev->port.membase) + return -ENODEV; + + dev->con->write = bflb_uart_earlycon_write; + + return 0; +} +OF_EARLYCON_DECLARE(bflb_uart, "bouffalolab,uart", bflb_uart_earlycon_setup); + +#else + +#define BFLB_UART_CONSOLE NULL + +#endif /* CONFIG_SERIAL_BFLB_CONSOLE */ + +static struct uart_driver bflb_uart_driver = { + .owner = THIS_MODULE, + .driver_name = "bflb_uart", + .dev_name = "ttyS", + .nr = BFLB_UART_MAXPORTS, + .cons = BFLB_UART_CONSOLE, +}; + +static int bflb_uart_probe(struct platform_device *pdev) +{ + struct uart_port *port; + struct bflb_uart_port *bp; + struct resource *res; + int index, irq; + + index = of_alias_get_id(pdev->dev.of_node, "serial"); + if (unlikely(index < 0 || index >= BFLB_UART_MAXPORTS)) { + dev_err(&pdev->dev, "got a wrong serial alias id %d\n", index); + return -EINVAL; + } + + bp = devm_kzalloc(&pdev->dev, sizeof(*bp), GFP_KERNEL); + if (!bp) + return -ENOMEM; + + bflb_uart_ports[index] = bp; + platform_set_drvdata(pdev, bp); + port = &bp->port; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + port->membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(port->membase)) + return PTR_ERR(port->membase); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + port->mapbase = res->start; + port->irq = irq; + port->line = index; + port->type = PORT_BFLB; + port->iotype = UPIO_MEM; + port->fifosize = 32; + port->ops = &bflb_uart_ops; + port->flags = UPF_BOOT_AUTOCONF; + port->dev = &pdev->dev; + port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_BFLB_CONSOLE); + + bp->clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(bp->clk)) + return PTR_ERR(bp->clk); + port->uartclk = clk_get_rate(bp->clk); + + return uart_add_one_port(&bflb_uart_driver, port); +} + +static int bflb_uart_remove(struct platform_device *pdev) +{ + struct bflb_uart_port *bp = platform_get_drvdata(pdev); + + uart_remove_one_port(&bflb_uart_driver, &bp->port); + bflb_uart_ports[bp->port.line] = NULL; + + return 0; +} + +static const struct of_device_id bflb_uart_match[] = { + { + .compatible = "bouffalolab,uart", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, bflb_uart_match); + +static struct platform_driver bflb_uart_platform_driver = { + .probe = bflb_uart_probe, + .remove = bflb_uart_remove, + .driver = { + .name = "bflb_uart", + .of_match_table = of_match_ptr(bflb_uart_match), + }, +}; + +static int __init bflb_uart_init(void) +{ + int ret; + + ret = uart_register_driver(&bflb_uart_driver); + if (ret) + return ret; + + ret = platform_driver_register(&bflb_uart_platform_driver); + if (ret) + uart_unregister_driver(&bflb_uart_driver); + + return ret; +} + +static void __exit bflb_uart_exit(void) +{ + platform_driver_unregister(&bflb_uart_platform_driver); + uart_unregister_driver(&bflb_uart_driver); +} + +module_init(bflb_uart_init); +module_exit(bflb_uart_exit); + +MODULE_DESCRIPTION("Bouffalolab UART driver"); +MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); +MODULE_LICENSE("GPL"); diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h index 3ba34d8378bd..dabbb5ea2857 100644 --- a/include/uapi/linux/serial_core.h +++ b/include/uapi/linux/serial_core.h @@ -276,4 +276,7 @@ /* Sunplus UART */ #define PORT_SUNPLUS 123 +/* Bouffalolab UART */ +#define PORT_BFLB 124 + #endif /* _UAPILINUX_SERIAL_CORE_H */ -- 2.37.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver 2022-11-20 8:21 ` [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver Jisheng Zhang @ 2022-11-21 8:09 ` Jiri Slaby 2022-11-21 13:59 ` Ilpo Järvinen 1 sibling, 0 replies; 27+ messages in thread From: Jiri Slaby @ 2022-11-21 8:09 UTC (permalink / raw) To: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou Cc: linux-serial, devicetree, linux-kernel, linux-riscv Hi, On 20. 11. 22, 9:21, Jisheng Zhang wrote: > Add the driver for Bouffalolab UART IP which is found in Bouffalolab > SoCs such as bl808. > > UART driver probe will create path named "/dev/ttySx". > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> ... > #define UART_FIFO_CONFIG_0 (0x80) Superfluous parentheses. ... > +static void bflb_uart_set_termios(struct uart_port *port, > + struct ktermios *termios, > + const struct ktermios *old) > +{ > + unsigned long flags; > + u32 valt, valr, val; > + unsigned int baud, min; > + > + valt = valr = 0; Unneeded (see below). > + > + spin_lock_irqsave(&port->lock, flags); > + > + /* set data length */ > + val = tty_get_char_size(termios->c_cflag) - 1; > + valt |= (val << UART_CR_UTX_BIT_CNT_D_SFT); Use =, not |=. Other than that, can FIELD_SET() be used, provided you already define the constants using GENMASK()? > + > + /* calculate parity */ > + termios->c_cflag &= ~CMSPAR; /* no support mark/space */ > + if (termios->c_cflag & PARENB) { > + valt |= UART_CR_UTX_PRT_EN; > + if (termios->c_cflag & PARODD) > + valr |= UART_CR_UTX_PRT_SEL; This should be valt, IMO. > + } > + > + valr = valt; If not, this doesn't make sense to me. > + /* calculate stop bits */ > + if (termios->c_cflag & CSTOPB) > + val = 2; > + else > + val = 1; > + valt |= (val << UART_CR_UTX_BIT_CNT_P_SFT); > + > + /* flow control */ > + if (termios->c_cflag & CRTSCTS) > + valt |= UART_CR_UTX_CTS_EN; > + > + /* enable TX freerunning mode */ > + valt |= UART_CR_UTX_FRM_EN; > + > + valt |= UART_CR_UTX_EN; > + valr |= UART_CR_URX_EN; Why this is not the very first and only for valt and copied to valr above? > + > + wrl(port, UART_UTX_CONFIG, valt); > + wrl(port, UART_URX_CONFIG, valr); > + > + min = port->uartclk / (UART_CR_UTX_BIT_PRD + 1); > + baud = uart_get_baud_rate(port, termios, old, min, 4000000); > + > + val = DIV_ROUND_CLOSEST(port->uartclk, baud) - 1; > + val &= UART_CR_UTX_BIT_PRD; > + val |= (val << 16); > + wrl(port, UART_BIT_PRD, val); > + > + uart_update_timeout(port, termios->c_cflag, baud); > + > + spin_unlock_irqrestore(&port->lock, flags); > +} > + > +static void bflb_uart_rx_chars(struct uart_port *port) > +{ > + unsigned char ch, flag; Please use u8. (serial_core should too, but that's only on a TODO list yet) > + unsigned long status; Long? I think u32. > + > + while ((status = rdl(port, UART_FIFO_CONFIG_1)) & UART_RX_FIFO_CNT_MSK) { > + ch = rdl(port, UART_FIFO_RDATA) & UART_FIFO_RDATA_MSK; > + flag = TTY_NORMAL; Drop this flag completely and use the constant below directly. > + port->icount.rx++; > + > + if (uart_handle_sysrq_char(port, ch)) > + continue; > + uart_insert_char(port, 0, 0, ch, flag); > + } > + > + spin_unlock(&port->lock); > + tty_flip_buffer_push(&port->state->port); > + spin_lock(&port->lock); > +} > + > +static void bflb_uart_tx_chars(struct uart_port *port) > +{ Are you unable to use the TX helper? If so: * why? * use uart_advance_xmit() at least. > + struct circ_buf *xmit = &port->state->xmit; > + unsigned int pending, count; > + > + if (port->x_char) { > + /* Send special char - probably flow control */ > + wrl(port, UART_FIFO_WDATA, port->x_char); > + port->x_char = 0; > + port->icount.tx++; > + return; > + } > + > + pending = uart_circ_chars_pending(xmit); > + if (pending > 0) { > + count = (rdl(port, UART_FIFO_CONFIG_1) & > + UART_TX_FIFO_CNT_MSK) >> UART_TX_FIFO_CNT_SFT; > + if (count > pending) > + count = pending; > + if (count > 0) { > + pending -= count; > + while (count--) { > + wrl(port, UART_FIFO_WDATA, xmit->buf[xmit->tail]); > + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); > + port->icount.tx++; > + } > + if (pending < WAKEUP_CHARS) > + uart_write_wakeup(port); > + } > + } > + > + if (pending == 0) > + bflb_uart_stop_tx(port); > +} > + > +static irqreturn_t bflb_uart_interrupt(int irq, void *data) > +{ > + struct uart_port *port = data; > + u32 isr, val; > + > + isr = rdl(port, UART_INT_STS); > + wrl(port, UART_INT_CLEAR, isr); > + > + isr &= ~rdl(port, UART_INT_MASK); > + > + spin_lock(&port->lock); > + > + if (isr & UART_URX_FER_INT) { > + /* RX FIFO error interrupt */ > + val = rdl(port, UART_FIFO_CONFIG_0); > + if (val & UART_RX_FIFO_OVERFLOW) > + port->icount.overrun++; > + > + val |= UART_RX_FIFO_CLR; > + wrl(port, UART_FIFO_CONFIG_0, val); > + } > + > + if (isr & (UART_URX_FIFO_INT | UART_URX_RTO_INT)) { > + bflb_uart_rx_chars(port); > + } > + if (isr & (UART_UTX_FIFO_INT | UART_UTX_END_INT)) { > + bflb_uart_tx_chars(port); > + } Superfluous braces. > + > + spin_unlock(&port->lock); > + > + return IRQ_RETVAL(isr); Can it happen that UART_INT_STS is nonzero and UART_INT_MASK is zero? You'd cause "irqX: nobody cared" in that case. > +} > + > +static void bflb_uart_config_port(struct uart_port *port, int flags) > +{ > + u32 val; > + > + port->type = PORT_BFLB; > + > + /* Clear mask, so no surprise interrupts. */ surprising? > + val = rdl(port, UART_INT_MASK); > + val |= UART_UTX_END_INT; > + val |= UART_UTX_FIFO_INT; > + val |= UART_URX_FIFO_INT; > + val |= UART_URX_RTO_INT; > + val |= UART_URX_FER_INT; > + wrl(port, UART_INT_MASK, val); > +} > + > +static int bflb_uart_startup(struct uart_port *port) > +{ > + unsigned long flags; > + int ret; > + u32 val; > + > + ret = devm_request_irq(port->dev, port->irq, bflb_uart_interrupt, > + IRQF_SHARED, port->name, port); > + if (ret) { > + dev_err(port->dev, "fail to request serial irq %d, ret=%d\n", > + port->irq, ret); > + return ret; > + } > + > + spin_lock_irqsave(&port->lock, flags); > + > + val = rdl(port, UART_INT_MASK); > + val |= 0xfff; Can this be a defined macro too, please? > + wrl(port, UART_INT_MASK, val); > + > + wrl(port, UART_DATA_CONFIG, 0); > + wrl(port, UART_SW_MODE, 0); > + wrl(port, UART_URX_RTO_TIMER, 0x4f); Another magic constant. > + > + val = rdl(port, UART_FIFO_CONFIG_1); > + val &= ~UART_RX_FIFO_TH_MSK; > + val |= BFLB_UART_RX_FIFO_TH << UART_RX_FIFO_TH_SFT; FIELD_SET()? > + wrl(port, UART_FIFO_CONFIG_1, val); > + > + /* Unmask RX interrupts now */ > + val = rdl(port, UART_INT_MASK); > + val &= ~UART_URX_FIFO_INT; > + val &= ~UART_URX_RTO_INT; > + val &= ~UART_URX_FER_INT; > + wrl(port, UART_INT_MASK, val); > + val = rdl(port, UART_UTX_CONFIG); > + val |= UART_CR_UTX_EN; > + wrl(port, UART_UTX_CONFIG, val); > + val = rdl(port, UART_URX_CONFIG); > + val |= UART_CR_URX_EN; > + wrl(port, UART_URX_CONFIG, val); > + > + spin_unlock_irqrestore(&port->lock, flags); > + > + return 0; > +} ... > +/* > + * Interrupts are disabled on entering > + */ > +static void bflb_uart_console_write(struct console *co, const char *s, > + u_int count) > +{ > + struct uart_port *port = &bflb_uart_ports[co->index]->port; > + u32 status, reg, mask; > + > + /* save then disable interrupts */ > + mask = rdl(port, UART_INT_MASK); > + reg = -1; You use 0xfff earlier, now 0xffffffff. Is that OK? Why not use the same constant? > + wrl(port, UART_INT_MASK, reg); > + > + /* Make sure that tx is enabled */ > + reg = rdl(port, UART_UTX_CONFIG); > + reg |= UART_CR_UTX_EN; > + wrl(port, UART_UTX_CONFIG, reg); > + > + uart_console_write(port, s, count, bflb_console_putchar); > + > + /* wait for TX done */ > + do { > + status = rdl(port, UART_STATUS); > + } while ((status & UART_STS_UTX_BUS_BUSY)); > + > + /* restore IRQ mask */ > + wrl(port, UART_INT_MASK, mask); > +} regards, -- js suse labs ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver 2022-11-20 8:21 ` [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver Jisheng Zhang 2022-11-21 8:09 ` Jiri Slaby @ 2022-11-21 13:59 ` Ilpo Järvinen 1 sibling, 0 replies; 27+ messages in thread From: Ilpo Järvinen @ 2022-11-21 13:59 UTC (permalink / raw) To: Jisheng Zhang Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, LKML, linux-riscv On Sun, 20 Nov 2022, Jisheng Zhang wrote: > Add the driver for Bouffalolab UART IP which is found in Bouffalolab > SoCs such as bl808. > > UART driver probe will create path named "/dev/ttySx". > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile > index 238a9557b487..8509cdc11d87 100644 > --- a/drivers/tty/serial/Makefile > +++ b/drivers/tty/serial/Makefile > @@ -25,6 +25,7 @@ obj-$(CONFIG_SERIAL_8250) += 8250/ > > obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o > obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o > +obj-$(CONFIG_SERIAL_BFLB) += bflb_uart.o > obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o > obj-$(CONFIG_SERIAL_PXA_NON8250) += pxa.o > obj-$(CONFIG_SERIAL_SA1100) += sa1100.o > diff --git a/drivers/tty/serial/bflb_uart.c b/drivers/tty/serial/bflb_uart.c > new file mode 100644 > index 000000000000..65f98ccf8fa8 > --- /dev/null > +++ b/drivers/tty/serial/bflb_uart.c > @@ -0,0 +1,659 @@ > +#define UART_FIFO_CONFIG_1 (0x84) > +#define UART_TX_FIFO_CNT_SFT 0 > +#define UART_TX_FIFO_CNT_MSK GENMASK(5, 0) > +#define UART_RX_FIFO_CNT_MSK GENMASK(13, 8) > +#define UART_TX_FIFO_TH_SFT 16 Use FIELD_PREP() instead of adding a separate *_SFT define. > +#define UART_TX_FIFO_TH_MSK GENMASK(20, 16) > +#define UART_RX_FIFO_TH_SFT 24 > +#define UART_RX_FIFO_TH_MSK GENMASK(28, 24) > +#define UART_FIFO_WDATA 0x88 > +#define UART_FIFO_RDATA 0x8c > +#define UART_FIFO_RDATA_MSK GENMASK(7, 0) > + val = rdl(port, UART_URX_CONFIG); > + val &= ~UART_CR_URX_EN; > + wrl(port, UART_URX_CONFIG, val); > + > + val = rdl(port, UART_INT_MASK); > + val |= UART_URX_FIFO_INT | UART_URX_RTO_INT | > + UART_URX_FER_INT; Fits to single line. > + port->type = PORT_BFLB; > + > + /* Clear mask, so no surprise interrupts. */ > + val = rdl(port, UART_INT_MASK); > + val |= UART_UTX_END_INT; > + val |= UART_UTX_FIFO_INT; > + val |= UART_URX_FIFO_INT; > + val |= UART_URX_RTO_INT; > + val |= UART_URX_FER_INT; Why to split it to this many lines? > + spin_lock_irqsave(&port->lock, flags); > + > + val = rdl(port, UART_INT_MASK); > + val |= 0xfff; In most of the other places, the bits used with UART_INT_MASK are named, but for some reason you don't do it here and the bits extend beyond the ones which are defined with name. > + wrl(port, UART_INT_MASK, val); > + > + wrl(port, UART_DATA_CONFIG, 0); > + wrl(port, UART_SW_MODE, 0); > + wrl(port, UART_URX_RTO_TIMER, 0x4f); FIELD_PREP(UART_CR_URX_RTO_VALUE_MSK, 0x4f)? It would document what field is written explicitly. > + > + val = rdl(port, UART_FIFO_CONFIG_1); > + val &= ~UART_RX_FIFO_TH_MSK; > + val |= BFLB_UART_RX_FIFO_TH << UART_RX_FIFO_TH_SFT; > + wrl(port, UART_FIFO_CONFIG_1, val); > + > + /* Unmask RX interrupts now */ > + val = rdl(port, UART_INT_MASK); > + val &= ~UART_URX_FIFO_INT; > + val &= ~UART_URX_RTO_INT; > + val &= ~UART_URX_FER_INT; Combine to single line. > +static int bflb_uart_request_port(struct uart_port *port) > +{ > + /* UARTs always present */ > + return 0; > +} > +static void bflb_uart_release_port(struct uart_port *port) > +{ > + /* Nothing to release... */ > +} Both release_port and request_port are NULL checked by the caller, there's no need to provide and empty one. > +static const struct uart_ops bflb_uart_ops = { > + .tx_empty = bflb_uart_tx_empty, > + .get_mctrl = bflb_uart_get_mctrl, > + .set_mctrl = bflb_uart_set_mctrl, > + .start_tx = bflb_uart_start_tx, > + .stop_tx = bflb_uart_stop_tx, > + .stop_rx = bflb_uart_stop_rx, > + .break_ctl = bflb_uart_break_ctl, > + .startup = bflb_uart_startup, > + .shutdown = bflb_uart_shutdown, > + .set_termios = bflb_uart_set_termios, > + .type = bflb_uart_type, > + .request_port = bflb_uart_request_port, > + .release_port = bflb_uart_release_port, > + .config_port = bflb_uart_config_port, > + .verify_port = bflb_uart_verify_port, > +}; > +static void bflb_uart_console_write(struct console *co, const char *s, > + u_int count) > +{ > + struct uart_port *port = &bflb_uart_ports[co->index]->port; > + u32 status, reg, mask; > + > + /* save then disable interrupts */ > + mask = rdl(port, UART_INT_MASK); > + reg = -1; Use ~0 instead. Why -1 here and 0xfff in the other place? -- i. ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 3/7] MAINTAINERS: add myself as a reviewer for Bouffalolab uart driver 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang 2022-11-20 8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang 2022-11-20 8:21 ` [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver Jisheng Zhang @ 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 8:21 ` [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang ` (3 subsequent siblings) 6 siblings, 0 replies; 27+ messages in thread From: Jisheng Zhang @ 2022-11-20 8:21 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv I want to maintain this Bouffalolab uart driver from now on. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2585e7edc335..92451834b940 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3718,6 +3718,12 @@ S: Maintained F: Documentation/devicetree/bindings/iio/accel/bosch,bma400.yaml F: drivers/iio/accel/bma400* +BOUFFALOLAB UART DRIVER +M: Jisheng Zhang <jszhang@kernel.org> +S: Maintained +F: Documentation/devicetree/bindings/serial/bouffalolab,uart.yaml +F: drivers/tty/serial/bflb_uart.c + BPF [GENERAL] (Safe Dynamic Programs and Tools) M: Alexei Starovoitov <ast@kernel.org> M: Daniel Borkmann <daniel@iogearbox.net> -- 2.37.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang ` (2 preceding siblings ...) 2022-11-20 8:21 ` [PATCH 3/7] MAINTAINERS: add myself as a reviewer for Bouffalolab uart driver Jisheng Zhang @ 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 10:43 ` Conor Dooley 2022-11-20 8:21 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang ` (2 subsequent siblings) 6 siblings, 1 reply; 27+ messages in thread From: Jisheng Zhang @ 2022-11-20 8:21 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and LP. The D0 is 64bit RISC-V GC compatible, so can run linux. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..90256f44ed4a 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,11 @@ menu "SoC selection" +config SOC_BOUFFALOLAB + bool "Bouffalolab SoCs" + select SIFIVE_PLIC + help + This enables support for Bouffalolab SoC platforms. + config SOC_MICROCHIP_POLARFIRE bool "Microchip PolarFire SoCs" select MCHP_CLK_MPFS -- 2.37.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option 2022-11-20 8:21 ` [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang @ 2022-11-20 10:43 ` Conor Dooley 0 siblings, 0 replies; 27+ messages in thread From: Conor Dooley @ 2022-11-20 10:43 UTC (permalink / raw) To: Jisheng Zhang Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, Nov 20, 2022 at 04:21:11PM +0800, Jisheng Zhang wrote: > The Bouffalolab bl808 SoC contains three riscv CPUs, namely M0, D0 and > LP. The D0 is 64bit RISC-V GC compatible, so can run linux. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Could you also add this new SOC_BOUFFALOLAB symbol to defconfig please? > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/Kconfig.socs | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs > index 69774bb362d6..90256f44ed4a 100644 > --- a/arch/riscv/Kconfig.socs > +++ b/arch/riscv/Kconfig.socs > @@ -1,5 +1,11 @@ > menu "SoC selection" > > +config SOC_BOUFFALOLAB > + bool "Bouffalolab SoCs" > + select SIFIVE_PLIC > + help > + This enables support for Bouffalolab SoC platforms. > + > config SOC_MICROCHIP_POLARFIRE > bool "Microchip PolarFire SoCs" > select MCHP_CLK_MPFS > -- > 2.37.2 > ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang ` (3 preceding siblings ...) 2022-11-20 8:21 ` [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang @ 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 11:02 ` Conor Dooley ` (2 more replies) 2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang 2022-11-20 8:21 ` [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Jisheng Zhang 6 siblings, 3 replies; 27+ messages in thread From: Jisheng Zhang @ 2022-11-20 8:21 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv Add a baisc dtsi for the bouffalolab bl808 SoC. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b525467152b2 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 +subdir-y += bouffalolab subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi new file mode 100644 index 000000000000..c98ebb14ee10 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> + */ + +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + compatible = "bouffalolab,bl808"; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + timebase-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <256>; + d-cache-size = <32768>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + ranges; + interrupt-parent = <&plic>; + dma-noncoherent; + #address-cells = <1>; + #size-cells = <1>; + + uart0: serial@30002000 { + compatible = "bouffalolab,uart"; + reg = <0x30002000 0x1000>; + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&xtal>; + status = "disabled"; + }; + + plic: interrupt-controller@e0000000 { + compatible = "thead,c900-plic"; + reg = <0xe0000000 0x4000000>; + interrupts-extended = <&cpu0_intc 0xffffffff>, + <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <64>; + }; + }; +}; -- 2.37.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 8:21 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang @ 2022-11-20 11:02 ` Conor Dooley 2022-11-20 11:58 ` Icenowy Zheng 2022-11-20 14:57 ` Emil Renner Berthing 2022-11-21 10:09 ` Krzysztof Kozlowski 2 siblings, 1 reply; 27+ messages in thread From: Conor Dooley @ 2022-11-20 11:02 UTC (permalink / raw) To: Jisheng Zhang Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 2 files changed, 75 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b525467152b2 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += bouffalolab > subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..c98ebb14ee10 > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; So this is not yet defined as the dt etc for the d1 has not yet landed. I think I will go pick up that patch for v6.2 as it should make everyone's life easier. Without that, dtbs_check produces: arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtb:0:0: /cpus/cpu@0: failed to match any schema with compatible: ['thead,c906', 'riscv'] > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + clock-frequency = <40000000>; > + clock-output-names = "xtal"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { > + compatible = "bouffalolab,uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; Hmm, this one fails validation too. Likely you need to add a "bouffalolab,plic" to the plic dt-binding or otherwise modify the binding such that thead,c900-plic on it's own is permitted. CC Samuel on that patch please in case he has an opinion on it. Also, I've taken over picking up the misc dt stuff that Palmer used to apply - so canaan, starfive & sifive stuff. Do you intended sending PRs to Arnd for this stuff, or would you like to me bundle it with what I am going to be sending anyway? Thanks, Conor. > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; > + }; > + }; > +}; > -- > 2.37.2 > ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 11:02 ` Conor Dooley @ 2022-11-20 11:58 ` Icenowy Zheng 2022-11-20 14:28 ` Conor Dooley 0 siblings, 1 reply; 27+ messages in thread From: Icenowy Zheng @ 2022-11-20 11:58 UTC (permalink / raw) To: Conor Dooley, Jisheng Zhang Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv 在 2022-11-20星期日的 11:02 +0000,Conor Dooley写道: > On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote: > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > ++++++++++++++++++++++ > > 2 files changed, 75 insertions(+) > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > diff --git a/arch/riscv/boot/dts/Makefile > > b/arch/riscv/boot/dts/Makefile > > index ff174996cdfd..b525467152b2 100644 > > --- a/arch/riscv/boot/dts/Makefile > > +++ b/arch/riscv/boot/dts/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > +subdir-y += bouffalolab > > subdir-y += sifive > > subdir-y += starfive > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > new file mode 100644 > > index 000000000000..c98ebb14ee10 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > @@ -0,0 +1,74 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > +/* > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + compatible = "bouffalolab,bl808"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + timebase-frequency = <1000000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + compatible = "thead,c906", "riscv"; > > So this is not yet defined as the dt etc for the d1 has not yet > landed. > I think I will go pick up that patch for v6.2 as it should make > everyone's life easier. > > Without that, dtbs_check produces: > arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtb:0:0: > /cpus/cpu@0: failed to match any schema with compatible: > ['thead,c906', 'riscv'] > > > + device_type = "cpu"; > > + reg = <0>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <256>; > > + d-cache-size = <32768>; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <32768>; > > + mmu-type = "riscv,sv39"; > > + riscv,isa = "rv64imafdc"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + }; > > + > > + xtal: xtal-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <40000000>; > > + clock-output-names = "xtal"; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + ranges; > > + interrupt-parent = <&plic>; > > + dma-noncoherent; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + uart0: serial@30002000 { > > + compatible = "bouffalolab,uart"; > > + reg = <0x30002000 0x1000>; > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&xtal>; > > + status = "disabled"; > > + }; > > + > > + plic: interrupt-controller@e0000000 { > > + compatible = "thead,c900-plic"; > > Hmm, this one fails validation too. Likely you need to add a > "bouffalolab,plic" to the plic dt-binding or otherwise modify the > binding such that thead,c900-plic on it's own is permitted. CC Samuel > on > that patch please in case he has an opinion on it. Personally I prefer a single c900-plic in compatible, because the PLIC doesn't look so configurable in C906/C910 (the interrupt source number is really adjustable, but it's already in the riscv,ndev property). > > Also, I've taken over picking up the misc dt stuff that Palmer used > to > apply - so canaan, starfive & sifive stuff. Do you intended sending > PRs > to Arnd for this stuff, or would you like to me bundle it with what I > am > going to be sending anyway? > > Thanks, > Conor. > > > + reg = <0xe0000000 0x4000000>; > > + interrupts-extended = <&cpu0_intc > > 0xffffffff>, > > + <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <2>; > > + riscv,ndev = <64>; > > + }; > > + }; > > +}; > > -- > > 2.37.2 > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 11:58 ` Icenowy Zheng @ 2022-11-20 14:28 ` Conor Dooley 0 siblings, 0 replies; 27+ messages in thread From: Conor Dooley @ 2022-11-20 14:28 UTC (permalink / raw) To: Icenowy Zheng Cc: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, Nov 20, 2022 at 07:58:56PM +0800, Icenowy Zheng wrote: > 在 2022-11-20星期日的 11:02 +0000,Conor Dooley写道: > > On Sun, Nov 20, 2022 at 04:21:12PM +0800, Jisheng Zhang wrote: > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > + plic: interrupt-controller@e0000000 { > > > + compatible = "thead,c900-plic"; > > > > Hmm, this one fails validation too. Likely you need to add a > > "bouffalolab,plic" to the plic dt-binding or otherwise modify the > > binding such that thead,c900-plic on it's own is permitted. CC Samuel > > on > > that patch please in case he has an opinion on it. > > Personally I prefer a single c900-plic in compatible, because the PLIC > doesn't look so configurable in C906/C910 (the interrupt source number > is really adjustable, but it's already in the riscv,ndev property). Right, if all implementations are going to be identical (modulo the riscv,ndev) allowing thead,c900-plic in isolation makes sense to me. I had a bit of a check in the history & it looks like there was no explanation given for why the D1 needed a specific compatible (although there's no harm in having one in case something comes up in the future that'd require special handling for a given implementation). ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 8:21 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang 2022-11-20 11:02 ` Conor Dooley @ 2022-11-20 14:57 ` Emil Renner Berthing 2022-11-20 17:51 ` Conor Dooley 2022-11-21 3:36 ` Icenowy Zheng 2022-11-21 10:09 ` Krzysztof Kozlowski 2 siblings, 2 replies; 27+ messages in thread From: Emil Renner Berthing @ 2022-11-20 14:57 UTC (permalink / raw) To: Jisheng Zhang Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote: > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 2 files changed, 75 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b525467152b2 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += bouffalolab > subdir-y += sifive > subdir-y += starfive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > new file mode 100644 > index 000000000000..c98ebb14ee10 > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > @@ -0,0 +1,74 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +#include <dt-bindings/interrupt-controller/irq.h> > + > +/ { > + compatible = "bouffalolab,bl808"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus { > + timebase-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <256>; > + d-cache-size = <32768>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + xtal: xtal-clk { > + compatible = "fixed-clock"; > + clock-frequency = <40000000>; This was discussed many times before, but I think the conclusion was that the frequency is a property of the crystal on the board, so this should be 0 in the SoC dtsi, and then overwritten in the board device tree. > + clock-output-names = "xtal"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + ranges; > + interrupt-parent = <&plic>; > + dma-noncoherent; > + #address-cells = <1>; > + #size-cells = <1>; > + > + uart0: serial@30002000 { > + compatible = "bouffalolab,uart"; > + reg = <0x30002000 0x1000>; > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&xtal>; > + status = "disabled"; > + }; > + > + plic: interrupt-controller@e0000000 { > + compatible = "thead,c900-plic"; > + reg = <0xe0000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 0xffffffff>, > + <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <64>; > + }; > + }; > +}; > -- > 2.37.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 14:57 ` Emil Renner Berthing @ 2022-11-20 17:51 ` Conor Dooley 2022-11-20 18:33 ` Emil Renner Berthing 2022-11-21 3:36 ` Icenowy Zheng 1 sibling, 1 reply; 27+ messages in thread From: Conor Dooley @ 2022-11-20 17:51 UTC (permalink / raw) To: Emil Renner Berthing Cc: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, Nov 20, 2022 at 03:57:17PM +0100, Emil Renner Berthing wrote: > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote: > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > + xtal: xtal-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <40000000>; > > This was discussed many times before, but I think the conclusion was > that the frequency is a property of the crystal on the board, so this > should be 0 in the SoC dtsi, and then overwritten in the board device > tree. Or set nothing in soc.dtsi so that dtbs_check can be used to see if someone forgot to set a clock for their board? > > + clock-output-names = "xtal"; > > + #clock-cells = <0>; > > + }; ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 17:51 ` Conor Dooley @ 2022-11-20 18:33 ` Emil Renner Berthing 0 siblings, 0 replies; 27+ messages in thread From: Emil Renner Berthing @ 2022-11-20 18:33 UTC (permalink / raw) To: Conor Dooley Cc: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, 20 Nov 2022 at 18:51, Conor Dooley <conor@kernel.org> wrote: > > On Sun, Nov 20, 2022 at 03:57:17PM +0100, Emil Renner Berthing wrote: > > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> wrote: > > > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > + xtal: xtal-clk { > > > + compatible = "fixed-clock"; > > > + clock-frequency = <40000000>; > > > > This was discussed many times before, but I think the conclusion was > > that the frequency is a property of the crystal on the board, so this > > should be 0 in the SoC dtsi, and then overwritten in the board device > > tree. > > Or set nothing in soc.dtsi so that dtbs_check can be used to see if > someone forgot to set a clock for their board? Sure. That sounds even better. > > > + clock-output-names = "xtal"; > > > + #clock-cells = <0>; > > > + }; > ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 14:57 ` Emil Renner Berthing 2022-11-20 17:51 ` Conor Dooley @ 2022-11-21 3:36 ` Icenowy Zheng 2022-11-21 11:25 ` Emil Renner Berthing 1 sibling, 1 reply; 27+ messages in thread From: Icenowy Zheng @ 2022-11-21 3:36 UTC (permalink / raw) To: Emil Renner Berthing, Jisheng Zhang Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv 在 2022-11-20星期日的 15:57 +0100,Emil Renner Berthing写道: > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> > wrote: > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > ++++++++++++++++++++++ > > 2 files changed, 75 insertions(+) > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > diff --git a/arch/riscv/boot/dts/Makefile > > b/arch/riscv/boot/dts/Makefile > > index ff174996cdfd..b525467152b2 100644 > > --- a/arch/riscv/boot/dts/Makefile > > +++ b/arch/riscv/boot/dts/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > +subdir-y += bouffalolab > > subdir-y += sifive > > subdir-y += starfive > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > new file mode 100644 > > index 000000000000..c98ebb14ee10 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > @@ -0,0 +1,74 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > +/* > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > + */ > > + > > +#include <dt-bindings/interrupt-controller/irq.h> > > + > > +/ { > > + compatible = "bouffalolab,bl808"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + cpus { > > + timebase-frequency = <1000000>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu0: cpu@0 { > > + compatible = "thead,c906", "riscv"; > > + device_type = "cpu"; > > + reg = <0>; > > + d-cache-block-size = <64>; > > + d-cache-sets = <256>; > > + d-cache-size = <32768>; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <32768>; > > + mmu-type = "riscv,sv39"; > > + riscv,isa = "rv64imafdc"; > > + > > + cpu0_intc: interrupt-controller { > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <1>; > > + }; > > + }; > > + }; > > + > > + xtal: xtal-clk { > > + compatible = "fixed-clock"; > > + clock-frequency = <40000000>; > > This was discussed many times before, but I think the conclusion was > that the frequency is a property of the crystal on the board, so this > should be 0 in the SoC dtsi, and then overwritten in the board device > tree. But many chips just specify an accepted frequency in their datasheet, and using a frequency other than this is undefined behavior. > > > + clock-output-names = "xtal"; > > + #clock-cells = <0>; > > + }; > > + > > + soc { > > + compatible = "simple-bus"; > > + ranges; > > + interrupt-parent = <&plic>; > > + dma-noncoherent; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + uart0: serial@30002000 { > > + compatible = "bouffalolab,uart"; > > + reg = <0x30002000 0x1000>; > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&xtal>; > > + status = "disabled"; > > + }; > > + > > + plic: interrupt-controller@e0000000 { > > + compatible = "thead,c900-plic"; > > + reg = <0xe0000000 0x4000000>; > > + interrupts-extended = <&cpu0_intc > > 0xffffffff>, > > + <&cpu0_intc 9>; > > + interrupt-controller; > > + #address-cells = <0>; > > + #interrupt-cells = <2>; > > + riscv,ndev = <64>; > > + }; > > + }; > > +}; > > -- > > 2.37.2 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-21 3:36 ` Icenowy Zheng @ 2022-11-21 11:25 ` Emil Renner Berthing 0 siblings, 0 replies; 27+ messages in thread From: Emil Renner Berthing @ 2022-11-21 11:25 UTC (permalink / raw) To: Icenowy Zheng Cc: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Mon, 21 Nov 2022 at 04:37, Icenowy Zheng <uwu@icenowy.me> wrote: > > 在 2022-11-20星期日的 15:57 +0100,Emil Renner Berthing写道: > > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang <jszhang@kernel.org> > > wrote: > > > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > > > --- > > > arch/riscv/boot/dts/Makefile | 1 + > > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > > ++++++++++++++++++++++ > > > 2 files changed, 75 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/Makefile > > > b/arch/riscv/boot/dts/Makefile > > > index ff174996cdfd..b525467152b2 100644 > > > --- a/arch/riscv/boot/dts/Makefile > > > +++ b/arch/riscv/boot/dts/Makefile > > > @@ -1,4 +1,5 @@ > > > # SPDX-License-Identifier: GPL-2.0 > > > +subdir-y += bouffalolab > > > subdir-y += sifive > > > subdir-y += starfive > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > new file mode 100644 > > > index 000000000000..c98ebb14ee10 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > @@ -0,0 +1,74 @@ > > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > > +/* > > > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > > > + */ > > > + > > > +#include <dt-bindings/interrupt-controller/irq.h> > > > + > > > +/ { > > > + compatible = "bouffalolab,bl808"; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + cpus { > > > + timebase-frequency = <1000000>; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu0: cpu@0 { > > > + compatible = "thead,c906", "riscv"; > > > + device_type = "cpu"; > > > + reg = <0>; > > > + d-cache-block-size = <64>; > > > + d-cache-sets = <256>; > > > + d-cache-size = <32768>; > > > + i-cache-block-size = <64>; > > > + i-cache-sets = <128>; > > > + i-cache-size = <32768>; > > > + mmu-type = "riscv,sv39"; > > > + riscv,isa = "rv64imafdc"; > > > + > > > + cpu0_intc: interrupt-controller { > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <1>; > > > + }; > > > + }; > > > + }; > > > + > > > + xtal: xtal-clk { > > > + compatible = "fixed-clock"; > > > + clock-frequency = <40000000>; > > > > This was discussed many times before, but I think the conclusion was > > that the frequency is a property of the crystal on the board, so this > > should be 0 in the SoC dtsi, and then overwritten in the board device > > tree. > > But many chips just specify an accepted frequency in their datasheet, > and using a frequency other than this is undefined behavior. Yes, this was the argument in previous discussions, but the conclusion was still that it should go in the board dts. To be clear I'm just summing up the conclusion from previous discussions about this, and have no strong opinion other than we should do the same everywhere. > > > > > + clock-output-names = "xtal"; > > > + #clock-cells = <0>; > > > + }; > > > + > > > + soc { > > > + compatible = "simple-bus"; > > > + ranges; > > > + interrupt-parent = <&plic>; > > > + dma-noncoherent; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + > > > + uart0: serial@30002000 { > > > + compatible = "bouffalolab,uart"; > > > + reg = <0x30002000 0x1000>; > > > + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks = <&xtal>; > > > + status = "disabled"; > > > + }; > > > + > > > + plic: interrupt-controller@e0000000 { > > > + compatible = "thead,c900-plic"; > > > + reg = <0xe0000000 0x4000000>; > > > + interrupts-extended = <&cpu0_intc > > > 0xffffffff>, > > > + <&cpu0_intc 9>; > > > + interrupt-controller; > > > + #address-cells = <0>; > > > + #interrupt-cells = <2>; > > > + riscv,ndev = <64>; > > > + }; > > > + }; > > > +}; > > > -- > > > 2.37.2 > > > > > > > > > _______________________________________________ > > > linux-riscv mailing list > > > linux-riscv@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree 2022-11-20 8:21 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang 2022-11-20 11:02 ` Conor Dooley 2022-11-20 14:57 ` Emil Renner Berthing @ 2022-11-21 10:09 ` Krzysztof Kozlowski 2 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2022-11-21 10:09 UTC (permalink / raw) To: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv On 20/11/2022 09:21, Jisheng Zhang wrote: > Add a baisc dtsi for the bouffalolab bl808 SoC. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 ++++++++++++++++++++++ > 2 files changed, 75 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index ff174996cdfd..b525467152b2 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,4 +1,5 @@ > # SPDX-License-Identifier: GPL-2.0 > +subdir-y += bouffalolab Nothing to build there, so not yet. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang ` (4 preceding siblings ...) 2022-11-20 8:21 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang @ 2022-11-20 8:21 ` Jisheng Zhang 2022-11-20 11:09 ` Conor Dooley ` (3 more replies) 2022-11-20 8:21 ` [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Jisheng Zhang 6 siblings, 4 replies; 27+ messages in thread From: Jisheng Zhang @ 2022-11-20 8:21 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv Sipeed manufactures a M1S system-on-module and dock board, add basic support for them. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- arch/riscv/boot/dts/bouffalolab/Makefile | 2 ++ .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 30 +++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile new file mode 100644 index 000000000000..42e17e1a97bd --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts new file mode 100644 index 000000000000..64421fb2ad67 --- /dev/null +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> + */ + +/dts-v1/; + +#include "bl808.dtsi" + +/ { + model = "Sipeed M1S"; + compatible = "sipeed,m1s", "bouffalolab,bl808"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:2000000n8"; + }; + + memory@50000000 { + device_type = "memory"; + reg = <0x50000000 0x04000000>; + }; +}; + +&uart0 { + status = "okay"; +}; -- 2.37.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree 2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang @ 2022-11-20 11:09 ` Conor Dooley 2022-11-20 11:57 ` Icenowy Zheng ` (2 subsequent siblings) 3 siblings, 0 replies; 27+ messages in thread From: Conor Dooley @ 2022-11-20 11:09 UTC (permalink / raw) To: Jisheng Zhang Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, Nov 20, 2022 at 04:21:13PM +0800, Jisheng Zhang wrote: > Sipeed manufactures a M1S system-on-module and dock board, add basic > support for them. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/bouffalolab/Makefile | 2 ++ > .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 30 +++++++++++++++++++ > 2 files changed, 32 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > > diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile > new file mode 100644 > index 000000000000..42e17e1a97bd > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > new file mode 100644 > index 000000000000..64421fb2ad67 > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > @@ -0,0 +1,30 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +/dts-v1/; > + > +#include "bl808.dtsi" > + > +/ { > + model = "Sipeed M1S"; > + compatible = "sipeed,m1s", "bouffalolab,bl808"; These compatibles also need to be defined, in a bouffalolab.yaml in the riscv/ bindings subdirectory. Otherwise: arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dtb:0:0: /: failed to match any schema with compatible: ['sipeed,m1s', 'bouffalolab,bl808'] Thanks, Conor. > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:2000000n8"; > + }; > + > + memory@50000000 { > + device_type = "memory"; > + reg = <0x50000000 0x04000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > -- > 2.37.2 > ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree 2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang 2022-11-20 11:09 ` Conor Dooley @ 2022-11-20 11:57 ` Icenowy Zheng 2022-11-20 15:06 ` Emil Renner Berthing 2022-11-21 10:10 ` Krzysztof Kozlowski 3 siblings, 0 replies; 27+ messages in thread From: Icenowy Zheng @ 2022-11-20 11:57 UTC (permalink / raw) To: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv 在 2022-11-20星期日的 16:21 +0800,Jisheng Zhang写道: > Sipeed manufactures a M1S system-on-module and dock board, add basic > support for them. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/bouffalolab/Makefile | 2 ++ > .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 30 I suggest a M1s DTSI and a M1s Dock DTS. > +++++++++++++++++++ > 2 files changed, 32 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed- > m1s.dts > > diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile > b/arch/riscv/boot/dts/bouffalolab/Makefile > new file mode 100644 > index 000000000000..42e17e1a97bd > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > new file mode 100644 > index 000000000000..64421fb2ad67 > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > @@ -0,0 +1,30 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +/dts-v1/; > + > +#include "bl808.dtsi" > + > +/ { > + model = "Sipeed M1S"; > + compatible = "sipeed,m1s", "bouffalolab,bl808"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:2000000n8"; > + }; > + > + memory@50000000 { > + device_type = "memory"; > + reg = <0x50000000 0x04000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree 2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang 2022-11-20 11:09 ` Conor Dooley 2022-11-20 11:57 ` Icenowy Zheng @ 2022-11-20 15:06 ` Emil Renner Berthing 2022-11-21 10:10 ` Krzysztof Kozlowski 3 siblings, 0 replies; 27+ messages in thread From: Emil Renner Berthing @ 2022-11-20 15:06 UTC (permalink / raw) To: Jisheng Zhang Cc: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby, linux-serial, devicetree, linux-kernel, linux-riscv On Sun, 20 Nov 2022 at 09:33, Jisheng Zhang <jszhang@kernel.org> wrote: > > Sipeed manufactures a M1S system-on-module and dock board, add basic > support for them. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/bouffalolab/Makefile | 2 ++ > .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 30 +++++++++++++++++++ > 2 files changed, 32 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > > diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile > new file mode 100644 > index 000000000000..42e17e1a97bd > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > new file mode 100644 > index 000000000000..64421fb2ad67 > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > @@ -0,0 +1,30 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +/dts-v1/; > + > +#include "bl808.dtsi" > + > +/ { > + model = "Sipeed M1S"; On seeedstudio.com and everywhere else I look I only see this written as "Sipeed M1s". And to echo what Icenowy writes, this is better split as a .dtsi for the Sipeed M1s module that can then be included by a .dts for the using the module with the dock, which should then have something like model = "Sipeed M1s Dock"; > + compatible = "sipeed,m1s", "bouffalolab,bl808"; > + > + aliases { > + serial0 = &uart0; > + }; > + > + chosen { > + stdout-path = "serial0:2000000n8"; > + }; > + > + memory@50000000 { > + device_type = "memory"; > + reg = <0x50000000 0x04000000>; > + }; > +}; > + > +&uart0 { > + status = "okay"; > +}; > --- > 2.37.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree 2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang ` (2 preceding siblings ...) 2022-11-20 15:06 ` Emil Renner Berthing @ 2022-11-21 10:10 ` Krzysztof Kozlowski 3 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2022-11-21 10:10 UTC (permalink / raw) To: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv On 20/11/2022 09:21, Jisheng Zhang wrote: > Sipeed manufactures a M1S system-on-module and dock board, add basic > support for them. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > arch/riscv/boot/dts/bouffalolab/Makefile | 2 ++ > .../boot/dts/bouffalolab/bl808-sipeed-m1s.dts | 30 +++++++++++++++++++ > 2 files changed, 32 insertions(+) > create mode 100644 arch/riscv/boot/dts/bouffalolab/Makefile > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > > diff --git a/arch/riscv/boot/dts/bouffalolab/Makefile b/arch/riscv/boot/dts/bouffalolab/Makefile > new file mode 100644 > index 000000000000..42e17e1a97bd > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_SOC_BOUFFALOLAB) += bl808-sipeed-m1s.dtb > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > new file mode 100644 > index 000000000000..64421fb2ad67 > --- /dev/null > +++ b/arch/riscv/boot/dts/bouffalolab/bl808-sipeed-m1s.dts > @@ -0,0 +1,30 @@ > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > +/* > + * Copyright (C) 2022 Jisheng Zhang <jszhang@kernel.org> > + */ > + > +/dts-v1/; > + > +#include "bl808.dtsi" > + > +/ { > + model = "Sipeed M1S"; > + compatible = "sipeed,m1s", "bouffalolab,bl808"; Missing bindings. Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang ` (5 preceding siblings ...) 2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang @ 2022-11-20 8:21 ` Jisheng Zhang 2022-11-21 10:11 ` Krzysztof Kozlowski 6 siblings, 1 reply; 27+ messages in thread From: Jisheng Zhang @ 2022-11-20 8:21 UTC (permalink / raw) To: Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv I want to maintain this Bouffalolab riscv SoC entry from now on. Signed-off-by: Jisheng Zhang <jszhang@kernel.org> --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 92451834b940..3564b27d7da4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17738,6 +17738,12 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V BOUFFALOLAB SOC SUPPORT +M: Jisheng Zhang <jszhang@kernel.org> +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/boot/dts/bouffalolab/ + RISC-V MICROCHIP FPGA SUPPORT M: Conor Dooley <conor.dooley@microchip.com> M: Daire McNamara <daire.mcnamara@microchip.com> -- 2.37.2 ^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer 2022-11-20 8:21 ` [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Jisheng Zhang @ 2022-11-21 10:11 ` Krzysztof Kozlowski 0 siblings, 0 replies; 27+ messages in thread From: Krzysztof Kozlowski @ 2022-11-21 10:11 UTC (permalink / raw) To: Jisheng Zhang, Greg Kroah-Hartman, Rob Herring, Krzysztof Kozlowski, Paul Walmsley, Palmer Dabbelt, Albert Ou, Jiri Slaby Cc: linux-serial, devicetree, linux-kernel, linux-riscv On 20/11/2022 09:21, Jisheng Zhang wrote: > I want to maintain this Bouffalolab riscv SoC entry from now on. Use 3rd person narrative, so: 1. Subject: MAINTAINERS: riscv: add entry for Bouffalolab SoC 2. Commit: Add Jisheng Zhang as Bouffalolab SoC maintainer. > > Signed-off-by: Jisheng Zhang <jszhang@kernel.org> > --- > MAINTAINERS | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 92451834b940..3564b27d7da4 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -17738,6 +17738,12 @@ F: arch/riscv/ > N: riscv > K: riscv > > +RISC-V BOUFFALOLAB SOC SUPPORT > +M: Jisheng Zhang <jszhang@kernel.org> > +L: linux-riscv@lists.infradead.org > +S: Maintained > +F: arch/riscv/boot/dts/bouffalolab/ > + > RISC-V MICROCHIP FPGA SUPPORT > M: Conor Dooley <conor.dooley@microchip.com> > M: Daire McNamara <daire.mcnamara@microchip.com> Best regards, Krzysztof ^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2022-11-30 18:04 UTC | newest] Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-11-20 8:21 [PATCH 0/7] riscv: add Bouffalolab bl808 support Jisheng Zhang 2022-11-20 8:21 ` [PATCH 1/7] dt-bindings: serial: add bindings doc for Bouffalolab uart driver Jisheng Zhang 2022-11-21 10:08 ` Krzysztof Kozlowski 2022-11-30 18:04 ` Rob Herring 2022-11-20 8:21 ` [PATCH 2/7] serial: bflb_uart: add Bouffalolab UART Driver Jisheng Zhang 2022-11-21 8:09 ` Jiri Slaby 2022-11-21 13:59 ` Ilpo Järvinen 2022-11-20 8:21 ` [PATCH 3/7] MAINTAINERS: add myself as a reviewer for Bouffalolab uart driver Jisheng Zhang 2022-11-20 8:21 ` [PATCH 4/7] riscv: add the Bouffalolab SoC family Kconfig option Jisheng Zhang 2022-11-20 10:43 ` Conor Dooley 2022-11-20 8:21 ` [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree Jisheng Zhang 2022-11-20 11:02 ` Conor Dooley 2022-11-20 11:58 ` Icenowy Zheng 2022-11-20 14:28 ` Conor Dooley 2022-11-20 14:57 ` Emil Renner Berthing 2022-11-20 17:51 ` Conor Dooley 2022-11-20 18:33 ` Emil Renner Berthing 2022-11-21 3:36 ` Icenowy Zheng 2022-11-21 11:25 ` Emil Renner Berthing 2022-11-21 10:09 ` Krzysztof Kozlowski 2022-11-20 8:21 ` [PATCH 6/7] riscv: dts: bouffalolab: add Sipeed M1S dock devicetree Jisheng Zhang 2022-11-20 11:09 ` Conor Dooley 2022-11-20 11:57 ` Icenowy Zheng 2022-11-20 15:06 ` Emil Renner Berthing 2022-11-21 10:10 ` Krzysztof Kozlowski 2022-11-20 8:21 ` [PATCH 7/7] MAINTAINERS: add myself as Bouffalolab SoC entry maintainer Jisheng Zhang 2022-11-21 10:11 ` Krzysztof Kozlowski
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