[PATCH 0/2] clocksource/meson6_timer: implement ARM delay timer

[PATCH 0/2] clocksource/meson6_timer: implement ARM delay timer

[Martin Blumenstingl]

While trying to add support for the ARM TWD Timer and the ARM Global
Timer on Meson8, Meson8b and Meson8m2 (ARM Cortex-A5 and Cortex-A9 SoCs)
I did a review of the existing driver.
Unfortunately I found it hard to review because the pre-processor
#defines did not match the names from the public S805 datasheet. Thus
patch #1 adjusts these. No functional changes here, this is just
preparation work for patch #2.

Using the ARM Global Timer (drivers/clocksource/arm_global_timer.c)
would have given us a timer-based delay implementation (so udelay() and
friends would use the timer instead of using a loop-based delay
implementation). Unfortunately we can't use the ARM Global Timer yet
because it's input clock is derived from the CPU clock (which can change
once we enable CPU frequency scaling on these SoCs, for which I will be
sending patches in the near future).
Amlogic's 3.10 kernel uses Timer E as delay timer which (with the
current configuration) has a resolution of 1us. So patch #2 uses
register_current_timer_delay() to register Timer E as ARM delay timer
(which will be especially useful as we have to use udelay() when
changing the CPU clocks during DVFS).


Martin Blumenstingl (2):
  clocksource: meson6_timer: use register names from the datasheet
  clocksource: meson6_timer: implement ARM delay timer

 drivers/clocksource/meson6_timer.c | 130 ++++++++++++++++++++---------
 1 file changed, 89 insertions(+), 41 deletions(-)

-- 
2.19.1

[PATCH 1/2] clocksource: meson6_timer: use register names from the datasheet

[Martin Blumenstingl]

This makes the driver use the names from S805 datasheet for the
preprocessor #defines. This makes it easier to spot that the driver
currently only supports Timer A (as clockevent with interrupt support)
and Timer E (as clocksource without interrupts). Timer B, C and D (which
are similar to Timer A) are currently not supported by the driver.

While here, this also removes the internal "CED_ID" and "CSD_ID" defines
which are used to identify the timer. These IDs are not described in the
datasheet and thus make it harder to compare the code to what's written
in the datasheet.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clocksource/meson6_timer.c | 110 ++++++++++++++++++-----------
 1 file changed, 68 insertions(+), 42 deletions(-)

diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c
index 92f20991a937..c622135bee9d 100644
--- a/drivers/clocksource/meson6_timer.c
+++ b/drivers/clocksource/meson6_timer.c
@@ -10,6 +10,8 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
@@ -20,80 +22,102 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
-#define CED_ID			0
-#define CSD_ID			4
-
-#define TIMER_ISA_MUX		0
-#define TIMER_ISA_VAL(t)	(((t) + 1) << 2)
-
-#define TIMER_INPUT_BIT(t)	(2 * (t))
-#define TIMER_ENABLE_BIT(t)	(16 + (t))
-#define TIMER_PERIODIC_BIT(t)	(12 + (t))
+enum meson6_timera_input_clock {
+	MESON_TIMERA_CLOCK_1US = 0x0,
+	MESON_TIMERA_CLOCK_10US = 0x1,
+	MESON_TIMERA_CLOCK_100US = 0x2,
+	MESON_TIMERA_CLOCK_1MS = 0x3,
+};
 
-#define TIMER_CED_INPUT_MASK	(3UL << TIMER_INPUT_BIT(CED_ID))
-#define TIMER_CSD_INPUT_MASK	(7UL << TIMER_INPUT_BIT(CSD_ID))
+enum meson6_timere_input_clock {
+	MESON_TIMERE_CLOCK_SYSTEM_CLOCK = 0x0,
+	MESON_TIMERE_CLOCK_1US = 0x1,
+	MESON_TIMERE_CLOCK_10US = 0x2,
+	MESON_TIMERE_CLOCK_100US = 0x3,
+	MESON_TIMERE_CLOCK_1MS = 0x4,
+};
 
-#define TIMER_CED_UNIT_1US	0
-#define TIMER_CSD_UNIT_1US	1
+#define MESON_ISA_TIMER_MUX					0x00
+#define MESON_ISA_TIMER_MUX_TIMERD_EN				BIT(19)
+#define MESON_ISA_TIMER_MUX_TIMERC_EN				BIT(18)
+#define MESON_ISA_TIMER_MUX_TIMERB_EN				BIT(17)
+#define MESON_ISA_TIMER_MUX_TIMERA_EN				BIT(16)
+#define MESON_ISA_TIMER_MUX_TIMERD_MODE				BIT(15)
+#define MESON_ISA_TIMER_MUX_TIMERC_MODE				BIT(14)
+#define MESON_ISA_TIMER_MUX_TIMERB_MODE				BIT(13)
+#define MESON_ISA_TIMER_MUX_TIMERA_MODE				BIT(12)
+#define MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK		GENMASK(10, 8)
+#define MESON_ISA_TIMER_MUX_TIMERD_INPUT_CLOCK_MASK		GENMASK(7, 6)
+#define MESON_ISA_TIMER_MUX_TIMERC_INPUT_CLOCK_MASK		GENMASK(5, 4)
+#define MESON_ISA_TIMER_MUX_TIMERB_INPUT_CLOCK_MASK		GENMASK(3, 2)
+#define MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK		GENMASK(1, 0)
+
+#define MESON_ISA_TIMERA					0x04
+#define MESON_ISA_TIMERB					0x08
+#define MESON_ISA_TIMERC					0x0c
+#define MESON_ISA_TIMERD					0x10
+#define MESON_ISA_TIMERE					0x14
 
 static void __iomem *timer_base;
 
 static u64 notrace meson6_timer_sched_read(void)
 {
-	return (u64)readl(timer_base + TIMER_ISA_VAL(CSD_ID));
+	return (u64)readl(timer_base + MESON_ISA_TIMERE);
 }
 
-static void meson6_clkevt_time_stop(unsigned char timer)
+static void meson6_clkevt_time_stop(void)
 {
-	u32 val = readl(timer_base + TIMER_ISA_MUX);
+	u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
 
-	writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);
+	writel(val & ~MESON_ISA_TIMER_MUX_TIMERA_EN,
+	       timer_base + MESON_ISA_TIMER_MUX);
 }
 
-static void meson6_clkevt_time_setup(unsigned char timer, unsigned long delay)
+static void meson6_clkevt_time_setup(unsigned long delay)
 {
-	writel(delay, timer_base + TIMER_ISA_VAL(timer));
+	writel(delay, timer_base + MESON_ISA_TIMERA);
 }
 
-static void meson6_clkevt_time_start(unsigned char timer, bool periodic)
+static void meson6_clkevt_time_start(bool periodic)
 {
-	u32 val = readl(timer_base + TIMER_ISA_MUX);
+	u32 val = readl(timer_base + MESON_ISA_TIMER_MUX);
 
 	if (periodic)
-		val |= TIMER_PERIODIC_BIT(timer);
+		val |= MESON_ISA_TIMER_MUX_TIMERA_MODE;
 	else
-		val &= ~TIMER_PERIODIC_BIT(timer);
+		val &= ~MESON_ISA_TIMER_MUX_TIMERA_MODE;
 
-	writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX);
+	writel(val | MESON_ISA_TIMER_MUX_TIMERA_EN,
+	       timer_base + MESON_ISA_TIMER_MUX);
 }
 
 static int meson6_shutdown(struct clock_event_device *evt)
 {
-	meson6_clkevt_time_stop(CED_ID);
+	meson6_clkevt_time_stop();
 	return 0;
 }
 
 static int meson6_set_oneshot(struct clock_event_device *evt)
 {
-	meson6_clkevt_time_stop(CED_ID);
-	meson6_clkevt_time_start(CED_ID, false);
+	meson6_clkevt_time_stop();
+	meson6_clkevt_time_start(false);
 	return 0;
 }
 
 static int meson6_set_periodic(struct clock_event_device *evt)
 {
-	meson6_clkevt_time_stop(CED_ID);
-	meson6_clkevt_time_setup(CED_ID, USEC_PER_SEC / HZ - 1);
-	meson6_clkevt_time_start(CED_ID, true);
+	meson6_clkevt_time_stop();
+	meson6_clkevt_time_setup(USEC_PER_SEC / HZ - 1);
+	meson6_clkevt_time_start(true);
 	return 0;
 }
 
 static int meson6_clkevt_next_event(unsigned long evt,
 				    struct clock_event_device *unused)
 {
-	meson6_clkevt_time_stop(CED_ID);
-	meson6_clkevt_time_setup(CED_ID, evt);
-	meson6_clkevt_time_start(CED_ID, false);
+	meson6_clkevt_time_stop();
+	meson6_clkevt_time_setup(evt);
+	meson6_clkevt_time_start(false);
 
 	return 0;
 }
@@ -144,22 +168,24 @@ static int __init meson6_timer_init(struct device_node *node)
 	}
 
 	/* Set 1us for timer E */
-	val = readl(timer_base + TIMER_ISA_MUX);
-	val &= ~TIMER_CSD_INPUT_MASK;
-	val |= TIMER_CSD_UNIT_1US << TIMER_INPUT_BIT(CSD_ID);
-	writel(val, timer_base + TIMER_ISA_MUX);
+	val = readl(timer_base + MESON_ISA_TIMER_MUX);
+	val &= ~MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK;
+	val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERE_INPUT_CLOCK_MASK,
+			  MESON_TIMERE_CLOCK_1US);
+	writel(val, timer_base + MESON_ISA_TIMER_MUX);
 
 	sched_clock_register(meson6_timer_sched_read, 32, USEC_PER_SEC);
-	clocksource_mmio_init(timer_base + TIMER_ISA_VAL(CSD_ID), node->name,
+	clocksource_mmio_init(timer_base + MESON_ISA_TIMERE, node->name,
 			      1000 * 1000, 300, 32, clocksource_mmio_readl_up);
 
 	/* Timer A base 1us */
-	val &= ~TIMER_CED_INPUT_MASK;
-	val |= TIMER_CED_UNIT_1US << TIMER_INPUT_BIT(CED_ID);
-	writel(val, timer_base + TIMER_ISA_MUX);
+	val &= ~MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK;
+	val |= FIELD_PREP(MESON_ISA_TIMER_MUX_TIMERA_INPUT_CLOCK_MASK,
+			  MESON_TIMERA_CLOCK_1US);
+	writel(val, timer_base + MESON_ISA_TIMER_MUX);
 
 	/* Stop the timer A */
-	meson6_clkevt_time_stop(CED_ID);
+	meson6_clkevt_time_stop();
 
 	ret = setup_irq(irq, &meson6_timer_irq);
 	if (ret) {
-- 
2.19.1

Re: [PATCH 1/2] clocksource: meson6_timer: use register names from the datasheet

[Daniel Lezcano]

On 28/10/2018 13:55, Martin Blumenstingl wrote:
> This makes the driver use the names from S805 datasheet for the
> preprocessor #defines. This makes it easier to spot that the driver
> currently only supports Timer A (as clockevent with interrupt support)
> and Timer E (as clocksource without interrupts). Timer B, C and D (which
> are similar to Timer A) are currently not supported by the driver.
> 
> While here, this also removes the internal "CED_ID" and "CSD_ID" defines
> which are used to identify the timer. These IDs are not described in the
> datasheet and thus make it harder to compare the code to what's written
> in the datasheet.
> 
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
>  drivers/clocksource/meson6_timer.c | 110 ++++++++++++++++++-----------
>  1 file changed, 68 insertions(+), 42 deletions(-)
> 
> diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c
> index 92f20991a937..c622135bee9d 100644
> --- a/drivers/clocksource/meson6_timer.c
> +++ b/drivers/clocksource/meson6_timer.c
> @@ -10,6 +10,8 @@
>   * warranty of any kind, whether express or implied.
>   */
>  
> +#include <linux/bitfield.h>
> +#include <linux/bitops.h>
>  #include <linux/clk.h>
>  #include <linux/clockchips.h>
>  #include <linux/interrupt.h>
> @@ -20,80 +22,102 @@
>  #include <linux/of_address.h>
>  #include <linux/of_irq.h>
>  
> -#define CED_ID			0
> -#define CSD_ID			4
> -
> -#define TIMER_ISA_MUX		0
> -#define TIMER_ISA_VAL(t)	(((t) + 1) << 2)
> -
> -#define TIMER_INPUT_BIT(t)	(2 * (t))
> -#define TIMER_ENABLE_BIT(t)	(16 + (t))
> -#define TIMER_PERIODIC_BIT(t)	(12 + (t))
> +enum meson6_timera_input_clock {
> +	MESON_TIMERA_CLOCK_1US = 0x0,
> +	MESON_TIMERA_CLOCK_10US = 0x1,
> +	MESON_TIMERA_CLOCK_100US = 0x2,
> +	MESON_TIMERA_CLOCK_1MS = 0x3,
> +};
>  
> -#define TIMER_CED_INPUT_MASK	(3UL << TIMER_INPUT_BIT(CED_ID))
> -#define TIMER_CSD_INPUT_MASK	(7UL << TIMER_INPUT_BIT(CSD_ID))
> +enum meson6_timere_input_clock {
> +	MESON_TIMERE_CLOCK_SYSTEM_CLOCK = 0x0,
> +	MESON_TIMERE_CLOCK_1US = 0x1,
> +	MESON_TIMERE_CLOCK_10US = 0x2,
> +	MESON_TIMERE_CLOCK_100US = 0x3,
> +	MESON_TIMERE_CLOCK_1MS = 0x4,
> +};

It is not required to specify the values. The standard defines the
default first value is zero, and each enum has the value which is +1 of
the previous one.

Other than that, the changes look ok.



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Re: [PATCH 1/2] clocksource: meson6_timer: use register names from the datasheet

[Martin Blumenstingl]

Hi Daniel,

thanks for your feedback!

On Thu, Nov 15, 2018 at 2:35 AM Daniel Lezcano
<daniel.lezcano@linaro.org> wrote:
>
> On 28/10/2018 13:55, Martin Blumenstingl wrote:
> > This makes the driver use the names from S805 datasheet for the
> > preprocessor #defines. This makes it easier to spot that the driver
> > currently only supports Timer A (as clockevent with interrupt support)
> > and Timer E (as clocksource without interrupts). Timer B, C and D (which
> > are similar to Timer A) are currently not supported by the driver.
> >
> > While here, this also removes the internal "CED_ID" and "CSD_ID" defines
> > which are used to identify the timer. These IDs are not described in the
> > datasheet and thus make it harder to compare the code to what's written
> > in the datasheet.
> >
> > Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> > ---
> >  drivers/clocksource/meson6_timer.c | 110 ++++++++++++++++++-----------
> >  1 file changed, 68 insertions(+), 42 deletions(-)
> >
> > diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c
> > index 92f20991a937..c622135bee9d 100644
> > --- a/drivers/clocksource/meson6_timer.c
> > +++ b/drivers/clocksource/meson6_timer.c
> > @@ -10,6 +10,8 @@
> >   * warranty of any kind, whether express or implied.
> >   */
> >
> > +#include <linux/bitfield.h>
> > +#include <linux/bitops.h>
> >  #include <linux/clk.h>
> >  #include <linux/clockchips.h>
> >  #include <linux/interrupt.h>
> > @@ -20,80 +22,102 @@
> >  #include <linux/of_address.h>
> >  #include <linux/of_irq.h>
> >
> > -#define CED_ID                       0
> > -#define CSD_ID                       4
> > -
> > -#define TIMER_ISA_MUX                0
> > -#define TIMER_ISA_VAL(t)     (((t) + 1) << 2)
> > -
> > -#define TIMER_INPUT_BIT(t)   (2 * (t))
> > -#define TIMER_ENABLE_BIT(t)  (16 + (t))
> > -#define TIMER_PERIODIC_BIT(t)        (12 + (t))
> > +enum meson6_timera_input_clock {
> > +     MESON_TIMERA_CLOCK_1US = 0x0,
> > +     MESON_TIMERA_CLOCK_10US = 0x1,
> > +     MESON_TIMERA_CLOCK_100US = 0x2,
> > +     MESON_TIMERA_CLOCK_1MS = 0x3,
> > +};
> >
> > -#define TIMER_CED_INPUT_MASK (3UL << TIMER_INPUT_BIT(CED_ID))
> > -#define TIMER_CSD_INPUT_MASK (7UL << TIMER_INPUT_BIT(CSD_ID))
> > +enum meson6_timere_input_clock {
> > +     MESON_TIMERE_CLOCK_SYSTEM_CLOCK = 0x0,
> > +     MESON_TIMERE_CLOCK_1US = 0x1,
> > +     MESON_TIMERE_CLOCK_10US = 0x2,
> > +     MESON_TIMERE_CLOCK_100US = 0x3,
> > +     MESON_TIMERE_CLOCK_1MS = 0x4,
> > +};
>
> It is not required to specify the values. The standard defines the
> default first value is zero, and each enum has the value which is +1 of
> the previous one.
the idea behind this is: these are values from the datasheet so I
wanted to make them easy to find when comparing the datasheet with the
driver.
I will replace the enums with simple #defines if there are no
objections (that also makes it consistent with the other register
values in the driver).


Regards
Martin

Re: [PATCH 1/2] clocksource: meson6_timer: use register names from the datasheet

[Daniel Lezcano]

On 15/11/2018 07:23, Martin Blumenstingl wrote:
> Hi Daniel,
> 
> thanks for your feedback!
> 
> On Thu, Nov 15, 2018 at 2:35 AM Daniel Lezcano
> <daniel.lezcano@linaro.org> wrote:
>>
>> On 28/10/2018 13:55, Martin Blumenstingl wrote:
>>> This makes the driver use the names from S805 datasheet for the
>>> preprocessor #defines. This makes it easier to spot that the driver
>>> currently only supports Timer A (as clockevent with interrupt support)
>>> and Timer E (as clocksource without interrupts). Timer B, C and D (which
>>> are similar to Timer A) are currently not supported by the driver.
>>>
>>> While here, this also removes the internal "CED_ID" and "CSD_ID" defines
>>> which are used to identify the timer. These IDs are not described in the
>>> datasheet and thus make it harder to compare the code to what's written
>>> in the datasheet.
>>>
>>> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
>>> ---
>>>  drivers/clocksource/meson6_timer.c | 110 ++++++++++++++++++-----------
>>>  1 file changed, 68 insertions(+), 42 deletions(-)
>>>
>>> diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c
>>> index 92f20991a937..c622135bee9d 100644
>>> --- a/drivers/clocksource/meson6_timer.c
>>> +++ b/drivers/clocksource/meson6_timer.c
>>> @@ -10,6 +10,8 @@
>>>   * warranty of any kind, whether express or implied.
>>>   */
>>>
>>> +#include <linux/bitfield.h>
>>> +#include <linux/bitops.h>
>>>  #include <linux/clk.h>
>>>  #include <linux/clockchips.h>
>>>  #include <linux/interrupt.h>
>>> @@ -20,80 +22,102 @@
>>>  #include <linux/of_address.h>
>>>  #include <linux/of_irq.h>
>>>
>>> -#define CED_ID                       0
>>> -#define CSD_ID                       4
>>> -
>>> -#define TIMER_ISA_MUX                0
>>> -#define TIMER_ISA_VAL(t)     (((t) + 1) << 2)
>>> -
>>> -#define TIMER_INPUT_BIT(t)   (2 * (t))
>>> -#define TIMER_ENABLE_BIT(t)  (16 + (t))
>>> -#define TIMER_PERIODIC_BIT(t)        (12 + (t))
>>> +enum meson6_timera_input_clock {
>>> +     MESON_TIMERA_CLOCK_1US = 0x0,
>>> +     MESON_TIMERA_CLOCK_10US = 0x1,
>>> +     MESON_TIMERA_CLOCK_100US = 0x2,
>>> +     MESON_TIMERA_CLOCK_1MS = 0x3,
>>> +};
>>>
>>> -#define TIMER_CED_INPUT_MASK (3UL << TIMER_INPUT_BIT(CED_ID))
>>> -#define TIMER_CSD_INPUT_MASK (7UL << TIMER_INPUT_BIT(CSD_ID))
>>> +enum meson6_timere_input_clock {
>>> +     MESON_TIMERE_CLOCK_SYSTEM_CLOCK = 0x0,
>>> +     MESON_TIMERE_CLOCK_1US = 0x1,
>>> +     MESON_TIMERE_CLOCK_10US = 0x2,
>>> +     MESON_TIMERE_CLOCK_100US = 0x3,
>>> +     MESON_TIMERE_CLOCK_1MS = 0x4,
>>> +};
>>
>> It is not required to specify the values. The standard defines the
>> default first value is zero, and each enum has the value which is +1 of
>> the previous one.
> the idea behind this is: these are values from the datasheet so I
> wanted to make them easy to find when comparing the datasheet with the
> driver.
> I will replace the enums with simple #defines if there are no
> objections (that also makes it consistent with the other register
> values in the driver).

No objection to change them to macros :)

  -- Daniel


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[PATCH 2/2] clocksource: meson6_timer: implement ARM delay timer

[Martin Blumenstingl]

Implement an ARM delay timer to be used for udelay(). This allows us to
skip the delay loop calibration at boot.

With this patch udelay() is now independent of CPU frequency changes.
This is a good thing on Meson8, Meson8b and Meson8m2 because changing
the CPU frequency requires running the CPU clock off the XTAL while
changing the PLL or it's dividers. After changing the CPU clocks we need
to wait a few usecs for the clock to become stable. So having an
udelay() implementation that doesn't depend on the CPU frequency is
beneficial.

Suggested-by: Jianxin Pan <jianxin.pan@amlogic.com>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
---
 drivers/clocksource/meson6_timer.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/clocksource/meson6_timer.c b/drivers/clocksource/meson6_timer.c
index c622135bee9d..5ee2a575069b 100644
--- a/drivers/clocksource/meson6_timer.c
+++ b/drivers/clocksource/meson6_timer.c
@@ -22,6 +22,10 @@
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 
+#ifdef CONFIG_ARM
+#include <linux/delay.h>
+#endif
+
 enum meson6_timera_input_clock {
 	MESON_TIMERA_CLOCK_1US = 0x0,
 	MESON_TIMERA_CLOCK_10US = 0x1,
@@ -60,6 +64,18 @@ enum meson6_timere_input_clock {
 
 static void __iomem *timer_base;
 
+#ifdef CONFIG_ARM
+static unsigned long meson6_read_current_timer(void)
+{
+	return readl_relaxed(timer_base + MESON_ISA_TIMERE);
+}
+
+static struct delay_timer meson6_delay_timer = {
+	.read_current_timer = meson6_read_current_timer,
+	.freq = 1000 * 1000,
+};
+#endif
+
 static u64 notrace meson6_timer_sched_read(void)
 {
 	return (u64)readl(timer_base + MESON_ISA_TIMERE);
@@ -198,6 +214,12 @@ static int __init meson6_timer_init(struct device_node *node)
 
 	clockevents_config_and_register(&meson6_clockevent, USEC_PER_SEC,
 					1, 0xfffe);
+
+#ifdef CONFIG_ARM
+	/* Also use MESON_ISA_TIMERE for delays */
+	register_current_timer_delay(&meson6_delay_timer);
+#endif
+
 	return 0;
 }
 TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",
-- 
2.19.1

Re: [PATCH 0/2] clocksource/meson6_timer: implement ARM delay timer

[Martin Blumenstingl]

Hi Daniel, Hi Thomas,

On Sun, Oct 28, 2018 at 1:55 PM Martin Blumenstingl
<martin.blumenstingl@googlemail.com> wrote:
>
> While trying to add support for the ARM TWD Timer and the ARM Global
> Timer on Meson8, Meson8b and Meson8m2 (ARM Cortex-A5 and Cortex-A9 SoCs)
> I did a review of the existing driver.
> Unfortunately I found it hard to review because the pre-processor
> #defines did not match the names from the public S805 datasheet. Thus
> patch #1 adjusts these. No functional changes here, this is just
> preparation work for patch #2.
>
> Using the ARM Global Timer (drivers/clocksource/arm_global_timer.c)
> would have given us a timer-based delay implementation (so udelay() and
> friends would use the timer instead of using a loop-based delay
> implementation). Unfortunately we can't use the ARM Global Timer yet
> because it's input clock is derived from the CPU clock (which can change
> once we enable CPU frequency scaling on these SoCs, for which I will be
> sending patches in the near future).
> Amlogic's 3.10 kernel uses Timer E as delay timer which (with the
> current configuration) has a resolution of 1us. So patch #2 uses
> register_current_timer_delay() to register Timer E as ARM delay timer
> (which will be especially useful as we have to use udelay() when
> changing the CPU clocks during DVFS).
>
>
> Martin Blumenstingl (2):
>   clocksource: meson6_timer: use register names from the datasheet
>   clocksource: meson6_timer: implement ARM delay timer
(gentle ping) can you please queue these two patches for v4.21?
if not: please let me know what I can improve, then I'll fix that and send a v2


thank you!
Regards
Martin