Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry

From: Thomas Gleixner <tglx@linutronix.de>
To: Borislav Petkov <bp@alien8.de>, Ingo Molnar <mingo@kernel.org>
Cc: Ira Weiny <ira.weiny@intel.com>,
	Andy Lutomirski <luto@kernel.org>,
	Dave Hansen <dave.hansen@intel.com>,
	Rik van Riel <riel@surriel.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@fb.com
Subject: Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry
Date: Tue, 09 Aug 2022 22:06:16 +0200	[thread overview]
Message-ID: <87o7wtqj0n.ffs@tglx> (raw)
In-Reply-To: <YvD7FNovYh7UzrAc@zn.tnic>

On Mon, Aug 08 2022 at 14:01, Borislav Petkov wrote:
> On Mon, Aug 08, 2022 at 01:03:24PM +0200, Ingo Molnar wrote:
>> I'd like to hear what Andy Lutomirski thinks about the notion that
>> "2 instructions don't matter at all" ...
>> 
>> Especially since it's now 4 instructions:
>
> He wasn't opposed to it when we talked on IRC last week.
>
>> ... 4 instructions in the exception path is a non-trivial impact.
>
> How do I measure this "impact"?
>
> Hell, we recently added retbleed - and IBRS especially on Intel - on
> the entry path which is whopping 30% perf impact in some cases. And
> now we're arguing about a handful of insns. I'm sceptical they'll be
> anything else but "in-the-noise" in any sensible workload.

I'm not worried about the 4 instructions per se, but storing the CPU
number on every exception and interrupt entry just to use it in exactly
one place, i.e. the user mode #PF handler, does not make any sense at
all.

Get the CPU number before enabling interrupts and hand it in to the
bad area variants.

I know that the aux reg code is required for other things, but just for
this it's complete overkill.

Thanks,

        tglx