From: Ira Weiny <ira.weiny@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Ingo Molnar <mingo@kernel.org>,
Dave Hansen <dave.hansen@intel.com>,
"Rik van Riel" <riel@surriel.com>, <x86@kernel.org>,
<linux-kernel@vger.kernel.org>, <kernel-team@fb.com>
Subject: Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry
Date: Sun, 7 Aug 2022 13:02:37 -0700 [thread overview]
Message-ID: <YvAaXet3sBg3mRDe@iweiny-desk3> (raw)
In-Reply-To: <Yu+VV8xFTYRh0D0a@zn.tnic>
On Sun, Aug 07, 2022 at 12:35:03PM +0200, Borislav Petkov wrote:
> On Sun, Aug 07, 2022 at 12:02:41PM +0200, Ingo Molnar wrote:
> > * Borislav Petkov <bp@alien8.de> wrote:
> > > With the amount of logical cores ever increasing and how CPU packages
> > > (nodes, L3 sharing, you name it) get more and more complex topology,
> > > I'd say the 2 insns to show the CPU number in every exception is a good
> > > thing to do.
> >
> > We can show it - I'm arguing against extracting it too early, which costs
>
> Not early - more correct. We can say which CPU executed the exception
> handler *exactly*. Not which CPU executed the exception handler *maybe*.
>
> > us 2 instructions in the exception fast path
>
> 2 insns? They don't matter at all. FWIW, they'll pull in the per-CPU
> cacheline earlier which should be a net win later, for code which does
> smp_processor_id().
I agree with Boris; however I feel that I have to mention that in patch 3/5 you
also have 1 instruction on each of entry and exit to push the extra stack
space. So all told it would cost 4 instructions.
Again, I don't believe this is too much overhead but I don't want people to say
it was not discussed.
Ira
>
> > - while in 99.999999999% of the cases we don't use that field at all ...
>
> See my text above about the ever-increasing complexity of CPU topology.
>
> Thx.
>
> --
> Regards/Gruss,
> Boris.
>
> https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2022-08-07 20:02 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 17:30 [RFC PATCH 0/5] Print CPU at segfault time ira.weiny
2022-08-05 17:30 ` [RFC PATCH 1/5] entry: Pass pt_regs to irqentry_exit_cond_resched() ira.weiny
2022-08-05 18:33 ` Rik van Riel
2022-08-08 10:38 ` Borislav Petkov
2022-08-08 17:34 ` Ira Weiny
2022-08-08 17:38 ` Borislav Petkov
2022-08-08 17:43 ` Dave Hansen
2022-08-08 17:52 ` Borislav Petkov
2022-08-09 23:18 ` Thomas Gleixner
2022-08-10 7:25 ` Thomas Gleixner
2022-08-05 17:30 ` [RFC PATCH 2/5] entry: Add calls for save/restore auxiliary pt_regs ira.weiny
2022-08-05 18:34 ` Rik van Riel
2022-08-09 12:05 ` Borislav Petkov
2022-08-09 18:38 ` Ira Weiny
2022-08-09 18:49 ` Borislav Petkov
2022-08-09 21:14 ` Thomas Gleixner
2022-08-09 21:38 ` Borislav Petkov
2022-08-09 22:33 ` Ira Weiny
2022-08-09 21:49 ` Ira Weiny
2022-08-09 23:53 ` Thomas Gleixner
2022-08-05 17:30 ` [RFC PATCH 3/5] x86/entry: Add auxiliary pt_regs space ira.weiny
2022-08-05 18:45 ` Rik van Riel
2022-08-05 17:30 ` [RFC PATCH 4/5] x86,mm: print likely CPU at segfault time ira.weiny
2022-08-05 17:30 ` [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry ira.weiny
2022-08-05 18:46 ` Rik van Riel
2022-08-05 18:47 ` Dave Hansen
2022-08-06 9:01 ` Ingo Molnar
2022-08-06 9:11 ` Borislav Petkov
2022-08-07 10:02 ` Ingo Molnar
2022-08-07 10:35 ` Borislav Petkov
2022-08-07 20:02 ` Ira Weiny [this message]
2022-08-08 11:03 ` Ingo Molnar
2022-08-08 12:01 ` Borislav Petkov
2022-08-09 20:06 ` Thomas Gleixner
2022-08-08 16:16 ` Dave Hansen
2022-08-08 17:24 ` Rik van Riel
2022-08-09 21:19 ` Andy Lutomirski
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