From: Ingo Molnar <mingo@kernel.org>
To: Dave Hansen <dave.hansen@intel.com>
Cc: ira.weiny@intel.com, Rik van Riel <riel@surriel.com>,
Borislav Petkov <bp@alien8.de>,
x86@kernel.org, linux-kernel@vger.kernel.org, kernel-team@fb.com
Subject: Re: [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry
Date: Sat, 6 Aug 2022 11:01:06 +0200 [thread overview]
Message-ID: <Yu4t0jkpIY4grgxL@gmail.com> (raw)
In-Reply-To: <5d62c1d0-7425-d5bb-ecb5-1dc3b4d7d245@intel.com>
* Dave Hansen <dave.hansen@intel.com> wrote:
> On 8/5/22 10:30, ira.weiny@intel.com wrote:
> > +static inline void arch_save_aux_pt_regs(struct pt_regs *regs)
> > +{
> > + struct pt_regs_auxiliary *aux_pt_regs = &to_extended_pt_regs(regs)->aux;
> > +
> > + aux_pt_regs->cpu = raw_smp_processor_id();
> > +}
>
> This is in a fast path that all interrupt and exception entry uses. So,
> I was curious what the overhead is.
>
> Code generation in irqentry_enter() gets a _bit_ more complicated
> because arch_save_aux_pt_regs() has to be done on the way out of the
> function and the compiler can't (for instance) do a
>
> mov $0x1,%eax
> ret
>
> to return. But, the gist of the change is still only two instructions
> that read a pretty hot, read-only per-cpu cacheline:
>
> mov %gs:0x7e21fa4a(%rip),%eax # 15a38 <cpu_number>
> mov %eax,-0x8(%rbx)
>
> That doesn't seem too bad.
It's still 2 instructions more than what we had before, while the
fault-time CPU number is only needed infrequently AFAICS.
Thanks,
Ingo
next prev parent reply other threads:[~2022-08-06 9:01 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-05 17:30 [RFC PATCH 0/5] Print CPU at segfault time ira.weiny
2022-08-05 17:30 ` [RFC PATCH 1/5] entry: Pass pt_regs to irqentry_exit_cond_resched() ira.weiny
2022-08-05 18:33 ` Rik van Riel
2022-08-08 10:38 ` Borislav Petkov
2022-08-08 17:34 ` Ira Weiny
2022-08-08 17:38 ` Borislav Petkov
2022-08-08 17:43 ` Dave Hansen
2022-08-08 17:52 ` Borislav Petkov
2022-08-09 23:18 ` Thomas Gleixner
2022-08-10 7:25 ` Thomas Gleixner
2022-08-05 17:30 ` [RFC PATCH 2/5] entry: Add calls for save/restore auxiliary pt_regs ira.weiny
2022-08-05 18:34 ` Rik van Riel
2022-08-09 12:05 ` Borislav Petkov
2022-08-09 18:38 ` Ira Weiny
2022-08-09 18:49 ` Borislav Petkov
2022-08-09 21:14 ` Thomas Gleixner
2022-08-09 21:38 ` Borislav Petkov
2022-08-09 22:33 ` Ira Weiny
2022-08-09 21:49 ` Ira Weiny
2022-08-09 23:53 ` Thomas Gleixner
2022-08-05 17:30 ` [RFC PATCH 3/5] x86/entry: Add auxiliary pt_regs space ira.weiny
2022-08-05 18:45 ` Rik van Riel
2022-08-05 17:30 ` [RFC PATCH 4/5] x86,mm: print likely CPU at segfault time ira.weiny
2022-08-05 17:30 ` [RFC PATCH 5/5] x86/entry: Store CPU info on exception entry ira.weiny
2022-08-05 18:46 ` Rik van Riel
2022-08-05 18:47 ` Dave Hansen
2022-08-06 9:01 ` Ingo Molnar [this message]
2022-08-06 9:11 ` Borislav Petkov
2022-08-07 10:02 ` Ingo Molnar
2022-08-07 10:35 ` Borislav Petkov
2022-08-07 20:02 ` Ira Weiny
2022-08-08 11:03 ` Ingo Molnar
2022-08-08 12:01 ` Borislav Petkov
2022-08-09 20:06 ` Thomas Gleixner
2022-08-08 16:16 ` Dave Hansen
2022-08-08 17:24 ` Rik van Riel
2022-08-09 21:19 ` Andy Lutomirski
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