[PATCH v2 0/9] Allwinner H6 USB support

[PATCH v2 0/9] Allwinner H6 USB support

[Icenowy Zheng]

This patchset introduces support for the USB ports (both USB2 and USB3)
on the Allwinner H6 SoC.

This revision adds the USB2 support, and places it before the USB3
support. So only the USB3 part will have changelog in this revision.

The first 5 PATCHes are the USB2 part, and the latter 4 PATCHes are the
USB3 part.

PATCH 1, 2, 6, 7 should go through the PHY tree, and the remaining
patches should go through the armsoc tree via sunxi tree.

Icenowy Zheng (9):
  phy: sun4i-usb: add support for missing USB PHY index
  phy: sun4i-usb: add support for H6 USB2 PHY
  arm64: allwinner: dts: h6: add USB2-related device nodes
  arm64: allwinner: dts: h6: add USB Vbus regulator
  arm64: allwinner: dts: h6: enable USB2 on Pine H64
  dt-bindings: phy: add binding for Allwinner USB3 PHY
  phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
  arm64: allwinner: dts: h6: add USB3 device nodes
  arm64: allwinner: dts: h6: enable USB3 port on Pine H64

 .../bindings/phy/sun50i-usb3-phy.txt          |  24 +++
 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts |  46 +++++
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 114 ++++++++++
 drivers/phy/allwinner/Kconfig                 |  13 ++
 drivers/phy/allwinner/Makefile                |   1 +
 drivers/phy/allwinner/phy-sun4i-usb.c         |  26 ++-
 drivers/phy/allwinner/phy-sun50i-usb3.c       | 194 ++++++++++++++++++
 7 files changed, 416 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
 create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c

-- 
2.17.1

[PATCH v2 1/9] phy: sun4i-usb: add support for missing USB PHY index

[Icenowy Zheng]

The new Allwinner H6 SoC's USB2 PHY has two holes -- USB1 (which is a
3.0 port with dedicated PHY) and USB2 (which doesn't exist at all).

Add support for this kind of missing USB PHY index.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index d4dcd39b8d76..881078ff73f6 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -126,6 +126,7 @@ struct sun4i_usb_phy_cfg {
 	bool dedicated_clocks;
 	bool enable_pmu_unk1;
 	bool phy0_dual_route;
+	int missing_phys;
 };
 
 struct sun4i_usb_phy_data {
@@ -646,6 +647,9 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
 	if (args->args[0] >= data->cfg->num_phys)
 		return ERR_PTR(-ENODEV);
 
+	if (data->cfg->missing_phys & BIT(args->args[0]))
+		return ERR_PTR(-ENODEV);
+
 	return data->phys[args->args[0]].phy;
 }
 
@@ -741,6 +745,9 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
 		struct sun4i_usb_phy *phy = data->phys + i;
 		char name[16];
 
+		if (data->cfg->missing_phys & BIT(i))
+			continue;
+
 		snprintf(name, sizeof(name), "usb%d_vbus", i);
 		phy->vbus = devm_regulator_get_optional(dev, name);
 		if (IS_ERR(phy->vbus)) {
-- 
2.17.1

[PATCH v2 2/9] phy: sun4i-usb: add support for H6 USB2 PHY

[Icenowy Zheng]

The USB 2.0 PHY on Allwinner H6 SoC is similar to older Allwinner SoCs,
with some USB0 quirk like A83T and PHY index 1/2 missing.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 drivers/phy/allwinner/phy-sun4i-usb.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 881078ff73f6..ae16854a770a 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -115,6 +115,7 @@ enum sun4i_usb_phy_type {
 	sun8i_r40_phy,
 	sun8i_v3s_phy,
 	sun50i_a64_phy,
+	sun50i_h6_phy,
 };
 
 struct sun4i_usb_phy_cfg {
@@ -295,7 +296,8 @@ static int sun4i_usb_phy_init(struct phy *_phy)
 		return ret;
 	}
 
-	if (data->cfg->type == sun8i_a83t_phy) {
+	if (data->cfg->type == sun8i_a83t_phy ||
+	    data->cfg->type == sun50i_h6_phy) {
 		if (phy->index == 0) {
 			val = readl(data->base + data->cfg->phyctl_offset);
 			val |= PHY_CTL_VBUSVLDEXT;
@@ -344,7 +346,8 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
 	struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
 
 	if (phy->index == 0) {
-		if (data->cfg->type == sun8i_a83t_phy) {
+		if (data->cfg->type == sun8i_a83t_phy ||
+		    data->cfg->type == sun50i_h6_phy) {
 			void __iomem *phyctl = data->base +
 				data->cfg->phyctl_offset;
 
@@ -959,6 +962,17 @@ static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
 	.phy0_dual_route = true,
 };
 
+static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
+	.num_phys = 4,
+	.type = sun50i_h6_phy,
+	.disc_thresh = 3,
+	.phyctl_offset = REG_PHYCTL_A33,
+	.dedicated_clocks = true,
+	.enable_pmu_unk1 = true,
+	.phy0_dual_route = true,
+	.missing_phys = BIT(1) | BIT(2),
+};
+
 static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
 	{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
@@ -972,6 +986,7 @@ static const struct of_device_id sun4i_usb_phy_of_match[] = {
 	{ .compatible = "allwinner,sun8i-v3s-usb-phy", .data = &sun8i_v3s_cfg },
 	{ .compatible = "allwinner,sun50i-a64-usb-phy",
 	  .data = &sun50i_a64_cfg},
+	{ .compatible = "allwinner,sun50i-h6-usb-phy", .data = &sun50i_h6_cfg },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
-- 
2.17.1

[PATCH v2 3/9] arm64: allwinner: dts: h6: add USB2-related device nodes

[Icenowy Zheng]

Allwinner H6 has two USB2 ports, one OTG and one host-only.

Add device tree nodes related to them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 90 ++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index c72da8cd9ef5..62fc0f5e10ba 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -174,6 +174,96 @@
 			status = "disabled";
 		};
 
+		usb2otg: usb@5100000 {
+			compatible = "allwinner,sun8i-a33-musb";
+			reg = <0x05100000 0x0400>;
+			clocks = <&ccu CLK_BUS_OTG>;
+			resets = <&ccu RST_BUS_OTG>;
+			interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "mc";
+			phys = <&usb2phy 0>;
+			phy-names = "usb";
+			extcon = <&usb2phy 0>;
+			status = "disabled";
+		};
+
+		usb2phy: phy@5100400 {
+			compatible = "allwinner,sun50i-h6-usb-phy";
+			reg = <0x05100400 0x14>,
+			      <0x05101800 0x4>,
+			      <0x05311800 0x4>;
+			reg-names = "phy_ctrl",
+				    "pmu0",
+				    "pmu3";
+			clocks = <&ccu CLK_USB_PHY0>,
+				 <&ccu CLK_USB_PHY3>;
+			clock-names = "usb0_phy",
+				      "usb3_phy";
+			resets = <&ccu RST_USB_PHY0>,
+				 <&ccu RST_USB_PHY3>;
+			reset-names = "usb0_reset",
+				      "usb3_reset";
+			status = "disabled";
+			#phy-cells = <1>;
+		};
+
+		ehci0: usb@5101000 {
+			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
+			reg = <0x05101000 0x100>;
+			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_BUS_EHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>,
+				 <&ccu RST_BUS_EHCI0>;
+			status = "disabled";
+		};
+
+		ohci0: usb@5101400 {
+			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
+			reg = <0x05101400 0x100>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI0>,
+				 <&ccu CLK_USB_OHCI0>;
+			resets = <&ccu RST_BUS_OHCI0>;
+			status = "disabled";
+		};
+
+		usb3phy: phy@5210000 {
+			compatible = "allwinner,sun50i-h6-usb3-phy";
+			reg = <0x5210000 0x10000>;
+			clocks = <&ccu CLK_USB_PHY1>;
+			resets = <&ccu RST_USB_PHY1>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		ehci3: usb@5311000 {
+			compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
+			reg = <0x05311000 0x100>;
+			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI3>,
+				 <&ccu CLK_BUS_EHCI3>,
+				 <&ccu CLK_USB_OHCI3>;
+			resets = <&ccu RST_BUS_OHCI3>,
+				 <&ccu RST_BUS_EHCI3>;
+			phys = <&usb2phy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
+		ohci3: usb@5311400 {
+			compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
+			reg = <0x05311400 0x100>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_OHCI3>,
+				 <&ccu CLK_USB_OHCI3>;
+			resets = <&ccu RST_BUS_OHCI3>;
+			phys = <&usb2phy 3>;
+			phy-names = "usb";
+			status = "disabled";
+		};
+
 		r_ccu: clock@7010000 {
 			compatible = "allwinner,sun50i-h6-r-ccu";
 			reg = <0x07010000 0x400>;
-- 
2.17.1

[PATCH v2 4/9] arm64: allwinner: dts: h6: add USB Vbus regulator

[Icenowy Zheng]

The 5V output of the USB ports on Pine H64 is controlled via a GPIO.

Add the USB Vbus regulator device tree node.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 2e97173c9204..31920d7d6666 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -39,6 +39,16 @@
 			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
 		};
 	};
+
+	reg_usb_vbus: vbus {
+		compatible = "regulator-fixed";
+		regulator-name = "usb-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		startup-delay-us = <100000>;
+		gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
 };
 
 &r_i2c {
-- 
2.17.1

[PATCH v2 5/9] arm64: allwinner: dts: h6: enable USB2 on Pine H64

[Icenowy Zheng]

Pine H64 board has both the USB2 OTG port and the USB2 host port on H6
SoC wired out to USB Type-A port.

Enable them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
 .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 27 +++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 31920d7d6666..104369228994 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -51,6 +51,22 @@
 	};
 };
 
+&ehci0 {
+	status = "okay";
+};
+
+&ehci3 {
+	status = "okay";
+};
+
+&ohci0 {
+	status = "okay";
+};
+
+&ohci3 {
+	status = "okay";
+};
+
 &r_i2c {
 	status = "okay";
 
@@ -66,3 +82,14 @@
 	pinctrl-0 = <&uart0_ph_pins>;
 	status = "okay";
 };
+
+&usb2otg {
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usb2phy {
+	usb0_vbus-supply = <&reg_usb_vbus>;
+	usb3_vbus-supply = <&reg_usb_vbus>;
+	status = "okay";
+};
-- 
2.17.1

[PATCH v2 6/9] dt-bindings: phy: add binding for Allwinner USB3 PHY

[Icenowy Zheng]

The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
external USB3 pins of the SoC.

Add a device tree binding for the PHY.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Splitted from the PHY driver patch in v1.

 .../bindings/phy/sun50i-usb3-phy.txt          | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt

diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
new file mode 100644
index 000000000000..912d55f9f69d
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
@@ -0,0 +1,24 @@
+Allwinner sun50i USB3 PHY
+-----------------------
+
+Required properties:
+- compatible : should be one of
+  * allwinner,sun60i-h6-usb3-phy
+- reg : a list of offset + length pairs
+- #phy-cells : from the generic phy bindings, must be 0
+- clocks : phandle + clock specifier for the phy clock
+- resets : phandle + reset specifier for the phy reset
+
+Optional Properties:
+- phy-supply : from the generic phy bindings, a phandle to a regulator that
+	       provides power to VBUS.
+
+Example:
+	usb3phy: phy@5210000 {
+		compatible = "allwinner,sun50i-h6-usb3-phy";
+		reg = <0x5210000 0x10000>;
+		clocks = <&ccu CLK_USB_PHY1>;
+		resets = <&ccu RST_USB_PHY1>;
+		#phy-cells = <0>;
+		status = "disabled";
+	};
-- 
2.17.1

[PATCH v2 7/9] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC

[Icenowy Zheng]

Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
controlled).

Add a driver for it.

The register operations in this driver is mainly extracted from the BSP
USB3 driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v2:
- Splitted out the DT binding.

 drivers/phy/allwinner/Kconfig           |  13 ++
 drivers/phy/allwinner/Makefile          |   1 +
 drivers/phy/allwinner/phy-sun50i-usb3.c | 194 ++++++++++++++++++++++++
 3 files changed, 208 insertions(+)
 create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c

diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
index cdc1e745ba47..cf373bcee034 100644
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -29,3 +29,16 @@ config PHY_SUN9I_USB
 	  sun9i SoCs.
 
 	  This driver controls each individual USB 2 host PHY.
+
+config PHY_SUN50I_USB3
+	tristate "Allwinner sun50i SoC USB3 PHY driver"
+	depends on ARCH_SUNXI && HAS_IOMEM && OF
+	depends on RESET_CONTROLLER
+	depends on USB_SUPPORT
+	select USB_COMMON
+	select GENERIC_PHY
+	help
+	  Enable this to support the USB3.0-capable transceiver that is
+	  part of some Allwinner sun50i SoCs.
+
+	  This driver controls each individual USB 2+3 host PHY combo.
diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
index 8605529c01a1..a8d01e9073c2 100644
--- a/drivers/phy/allwinner/Makefile
+++ b/drivers/phy/allwinner/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
 obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
+obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c
new file mode 100644
index 000000000000..226c99c2d664
--- /dev/null
+++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Allwinner sun50i(H6) USB 3.0 phy driver
+ *
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * Based on phy-sun9i-usb.c, which is:
+ *
+ * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
+ *
+ * Based on code from Allwinner BSP, which is:
+ *
+ * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/phy/phy.h>
+#include <linux/usb/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+/* Interface Status and Control Registers */
+#define SUNXI_ISCR			0x00
+#define SUNXI_PIPE_CLOCK_CONTROL	0x14
+#define SUNXI_PHY_TUNE_LOW		0x18
+#define SUNXI_PHY_TUNE_HIGH		0x1c
+#define SUNXI_PHY_EXTERNAL_CONTROL	0x20
+
+/* USB2.0 Interface Status and Control Register */
+#define SUNXI_ISCR_FORCE_VBUS		(3 << 12)
+
+/* PIPE Clock Control Register */
+#define SUNXI_PCC_PIPE_CLK_OPEN		(1 << 6)
+
+/* PHY External Control Register */
+#define SUNXI_PEC_EXTERN_VBUS		(3 << 1)
+#define SUNXI_PEC_SSC_EN		(1 << 24)
+#define SUNXI_PEC_REF_SSP_EN		(1 << 26)
+
+/* PHY Tune High Register */
+#define SUNXI_TX_DEEMPH_3P5DB(n)	((n) << 19)
+#define SUNXI_TX_DEEMPH_3P5DB_MASK	GENMASK(24, 19)
+#define SUNXI_TX_DEEMPH_6DB(n)		((n) << 13)
+#define SUNXI_TX_DEEMPH_6GB_MASK	GENMASK(18, 13)
+#define SUNXI_TX_SWING_FULL(n)		((n) << 6)
+#define SUNXI_TX_SWING_FULL_MASK	GENMASK(12, 6)
+#define SUNXI_LOS_BIAS(n)		((n) << 3)
+#define SUNXI_LOS_BIAS_MASK		GENMASK(5, 3)
+#define SUNXI_TXVBOOSTLVL(n)		((n) << 0)
+#define SUNXI_TXVBOOSTLVL_MASK		GENMASK(0, 2)
+
+struct sun50i_usb3_phy {
+	struct phy *phy;
+	void __iomem *regs;
+	struct reset_control *reset;
+	struct clk *clk;
+};
+
+static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
+{
+	u32 val;
+
+	val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
+	val |= SUNXI_PEC_EXTERN_VBUS;
+	val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
+	writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
+
+	val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
+	val |= SUNXI_PCC_PIPE_CLK_OPEN;
+	writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
+
+	val = readl(phy->regs + SUNXI_ISCR);
+	val |= SUNXI_ISCR_FORCE_VBUS;
+	writel(val, phy->regs + SUNXI_ISCR);
+
+	/*
+	 * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
+	 * registers are directly taken from the BSP USB3 driver from
+	 * Allwiner.
+	 */
+	writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
+
+	val = readl(phy->regs + SUNXI_PHY_TUNE_HIGH);
+	val &= ~(SUNXI_TXVBOOSTLVL_MASK | SUNXI_LOS_BIAS_MASK |
+		 SUNXI_TX_SWING_FULL_MASK | SUNXI_TX_DEEMPH_6GB_MASK |
+		 SUNXI_TX_DEEMPH_3P5DB_MASK);
+	val |= SUNXI_TXVBOOSTLVL(0x7);
+	val |= SUNXI_LOS_BIAS(0x7);
+	val |= SUNXI_TX_SWING_FULL(0x55);
+	val |= SUNXI_TX_DEEMPH_6DB(0x20);
+	val |= SUNXI_TX_DEEMPH_3P5DB(0x15);
+	writel(val, phy->regs + SUNXI_PHY_TUNE_HIGH);
+}
+
+static int sun50i_usb3_phy_init(struct phy *_phy)
+{
+	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
+	int ret;
+
+	ret = clk_prepare_enable(phy->clk);
+	if (ret)
+		goto err_clk;
+
+	ret = reset_control_deassert(phy->reset);
+	if (ret)
+		goto err_reset;
+
+	sun50i_usb3_phy_open(phy);
+	return 0;
+
+err_reset:
+	clk_disable_unprepare(phy->clk);
+
+err_clk:
+	return ret;
+}
+
+static int sun50i_usb3_phy_exit(struct phy *_phy)
+{
+	struct sun50i_usb3_phy *phy = phy_get_drvdata(_phy);
+
+	reset_control_assert(phy->reset);
+	clk_disable_unprepare(phy->clk);
+
+	return 0;
+}
+
+static const struct phy_ops sun50i_usb3_phy_ops = {
+	.init		= sun50i_usb3_phy_init,
+	.exit		= sun50i_usb3_phy_exit,
+	.owner		= THIS_MODULE,
+};
+
+static int sun50i_usb3_phy_probe(struct platform_device *pdev)
+{
+	struct sun50i_usb3_phy *phy;
+	struct device *dev = &pdev->dev;
+	struct phy_provider *phy_provider;
+	struct resource *res;
+
+	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
+	if (!phy)
+		return -ENOMEM;
+
+	phy->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(phy->clk)) {
+		dev_err(dev, "failed to get phy clock\n");
+		return PTR_ERR(phy->clk);
+	}
+
+	phy->reset = devm_reset_control_get(dev, NULL);
+	if (IS_ERR(phy->reset)) {
+		dev_err(dev, "failed to get reset control\n");
+		return PTR_ERR(phy->reset);
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	phy->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(phy->regs))
+		return PTR_ERR(phy->regs);
+
+	phy->phy = devm_phy_create(dev, NULL, &sun50i_usb3_phy_ops);
+	if (IS_ERR(phy->phy)) {
+		dev_err(dev, "failed to create PHY\n");
+		return PTR_ERR(phy->phy);
+	}
+
+	phy_set_drvdata(phy->phy, phy);
+	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+	return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id sun50i_usb3_phy_of_match[] = {
+	{ .compatible = "allwinner,sun50i-h6-usb3-phy" },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, sun50i_usb3_phy_of_match);
+
+static struct platform_driver sun50i_usb3_phy_driver = {
+	.probe	= sun50i_usb3_phy_probe,
+	.driver = {
+		.of_match_table	= sun50i_usb3_phy_of_match,
+		.name  = "sun50i-usb3-phy",
+	}
+};
+module_platform_driver(sun50i_usb3_phy_driver);
+
+MODULE_DESCRIPTION("Allwinner sun50i USB 3.0 phy driver");
+MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>");
+MODULE_LICENSE("GPL");
-- 
2.17.1

[PATCH v2 8/9] arm64: allwinner: dts: h6: add USB3 device nodes

[Icenowy Zheng]

Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.

Add device tree nodes for them.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v2:
- Rebased on top of the USB2 support patch.
- Dropped the dwc3-of-simple device.

 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 62fc0f5e10ba..6738e97ee37f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -229,6 +229,30 @@
 			status = "disabled";
 		};
 
+		dwc3: dwc3 {
+			compatible = "snps,dwc3";
+			reg = <0x5200000 0x10000>;
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+			/* The only clock is shared. */
+			clocks = <&ccu CLK_BUS_XHCI>,
+				 <&ccu CLK_BUS_XHCI>,
+				 <&ccu CLK_BUS_XHCI>;
+			clock-names = "ref", "bus_early", "suspend";
+			resets = <&ccu RST_BUS_XHCI>;
+			/*
+			 * The datasheet of the chip doesn't declare the
+			 * peripheral function, and there's no boards known
+			 * to have a USB Type-B port routed to the port.
+			 * In addition, no one has tested the peripheral
+			 * function yet.
+			 * So set the dr_mode to "host" in the DTSI file.
+			 */
+			dr_mode = "host";
+			phys = <&usb3phy>;
+			phy-names = "usb3-phy";
+			status = "disabled";
+		};
+
 		usb3phy: phy@5210000 {
 			compatible = "allwinner,sun50i-h6-usb3-phy";
 			reg = <0x5210000 0x10000>;
-- 
2.17.1

[PATCH v2 9/9] arm64: allwinner: dts: h6: enable USB3 port on Pine H64

[Icenowy Zheng]

Pine H64 board have a USB3 port, which is connected to the USB3 pins of
the H6 SoC, and the 5V power supply is controlled via GPIO (shared with
the power USB ports).

Enable this port.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v2:
- Rebased on top of the USB2 support patches.
- Dropped the enable of the dwc3-of-simple node.

 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 104369228994..28eeb8dcfa35 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -51,6 +51,10 @@
 	};
 };
 
+&dwc3 {
+	status = "okay";
+};
+
 &ehci0 {
 	status = "okay";
 };
@@ -93,3 +97,8 @@
 	usb3_vbus-supply = <&reg_usb_vbus>;
 	status = "okay";
 };
+
+&usb3phy {
+	phy-supply = <&reg_usb_vbus>;
+	status = "okay";
+};
-- 
2.17.1

Re: [linux-sunxi] [PATCH v2 3/9] arm64: allwinner: dts: h6: add USB2-related device nodes

[Chen-Yu Tsai]

On Fri, Jul 6, 2018 at 11:37 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> Allwinner H6 has two USB2 ports, one OTG and one host-only.
>
> Add device tree nodes related to them.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 90 ++++++++++++++++++++
>  1 file changed, 90 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index c72da8cd9ef5..62fc0f5e10ba 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -174,6 +174,96 @@
>                         status = "disabled";
>                 };
>
> +               usb2otg: usb@5100000 {
> +                       compatible = "allwinner,sun8i-a33-musb";
> +                       reg = <0x05100000 0x0400>;
> +                       clocks = <&ccu CLK_BUS_OTG>;
> +                       resets = <&ccu RST_BUS_OTG>;
> +                       interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +                       interrupt-names = "mc";
> +                       phys = <&usb2phy 0>;
> +                       phy-names = "usb";
> +                       extcon = <&usb2phy 0>;
> +                       status = "disabled";
> +               };
> +
> +               usb2phy: phy@5100400 {
> +                       compatible = "allwinner,sun50i-h6-usb-phy";
> +                       reg = <0x05100400 0x14>,
> +                             <0x05101800 0x4>,
> +                             <0x05311800 0x4>;
> +                       reg-names = "phy_ctrl",
> +                                   "pmu0",
> +                                   "pmu3";
> +                       clocks = <&ccu CLK_USB_PHY0>,
> +                                <&ccu CLK_USB_PHY3>;
> +                       clock-names = "usb0_phy",
> +                                     "usb3_phy";
> +                       resets = <&ccu RST_USB_PHY0>,
> +                                <&ccu RST_USB_PHY3>;
> +                       reset-names = "usb0_reset",
> +                                     "usb3_reset";
> +                       status = "disabled";
> +                       #phy-cells = <1>;
> +               };
> +
> +               ehci0: usb@5101000 {
> +                       compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
> +                       reg = <0x05101000 0x100>;
> +                       interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI0>,
> +                                <&ccu CLK_BUS_EHCI0>,
> +                                <&ccu CLK_USB_OHCI0>;
> +                       resets = <&ccu RST_BUS_OHCI0>,
> +                                <&ccu RST_BUS_EHCI0>;
> +                       status = "disabled";
> +               };
> +
> +               ohci0: usb@5101400 {
> +                       compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
> +                       reg = <0x05101400 0x100>;
> +                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI0>,
> +                                <&ccu CLK_USB_OHCI0>;
> +                       resets = <&ccu RST_BUS_OHCI0>;
> +                       status = "disabled";
> +               };
> +
> +               usb3phy: phy@5210000 {

Maybe you should split this one out and put it in the USB 3.0 patch?

ChenYu

> +                       compatible = "allwinner,sun50i-h6-usb3-phy";
> +                       reg = <0x5210000 0x10000>;
> +                       clocks = <&ccu CLK_USB_PHY1>;
> +                       resets = <&ccu RST_USB_PHY1>;
> +                       #phy-cells = <0>;
> +                       status = "disabled";
> +               };
> +
> +               ehci3: usb@5311000 {
> +                       compatible = "allwinner,sun50i-h6-ehci", "generic-ehci";
> +                       reg = <0x05311000 0x100>;
> +                       interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI3>,
> +                                <&ccu CLK_BUS_EHCI3>,
> +                                <&ccu CLK_USB_OHCI3>;
> +                       resets = <&ccu RST_BUS_OHCI3>,
> +                                <&ccu RST_BUS_EHCI3>;
> +                       phys = <&usb2phy 3>;
> +                       phy-names = "usb";
> +                       status = "disabled";
> +               };
> +
> +               ohci3: usb@5311400 {
> +                       compatible = "allwinner,sun50i-h6-ohci", "generic-ohci";
> +                       reg = <0x05311400 0x100>;
> +                       interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&ccu CLK_BUS_OHCI3>,
> +                                <&ccu CLK_USB_OHCI3>;
> +                       resets = <&ccu RST_BUS_OHCI3>;
> +                       phys = <&usb2phy 3>;
> +                       phy-names = "usb";
> +                       status = "disabled";
> +               };
> +
>                 r_ccu: clock@7010000 {
>                         compatible = "allwinner,sun50i-h6-r-ccu";
>                         reg = <0x07010000 0x400>;
> --
> 2.17.1
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

Re: [linux-sunxi] [PATCH v2 3/9] arm64: allwinner: dts: h6: add USB2-related device nodes

[Icenowy Zheng]

于 2018年7月7日 GMT+08:00 上午11:31:39, Chen-Yu Tsai <wens@csie.org> 写到:
>On Fri, Jul 6, 2018 at 11:37 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>> Allwinner H6 has two USB2 ports, one OTG and one host-only.
>>
>> Add device tree nodes related to them.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 90
>++++++++++++++++++++
>>  1 file changed, 90 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> index c72da8cd9ef5..62fc0f5e10ba 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> @@ -174,6 +174,96 @@
>>                         status = "disabled";
>>                 };
>>
>> +               usb2otg: usb@5100000 {
>> +                       compatible = "allwinner,sun8i-a33-musb";
>> +                       reg = <0x05100000 0x0400>;
>> +                       clocks = <&ccu CLK_BUS_OTG>;
>> +                       resets = <&ccu RST_BUS_OTG>;
>> +                       interrupts = <GIC_SPI 23
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       interrupt-names = "mc";
>> +                       phys = <&usb2phy 0>;
>> +                       phy-names = "usb";
>> +                       extcon = <&usb2phy 0>;
>> +                       status = "disabled";
>> +               };
>> +
>> +               usb2phy: phy@5100400 {
>> +                       compatible = "allwinner,sun50i-h6-usb-phy";
>> +                       reg = <0x05100400 0x14>,
>> +                             <0x05101800 0x4>,
>> +                             <0x05311800 0x4>;
>> +                       reg-names = "phy_ctrl",
>> +                                   "pmu0",
>> +                                   "pmu3";
>> +                       clocks = <&ccu CLK_USB_PHY0>,
>> +                                <&ccu CLK_USB_PHY3>;
>> +                       clock-names = "usb0_phy",
>> +                                     "usb3_phy";
>> +                       resets = <&ccu RST_USB_PHY0>,
>> +                                <&ccu RST_USB_PHY3>;
>> +                       reset-names = "usb0_reset",
>> +                                     "usb3_reset";
>> +                       status = "disabled";
>> +                       #phy-cells = <1>;
>> +               };
>> +
>> +               ehci0: usb@5101000 {
>> +                       compatible = "allwinner,sun50i-h6-ehci",
>"generic-ehci";
>> +                       reg = <0x05101000 0x100>;
>> +                       interrupts = <GIC_SPI 24
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&ccu CLK_BUS_OHCI0>,
>> +                                <&ccu CLK_BUS_EHCI0>,
>> +                                <&ccu CLK_USB_OHCI0>;
>> +                       resets = <&ccu RST_BUS_OHCI0>,
>> +                                <&ccu RST_BUS_EHCI0>;
>> +                       status = "disabled";
>> +               };
>> +
>> +               ohci0: usb@5101400 {
>> +                       compatible = "allwinner,sun50i-h6-ohci",
>"generic-ohci";
>> +                       reg = <0x05101400 0x100>;
>> +                       interrupts = <GIC_SPI 25
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&ccu CLK_BUS_OHCI0>,
>> +                                <&ccu CLK_USB_OHCI0>;
>> +                       resets = <&ccu RST_BUS_OHCI0>;
>> +                       status = "disabled";
>> +               };
>> +
>> +               usb3phy: phy@5210000 {
>
>Maybe you should split this one out and put it in the USB 3.0 patch?

Sorry, -EREBASE.

>
>ChenYu
>
>> +                       compatible = "allwinner,sun50i-h6-usb3-phy";
>> +                       reg = <0x5210000 0x10000>;
>> +                       clocks = <&ccu CLK_USB_PHY1>;
>> +                       resets = <&ccu RST_USB_PHY1>;
>> +                       #phy-cells = <0>;
>> +                       status = "disabled";
>> +               };
>> +
>> +               ehci3: usb@5311000 {
>> +                       compatible = "allwinner,sun50i-h6-ehci",
>"generic-ehci";
>> +                       reg = <0x05311000 0x100>;
>> +                       interrupts = <GIC_SPI 28
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&ccu CLK_BUS_OHCI3>,
>> +                                <&ccu CLK_BUS_EHCI3>,
>> +                                <&ccu CLK_USB_OHCI3>;
>> +                       resets = <&ccu RST_BUS_OHCI3>,
>> +                                <&ccu RST_BUS_EHCI3>;
>> +                       phys = <&usb2phy 3>;
>> +                       phy-names = "usb";
>> +                       status = "disabled";
>> +               };
>> +
>> +               ohci3: usb@5311400 {
>> +                       compatible = "allwinner,sun50i-h6-ohci",
>"generic-ohci";
>> +                       reg = <0x05311400 0x100>;
>> +                       interrupts = <GIC_SPI 29
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       clocks = <&ccu CLK_BUS_OHCI3>,
>> +                                <&ccu CLK_USB_OHCI3>;
>> +                       resets = <&ccu RST_BUS_OHCI3>;
>> +                       phys = <&usb2phy 3>;
>> +                       phy-names = "usb";
>> +                       status = "disabled";
>> +               };
>> +
>>                 r_ccu: clock@7010000 {
>>                         compatible = "allwinner,sun50i-h6-r-ccu";
>>                         reg = <0x07010000 0x400>;
>> --
>> 2.17.1
>>
>> --
>> You received this message because you are subscribed to the Google
>Groups "linux-sunxi" group.
>> To unsubscribe from this group and stop receiving emails from it,
>send an email to linux-sunxi+unsubscribe@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.
>
>_______________________________________________
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>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [linux-sunxi] [PATCH v2 8/9] arm64: allwinner: dts: h6: add USB3 device nodes

[Chen-Yu Tsai]

On Fri, Jul 6, 2018 at 11:38 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
> a custom PHY.
>
> Add device tree nodes for them.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Changes in v2:
> - Rebased on top of the USB2 support patch.
> - Dropped the dwc3-of-simple device.
>
>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24 ++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 62fc0f5e10ba..6738e97ee37f 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -229,6 +229,30 @@
>                         status = "disabled";
>                 };
>
> +               dwc3: dwc3 {
> +                       compatible = "snps,dwc3";
> +                       reg = <0x5200000 0x10000>;
> +                       interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +                       /* The only clock is shared. */
> +                       clocks = <&ccu CLK_BUS_XHCI>,
> +                                <&ccu CLK_BUS_XHCI>,
> +                                <&ccu CLK_BUS_XHCI>;
> +                       clock-names = "ref", "bus_early", "suspend";

The diagram in the user manual also shows the low speed 32k oscillator
being fed into DWC3. Maybe someone with more knowledge of what the IP
block expects can give us a clue about which one of these it is.

ChenYu

> +                       resets = <&ccu RST_BUS_XHCI>;
> +                       /*
> +                        * The datasheet of the chip doesn't declare the
> +                        * peripheral function, and there's no boards known
> +                        * to have a USB Type-B port routed to the port.
> +                        * In addition, no one has tested the peripheral
> +                        * function yet.
> +                        * So set the dr_mode to "host" in the DTSI file.
> +                        */
> +                       dr_mode = "host";
> +                       phys = <&usb3phy>;
> +                       phy-names = "usb3-phy";
> +                       status = "disabled";
> +               };
> +
>                 usb3phy: phy@5210000 {
>                         compatible = "allwinner,sun50i-h6-usb3-phy";
>                         reg = <0x5210000 0x10000>;
> --
> 2.17.1
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.

Re: [linux-sunxi] [PATCH v2 8/9] arm64: allwinner: dts: h6: add USB3 device nodes

[Icenowy Zheng]

于 2018年7月7日 GMT+08:00 上午11:35:22, Chen-Yu Tsai <wens@csie.org> 写到:
>On Fri, Jul 6, 2018 at 11:38 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>> Allwinner H6 SoC features USB3 functionality, with a DWC3 controller
>and
>> a custom PHY.
>>
>> Add device tree nodes for them.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> Changes in v2:
>> - Rebased on top of the USB2 support patch.
>> - Dropped the dwc3-of-simple device.
>>
>>  arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 24
>++++++++++++++++++++
>>  1 file changed, 24 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> index 62fc0f5e10ba..6738e97ee37f 100644
>> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>> @@ -229,6 +229,30 @@
>>                         status = "disabled";
>>                 };
>>
>> +               dwc3: dwc3 {
>> +                       compatible = "snps,dwc3";
>> +                       reg = <0x5200000 0x10000>;
>> +                       interrupts = <GIC_SPI 26
>IRQ_TYPE_LEVEL_HIGH>;
>> +                       /* The only clock is shared. */
>> +                       clocks = <&ccu CLK_BUS_XHCI>,
>> +                                <&ccu CLK_BUS_XHCI>,
>> +                                <&ccu CLK_BUS_XHCI>;
>> +                       clock-names = "ref", "bus_early", "suspend";
>
>The diagram in the user manual also shows the low speed 32k oscillator
>being fed into DWC3. Maybe someone with more knowledge of what the IP
>block expects can give us a clue about which one of these it is.

If possible, I think it's suspend clock.

I have checked RK3399 clk tree and USB3 ref is just a gate
on 24M osc, and bus clock is surely CLK_BUS_XHCI.

>
>ChenYu
>
>> +                       resets = <&ccu RST_BUS_XHCI>;
>> +                       /*
>> +                        * The datasheet of the chip doesn't declare
>the
>> +                        * peripheral function, and there's no boards
>known
>> +                        * to have a USB Type-B port routed to the
>port.
>> +                        * In addition, no one has tested the
>peripheral
>> +                        * function yet.
>> +                        * So set the dr_mode to "host" in the DTSI
>file.
>> +                        */
>> +                       dr_mode = "host";
>> +                       phys = <&usb3phy>;
>> +                       phy-names = "usb3-phy";
>> +                       status = "disabled";
>> +               };
>> +
>>                 usb3phy: phy@5210000 {
>>                         compatible = "allwinner,sun50i-h6-usb3-phy";
>>                         reg = <0x5210000 0x10000>;
>> --
>> 2.17.1
>>
>> --
>> You received this message because you are subscribed to the Google
>Groups "linux-sunxi" group.
>> To unsubscribe from this group and stop receiving emails from it,
>send an email to linux-sunxi+unsubscribe@googlegroups.com.
>> For more options, visit https://groups.google.com/d/optout.

Re: [linux-sunxi] [PATCH v2 5/9] arm64: allwinner: dts: h6: enable USB2 on Pine H64

[Chen-Yu Tsai]

On Fri, Jul 6, 2018 at 11:38 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> Pine H64 board has both the USB2 OTG port and the USB2 host port on H6

Nit: USB* pins. A "port" implies something you can plug into.

ChenYu

> SoC wired out to USB Type-A port.
>
> Enable them.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

Re: [linux-sunxi] [PATCH v2 0/9] Allwinner H6 USB support

[Chen-Yu Tsai]

On Fri, Jul 6, 2018 at 11:37 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> This patchset introduces support for the USB ports (both USB2 and USB3)
> on the Allwinner H6 SoC.
>
> This revision adds the USB2 support, and places it before the USB3
> support. So only the USB3 part will have changelog in this revision.
>
> The first 5 PATCHes are the USB2 part, and the latter 4 PATCHes are the
> USB3 part.
>
> PATCH 1, 2, 6, 7 should go through the PHY tree, and the remaining
> patches should go through the armsoc tree via sunxi tree.
>
> Icenowy Zheng (9):
>   phy: sun4i-usb: add support for missing USB PHY index
>   phy: sun4i-usb: add support for H6 USB2 PHY
>   arm64: allwinner: dts: h6: add USB2-related device nodes
>   arm64: allwinner: dts: h6: add USB Vbus regulator
>   arm64: allwinner: dts: h6: enable USB2 on Pine H64
>   dt-bindings: phy: add binding for Allwinner USB3 PHY
>   phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC
>   arm64: allwinner: dts: h6: add USB3 device nodes
>   arm64: allwinner: dts: h6: enable USB3 port on Pine H64

Apart from my comments in a few patches, this series is

Reviewed-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH v2 7/9] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC

[Kishon Vijay Abraham I]

Hi,

On Friday 06 July 2018 09:08 PM, Icenowy Zheng wrote:
> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> controlled).
> 
> Add a driver for it.
> 
> The register operations in this driver is mainly extracted from the BSP
> USB3 driver.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Changes in v2:
> - Splitted out the DT binding.
> 
>  drivers/phy/allwinner/Kconfig           |  13 ++
>  drivers/phy/allwinner/Makefile          |   1 +
>  drivers/phy/allwinner/phy-sun50i-usb3.c | 194 ++++++++++++++++++++++++
>  3 files changed, 208 insertions(+)
>  create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c
> 
> diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
> index cdc1e745ba47..cf373bcee034 100644
> --- a/drivers/phy/allwinner/Kconfig
> +++ b/drivers/phy/allwinner/Kconfig
> @@ -29,3 +29,16 @@ config PHY_SUN9I_USB
>  	  sun9i SoCs.
>  
>  	  This driver controls each individual USB 2 host PHY.
> +
> +config PHY_SUN50I_USB3
> +	tristate "Allwinner sun50i SoC USB3 PHY driver"
> +	depends on ARCH_SUNXI && HAS_IOMEM && OF
> +	depends on RESET_CONTROLLER
> +	depends on USB_SUPPORT
> +	select USB_COMMON

Doesn't look like this driver depends on USB_SUPPORT.
> +	select GENERIC_PHY
> +	help
> +	  Enable this to support the USB3.0-capable transceiver that is
> +	  part of some Allwinner sun50i SoCs.
> +
> +	  This driver controls each individual USB 2+3 host PHY combo.
> diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
> index 8605529c01a1..a8d01e9073c2 100644
> --- a/drivers/phy/allwinner/Makefile
> +++ b/drivers/phy/allwinner/Makefile
> @@ -1,2 +1,3 @@
>  obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
>  obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
> +obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
> diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c
> new file mode 100644
> index 000000000000..226c99c2d664
> --- /dev/null
> +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
> @@ -0,0 +1,194 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Allwinner sun50i(H6) USB 3.0 phy driver
> + *
> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> + *
> + * Based on phy-sun9i-usb.c, which is:
> + *
> + * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
> + *
> + * Based on code from Allwinner BSP, which is:
> + *
> + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.

Does the BSP also use GPL license?
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/phy/phy.h>
> +#include <linux/usb/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +
> +/* Interface Status and Control Registers */
> +#define SUNXI_ISCR			0x00
> +#define SUNXI_PIPE_CLOCK_CONTROL	0x14
> +#define SUNXI_PHY_TUNE_LOW		0x18
> +#define SUNXI_PHY_TUNE_HIGH		0x1c
> +#define SUNXI_PHY_EXTERNAL_CONTROL	0x20
> +
> +/* USB2.0 Interface Status and Control Register */
> +#define SUNXI_ISCR_FORCE_VBUS		(3 << 12)
> +
> +/* PIPE Clock Control Register */
> +#define SUNXI_PCC_PIPE_CLK_OPEN		(1 << 6)
> +
> +/* PHY External Control Register */
> +#define SUNXI_PEC_EXTERN_VBUS		(3 << 1)
> +#define SUNXI_PEC_SSC_EN		(1 << 24)
> +#define SUNXI_PEC_REF_SSP_EN		(1 << 26)
> +
> +/* PHY Tune High Register */
> +#define SUNXI_TX_DEEMPH_3P5DB(n)	((n) << 19)
> +#define SUNXI_TX_DEEMPH_3P5DB_MASK	GENMASK(24, 19)
> +#define SUNXI_TX_DEEMPH_6DB(n)		((n) << 13)
> +#define SUNXI_TX_DEEMPH_6GB_MASK	GENMASK(18, 13)
> +#define SUNXI_TX_SWING_FULL(n)		((n) << 6)
> +#define SUNXI_TX_SWING_FULL_MASK	GENMASK(12, 6)
> +#define SUNXI_LOS_BIAS(n)		((n) << 3)
> +#define SUNXI_LOS_BIAS_MASK		GENMASK(5, 3)
> +#define SUNXI_TXVBOOSTLVL(n)		((n) << 0)
> +#define SUNXI_TXVBOOSTLVL_MASK		GENMASK(0, 2)
> +
> +struct sun50i_usb3_phy {
> +	struct phy *phy;
> +	void __iomem *regs;
> +	struct reset_control *reset;
> +	struct clk *clk;
> +};
> +
> +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
> +{
> +	u32 val;
> +
> +	val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
> +	val |= SUNXI_PEC_EXTERN_VBUS;
> +	val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
> +	writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
> +
> +	val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
> +	val |= SUNXI_PCC_PIPE_CLK_OPEN;
> +	writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
> +
> +	val = readl(phy->regs + SUNXI_ISCR);
> +	val |= SUNXI_ISCR_FORCE_VBUS;
> +	writel(val, phy->regs + SUNXI_ISCR);
> +
> +	/*
> +	 * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
> +	 * registers are directly taken from the BSP USB3 driver from
> +	 * Allwiner.

%s/Allwiner/Allwinner/
> +	 */
> +	writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);

PHY_TUNE_LOW should also configure individual parameters like how you've done
below for PHY_TUNE_HIGH.

Thanks
Kishon

Re: [PATCH v2 7/9] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC

[Chen-Yu Tsai]

On Mon, Jul 9, 2018 at 12:31 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
> Hi,
>
> On Friday 06 July 2018 09:08 PM, Icenowy Zheng wrote:
>> Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
>> controlled).
>>
>> Add a driver for it.
>>
>> The register operations in this driver is mainly extracted from the BSP
>> USB3 driver.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> Changes in v2:
>> - Splitted out the DT binding.
>>
>>  drivers/phy/allwinner/Kconfig           |  13 ++
>>  drivers/phy/allwinner/Makefile          |   1 +
>>  drivers/phy/allwinner/phy-sun50i-usb3.c | 194 ++++++++++++++++++++++++
>>  3 files changed, 208 insertions(+)
>>  create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c
>>
>> diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
>> index cdc1e745ba47..cf373bcee034 100644
>> --- a/drivers/phy/allwinner/Kconfig
>> +++ b/drivers/phy/allwinner/Kconfig
>> @@ -29,3 +29,16 @@ config PHY_SUN9I_USB
>>         sun9i SoCs.
>>
>>         This driver controls each individual USB 2 host PHY.
>> +
>> +config PHY_SUN50I_USB3
>> +     tristate "Allwinner sun50i SoC USB3 PHY driver"
>> +     depends on ARCH_SUNXI && HAS_IOMEM && OF
>> +     depends on RESET_CONTROLLER
>> +     depends on USB_SUPPORT
>> +     select USB_COMMON
>
> Doesn't look like this driver depends on USB_SUPPORT.
>> +     select GENERIC_PHY
>> +     help
>> +       Enable this to support the USB3.0-capable transceiver that is
>> +       part of some Allwinner sun50i SoCs.
>> +
>> +       This driver controls each individual USB 2+3 host PHY combo.
>> diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
>> index 8605529c01a1..a8d01e9073c2 100644
>> --- a/drivers/phy/allwinner/Makefile
>> +++ b/drivers/phy/allwinner/Makefile
>> @@ -1,2 +1,3 @@
>>  obj-$(CONFIG_PHY_SUN4I_USB)          += phy-sun4i-usb.o
>>  obj-$(CONFIG_PHY_SUN9I_USB)          += phy-sun9i-usb.o
>> +obj-$(CONFIG_PHY_SUN50I_USB3)                += phy-sun50i-usb3.o
>> diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c b/drivers/phy/allwinner/phy-sun50i-usb3.c
>> new file mode 100644
>> index 000000000000..226c99c2d664
>> --- /dev/null
>> +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
>> @@ -0,0 +1,194 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Allwinner sun50i(H6) USB 3.0 phy driver
>> + *
>> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
>> + *
>> + * Based on phy-sun9i-usb.c, which is:
>> + *
>> + * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
>> + *
>> + * Based on code from Allwinner BSP, which is:
>> + *
>> + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
>
> Does the BSP also use GPL license?

Yes they released it under the GPL license. It's still available here:

    https://github.com/allwinner-zh/linux-3.4-sunxi

But is now unmaintained.

ChenYu


>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/usb/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/reset.h>
>> +
>> +/* Interface Status and Control Registers */
>> +#define SUNXI_ISCR                   0x00
>> +#define SUNXI_PIPE_CLOCK_CONTROL     0x14
>> +#define SUNXI_PHY_TUNE_LOW           0x18
>> +#define SUNXI_PHY_TUNE_HIGH          0x1c
>> +#define SUNXI_PHY_EXTERNAL_CONTROL   0x20
>> +
>> +/* USB2.0 Interface Status and Control Register */
>> +#define SUNXI_ISCR_FORCE_VBUS                (3 << 12)
>> +
>> +/* PIPE Clock Control Register */
>> +#define SUNXI_PCC_PIPE_CLK_OPEN              (1 << 6)
>> +
>> +/* PHY External Control Register */
>> +#define SUNXI_PEC_EXTERN_VBUS                (3 << 1)
>> +#define SUNXI_PEC_SSC_EN             (1 << 24)
>> +#define SUNXI_PEC_REF_SSP_EN         (1 << 26)
>> +
>> +/* PHY Tune High Register */
>> +#define SUNXI_TX_DEEMPH_3P5DB(n)     ((n) << 19)
>> +#define SUNXI_TX_DEEMPH_3P5DB_MASK   GENMASK(24, 19)
>> +#define SUNXI_TX_DEEMPH_6DB(n)               ((n) << 13)
>> +#define SUNXI_TX_DEEMPH_6GB_MASK     GENMASK(18, 13)
>> +#define SUNXI_TX_SWING_FULL(n)               ((n) << 6)
>> +#define SUNXI_TX_SWING_FULL_MASK     GENMASK(12, 6)
>> +#define SUNXI_LOS_BIAS(n)            ((n) << 3)
>> +#define SUNXI_LOS_BIAS_MASK          GENMASK(5, 3)
>> +#define SUNXI_TXVBOOSTLVL(n)         ((n) << 0)
>> +#define SUNXI_TXVBOOSTLVL_MASK               GENMASK(0, 2)
>> +
>> +struct sun50i_usb3_phy {
>> +     struct phy *phy;
>> +     void __iomem *regs;
>> +     struct reset_control *reset;
>> +     struct clk *clk;
>> +};
>> +
>> +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
>> +{
>> +     u32 val;
>> +
>> +     val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
>> +     val |= SUNXI_PEC_EXTERN_VBUS;
>> +     val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
>> +     writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
>> +
>> +     val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
>> +     val |= SUNXI_PCC_PIPE_CLK_OPEN;
>> +     writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
>> +
>> +     val = readl(phy->regs + SUNXI_ISCR);
>> +     val |= SUNXI_ISCR_FORCE_VBUS;
>> +     writel(val, phy->regs + SUNXI_ISCR);
>> +
>> +     /*
>> +      * All the magic numbers written to the PHY_TUNE_{LOW_HIGH}
>> +      * registers are directly taken from the BSP USB3 driver from
>> +      * Allwiner.
>
> %s/Allwiner/Allwinner/
>> +      */
>> +     writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
>
> PHY_TUNE_LOW should also configure individual parameters like how you've done
> below for PHY_TUNE_HIGH.
>
> Thanks
> Kishon

Re: [linux-sunxi] Re: [PATCH v2 7/9] phy: allwinner: add phy driver for USB3 PHY on Allwinner H6 SoC

[Icenowy Zheng]

在 2018-07-09一的 10:01 +0530，'Kishon Vijay Abraham I' via linux-sunxi写道：
> Hi,
> 
> On Friday 06 July 2018 09:08 PM, Icenowy Zheng wrote:
> > Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> > controlled).
> > 
> > Add a driver for it.
> > 
> > The register operations in this driver is mainly extracted from the
> > BSP
> > USB3 driver.
> > 
> > Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> > ---
> > Changes in v2:
> > - Splitted out the DT binding.
> > 
> >  drivers/phy/allwinner/Kconfig           |  13 ++
> >  drivers/phy/allwinner/Makefile          |   1 +
> >  drivers/phy/allwinner/phy-sun50i-usb3.c | 194
> > ++++++++++++++++++++++++
> >  3 files changed, 208 insertions(+)
> >  create mode 100644 drivers/phy/allwinner/phy-sun50i-usb3.c
> > 
> > diff --git a/drivers/phy/allwinner/Kconfig
> > b/drivers/phy/allwinner/Kconfig
> > index cdc1e745ba47..cf373bcee034 100644
> > --- a/drivers/phy/allwinner/Kconfig
> > +++ b/drivers/phy/allwinner/Kconfig
> > @@ -29,3 +29,16 @@ config PHY_SUN9I_USB
> >  	  sun9i SoCs.
> >  
> >  	  This driver controls each individual USB 2 host PHY.
> > +
> > +config PHY_SUN50I_USB3
> > +	tristate "Allwinner sun50i SoC USB3 PHY driver"
> > +	depends on ARCH_SUNXI && HAS_IOMEM && OF
> > +	depends on RESET_CONTROLLER
> > +	depends on USB_SUPPORT
> > +	select USB_COMMON
> 
> Doesn't look like this driver depends on USB_SUPPORT.

Yes, it doesn't depend on USB_SUPPORT; however, it's a USB PHY.

> > +	select GENERIC_PHY
> > +	help
> > +	  Enable this to support the USB3.0-capable transceiver
> > that is
> > +	  part of some Allwinner sun50i SoCs.
> > +
> > +	  This driver controls each individual USB 2+3 host PHY
> > combo.
> > diff --git a/drivers/phy/allwinner/Makefile
> > b/drivers/phy/allwinner/Makefile
> > index 8605529c01a1..a8d01e9073c2 100644
> > --- a/drivers/phy/allwinner/Makefile
> > +++ b/drivers/phy/allwinner/Makefile
> > @@ -1,2 +1,3 @@
> >  obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
> >  obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
> > +obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
> > diff --git a/drivers/phy/allwinner/phy-sun50i-usb3.c
> > b/drivers/phy/allwinner/phy-sun50i-usb3.c
> > new file mode 100644
> > index 000000000000..226c99c2d664
> > --- /dev/null
> > +++ b/drivers/phy/allwinner/phy-sun50i-usb3.c
> > @@ -0,0 +1,194 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Allwinner sun50i(H6) USB 3.0 phy driver
> > + *
> > + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> > + *
> > + * Based on phy-sun9i-usb.c, which is:
> > + *
> > + * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
> > + *
> > + * Based on code from Allwinner BSP, which is:
> > + *
> > + * Copyright (c) 2010-2015 Allwinner Technology Co., Ltd.
> 
> Does the BSP also use GPL license?

See [1].

[1] https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/dri
vers/usb/host/xhci_sunxi.c

> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/err.h>
> > +#include <linux/io.h>
> > +#include <linux/module.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/usb/of.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/reset.h>
> > +
> > +/* Interface Status and Control Registers */
> > +#define SUNXI_ISCR			0x00
> > +#define SUNXI_PIPE_CLOCK_CONTROL	0x14
> > +#define SUNXI_PHY_TUNE_LOW		0x18
> > +#define SUNXI_PHY_TUNE_HIGH		0x1c
> > +#define SUNXI_PHY_EXTERNAL_CONTROL	0x20
> > +
> > +/* USB2.0 Interface Status and Control Register */
> > +#define SUNXI_ISCR_FORCE_VBUS		(3 << 12)
> > +
> > +/* PIPE Clock Control Register */
> > +#define SUNXI_PCC_PIPE_CLK_OPEN		(1 << 6)
> > +
> > +/* PHY External Control Register */
> > +#define SUNXI_PEC_EXTERN_VBUS		(3 << 1)
> > +#define SUNXI_PEC_SSC_EN		(1 << 24)
> > +#define SUNXI_PEC_REF_SSP_EN		(1 << 26)
> > +
> > +/* PHY Tune High Register */
> > +#define SUNXI_TX_DEEMPH_3P5DB(n)	((n) << 19)
> > +#define SUNXI_TX_DEEMPH_3P5DB_MASK	GENMASK(24, 19)
> > +#define SUNXI_TX_DEEMPH_6DB(n)		((n) << 13)
> > +#define SUNXI_TX_DEEMPH_6GB_MASK	GENMASK(18, 13)
> > +#define SUNXI_TX_SWING_FULL(n)		((n) << 6)
> > +#define SUNXI_TX_SWING_FULL_MASK	GENMASK(12, 6)
> > +#define SUNXI_LOS_BIAS(n)		((n) << 3)
> > +#define SUNXI_LOS_BIAS_MASK		GENMASK(5, 3)
> > +#define SUNXI_TXVBOOSTLVL(n)		((n) << 0)
> > +#define SUNXI_TXVBOOSTLVL_MASK		GENMASK(0, 2)
> > +
> > +struct sun50i_usb3_phy {
> > +	struct phy *phy;
> > +	void __iomem *regs;
> > +	struct reset_control *reset;
> > +	struct clk *clk;
> > +};
> > +
> > +static void sun50i_usb3_phy_open(struct sun50i_usb3_phy *phy)
> > +{
> > +	u32 val;
> > +
> > +	val = readl(phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
> > +	val |= SUNXI_PEC_EXTERN_VBUS;
> > +	val |= SUNXI_PEC_SSC_EN | SUNXI_PEC_REF_SSP_EN;
> > +	writel(val, phy->regs + SUNXI_PHY_EXTERNAL_CONTROL);
> > +
> > +	val = readl(phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
> > +	val |= SUNXI_PCC_PIPE_CLK_OPEN;
> > +	writel(val, phy->regs + SUNXI_PIPE_CLOCK_CONTROL);
> > +
> > +	val = readl(phy->regs + SUNXI_ISCR);
> > +	val |= SUNXI_ISCR_FORCE_VBUS;
> > +	writel(val, phy->regs + SUNXI_ISCR);
> > +
> > +	/*
> > +	 * All the magic numbers written to the
> > PHY_TUNE_{LOW_HIGH}
> > +	 * registers are directly taken from the BSP USB3 driver
> > from
> > +	 * Allwiner.
> 
> %s/Allwiner/Allwinner/
> > +	 */
> > +	writel(0x0047fc87, phy->regs + SUNXI_PHY_TUNE_LOW);
> 
> PHY_TUNE_LOW should also configure individual parameters like how
> you've done
> below for PHY_TUNE_HIGH.

Sorry the BSP doesn't contain any macros on it, only a comment says "It
is set 0x0047fc87 on bare-metal."

> 
> Thanks
> Kishon
> 

Re: [PATCH v2 6/9] dt-bindings: phy: add binding for Allwinner USB3 PHY

[Rob Herring]

On Fri, Jul 06, 2018 at 11:38:02PM +0800, Icenowy Zheng wrote:
> The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
> external USB3 pins of the SoC.
> 
> Add a device tree binding for the PHY.
> 
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Splitted from the PHY driver patch in v1.
> 
>  .../bindings/phy/sun50i-usb3-phy.txt          | 24 +++++++++++++++++++
>  1 file changed, 24 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> 
> diff --git a/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> new file mode 100644
> index 000000000000..912d55f9f69d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> @@ -0,0 +1,24 @@
> +Allwinner sun50i USB3 PHY
> +-----------------------
> +
> +Required properties:
> +- compatible : should be one of
> +  * allwinner,sun60i-h6-usb3-phy
> +- reg : a list of offset + length pairs
> +- #phy-cells : from the generic phy bindings, must be 0
> +- clocks : phandle + clock specifier for the phy clock
> +- resets : phandle + reset specifier for the phy reset
> +
> +Optional Properties:
> +- phy-supply : from the generic phy bindings, a phandle to a regulator that
> +	       provides power to VBUS.

Power to the phy or Vbus? If the latter only, then this property should 
be elsewhere (like a connector node).

> +
> +Example:
> +	usb3phy: phy@5210000 {
> +		compatible = "allwinner,sun50i-h6-usb3-phy";
> +		reg = <0x5210000 0x10000>;
> +		clocks = <&ccu CLK_USB_PHY1>;
> +		resets = <&ccu RST_USB_PHY1>;
> +		#phy-cells = <0>;
> +		status = "disabled";
> +	};
> -- 
> 2.17.1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 6/9] dt-bindings: phy: add binding for Allwinner USB3 PHY

[Icenowy Zheng]

于 2018年7月12日 GMT+08:00 上午12:13:56, Rob Herring <robh@kernel.org> 写到:
>On Fri, Jul 06, 2018 at 11:38:02PM +0800, Icenowy Zheng wrote:
>> The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
>> external USB3 pins of the SoC.
>> 
>> Add a device tree binding for the PHY.
>> 
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
>> ---
>> Splitted from the PHY driver patch in v1.
>> 
>>  .../bindings/phy/sun50i-usb3-phy.txt          | 24
>+++++++++++++++++++
>>  1 file changed, 24 insertions(+)
>>  create mode 100644
>Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
>> 
>> diff --git
>a/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
>b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
>> new file mode 100644
>> index 000000000000..912d55f9f69d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
>> @@ -0,0 +1,24 @@
>> +Allwinner sun50i USB3 PHY
>> +-----------------------
>> +
>> +Required properties:
>> +- compatible : should be one of
>> +  * allwinner,sun60i-h6-usb3-phy
>> +- reg : a list of offset + length pairs
>> +- #phy-cells : from the generic phy bindings, must be 0
>> +- clocks : phandle + clock specifier for the phy clock
>> +- resets : phandle + reset specifier for the phy reset
>> +
>> +Optional Properties:
>> +- phy-supply : from the generic phy bindings, a phandle to a
>regulator that
>> +	       provides power to VBUS.
>
>Power to the phy or Vbus? If the latter only, then this property should
>
>be elsewhere (like a connector node).

I don't think there's connector nodes for USB ports now.

And by checking existed device trees, use phy-supply on USB
phy is common. It's seen on Meson GXBB, RK3399 and Hi6220
in arch/arm64/boot/dts.

>
>> +
>> +Example:
>> +	usb3phy: phy@5210000 {
>> +		compatible = "allwinner,sun50i-h6-usb3-phy";
>> +		reg = <0x5210000 0x10000>;
>> +		clocks = <&ccu CLK_USB_PHY1>;
>> +		resets = <&ccu RST_USB_PHY1>;
>> +		#phy-cells = <0>;
>> +		status = "disabled";
>> +	};
>> -- 
>> 2.17.1
>> 
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree"
>in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2 6/9] dt-bindings: phy: add binding for Allwinner USB3 PHY

[Rob Herring]

On Wed, Jul 11, 2018 at 10:20 AM Icenowy Zheng <icenowy@aosc.io> wrote:
>
>
>
> 于 2018年7月12日 GMT+08:00 上午12:13:56, Rob Herring <robh@kernel.org> 写到:
> >On Fri, Jul 06, 2018 at 11:38:02PM +0800, Icenowy Zheng wrote:
> >> The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
> >> external USB3 pins of the SoC.
> >>
> >> Add a device tree binding for the PHY.
> >>
> >> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> ---
> >> Splitted from the PHY driver patch in v1.
> >>
> >>  .../bindings/phy/sun50i-usb3-phy.txt          | 24
> >+++++++++++++++++++
> >>  1 file changed, 24 insertions(+)
> >>  create mode 100644
> >Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> >>
> >> diff --git
> >a/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> >b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> >> new file mode 100644
> >> index 000000000000..912d55f9f69d
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
> >> @@ -0,0 +1,24 @@
> >> +Allwinner sun50i USB3 PHY
> >> +-----------------------
> >> +
> >> +Required properties:
> >> +- compatible : should be one of
> >> +  * allwinner,sun60i-h6-usb3-phy
> >> +- reg : a list of offset + length pairs
> >> +- #phy-cells : from the generic phy bindings, must be 0
> >> +- clocks : phandle + clock specifier for the phy clock
> >> +- resets : phandle + reset specifier for the phy reset
> >> +
> >> +Optional Properties:
> >> +- phy-supply : from the generic phy bindings, a phandle to a
> >regulator that
> >> +           provides power to VBUS.
> >
> >Power to the phy or Vbus? If the latter only, then this property should
> >
> >be elsewhere (like a connector node).
>
> I don't think there's connector nodes for USB ports now.

Yes, there's a recently added binding.

> And by checking existed device trees, use phy-supply on USB
> phy is common. It's seen on Meson GXBB, RK3399 and Hi6220
> in arch/arm64/boot/dts.

I don't doubt that the phy needs a supply, but that's not how you
described it. If it is needed for the phy, then it's okay to have it.
If it is for Vbus and not connected to the phy, then it is not okay.

Rob