From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Arnd Bergmann <arnd@arndb.de>
Cc: "Conor.Dooley" <conor.dooley@microchip.com>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Heiko Stübner" <heiko@sntech.de>, guoren <guoren@kernel.org>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>,
"open list" <linux-kernel@vger.kernel.org>,
devicetree@vger.kernel.org,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"Lad, Prabhakar" <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"Philipp Tomsich" <philipp.tomsich@vrull.eu>,
"Nathan Chancellor" <nathan@kernel.org>,
"Atish Patra" <atishp@rivosinc.com>,
"Anup Patel" <apatel@ventanamicro.com>,
"Tsukasa OI" <research_trasio@irq.a4lg.com>,
"Jisheng Zhang" <jszhang@kernel.org>,
"Mayuresh Chitale" <mchitale@ventanamicro.com>
Subject: Re: [RFC PATCH v6 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
Date: Mon, 9 Jan 2023 12:03:44 +0000 [thread overview]
Message-ID: <CA+V-a8u6jvR=EDeE3mAbDr6-06NoBJ7mwmi_Y9qVyHT+aC-9rg@mail.gmail.com> (raw)
In-Reply-To: <9017adf0-acd4-4c43-8aea-3579b214b477@app.fastmail.com>
On Sun, Jan 8, 2023 at 12:08 AM Arnd Bergmann <arnd@arndb.de> wrote:
>
> On Sat, Jan 7, 2023, at 23:10, Lad, Prabhakar wrote:
>
> >> > +
> >> > + memset(&thead_cmo_ops, 0x0, sizeof(thead_cmo_ops));
> >> > + if (IS_ENABLED(CONFIG_ERRATA_THEAD_CMO)) {
> >> > + thead_cmo_ops.clean_range = &thead_cmo_clean_range;
> >> > + thead_cmo_ops.inv_range = &thead_cmo_inval_range;
> >> > + thead_cmo_ops.flush_range = &thead_cmo_flush_range;
> >> > + riscv_noncoherent_register_cache_ops(&thead_cmo_ops);
> >> > + }
> >>
> >> The implementation here looks reasonable, just wonder whether
> >> the classification as an 'errata' makes sense. I would probably
> >> consider this a 'driver' at this point, but that's just
> >> a question of personal preference.
> >>
> > zicbom is a CPU feature that doesn't have any DT node and hence no
> > driver and similarly for T-HEAD SoC.
>
> A driver does not have to be a 'struct platform_driver' that
> matches to a device node, my point was more about what to
> name it, regardless of how the code is entered.
>
> > Also the arch_setup_dma_ops()
> > happens quite early before driver probing due to which we get WARN()
> > messages during bootup hence I have implemented it as errata; as
> > errata patching happens quite early.
>
> But there is no more patching here, just setting the
> function pointers, right?
>
Yes that's right.
> >> > +struct riscv_cache_ops {
> >> > + void (*clean_range)(unsigned long addr, unsigned long size);
> >> > + void (*inv_range)(unsigned long addr, unsigned long size);
> >> > + void (*flush_range)(unsigned long addr, unsigned long size);
> >> > + void (*riscv_dma_noncoherent_cmo_ops)(void *vaddr, size_t size,
> >> > + enum dma_data_direction dir,
> >> > + enum dma_noncoherent_ops ops);
> >> > +};
> >>
> >> I don't quite see how the fourth operation is used here.
> >> Are there cache controllers that need something beyond
> >> clean/inv/flush?
> >>
> > This is for platforms that dont follow standard cache operations (like
> > done in patch 5/6) and there drivers decide on the operations
> > depending on the ops and dir.
>
> My feeling is that the set of operations that get called should
> not depend on the cache controller but at best the CPU. I tried to
> enumerate how zicbom and ax45 differ here, and how that compares
> to other architectures:
>
> zicbom ax45,mips,arc arm arm64
> fromdevice clean/flush inval/inval inval/inval clean/inval
> todevice clean/- clean/- clean/- clean/-
> bidi flush/flush flush/inval clean/inval clean/inval
>
> So everyone does the same operation for DMA_TO_DEVICE, but
> they differ in the DMA_FROM_DEVICE handling, for reasons I
> don't quite see:
>
> Your ax45 code does the same as arc and mips. arm and
> arm64 skip invalidating the cache before bidi mappings,
> but arm has a FIXME comment about that. arm64 does a
> 'clean' instead of 'inval' when mapping a fromdevice
> page, which seems valid but slower than necessary.
>
> Could the zicbom operations be changed to do the same
> things as the ax45/mips/arc ones, or are there specific
> details in the zicbom spec that require this?
>
I'll let the RISC-V experts respond here.
Cheers,
Prabhakar
next prev parent reply other threads:[~2023-01-09 12:04 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-06 18:55 [PATCH v6 0/6] RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support for AX45MP Prabhakar
2023-01-06 18:55 ` [RFC PATCH v6 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management Prabhakar
2023-01-06 22:31 ` Arnd Bergmann
2023-01-06 23:29 ` Conor Dooley
2023-01-07 21:52 ` Arnd Bergmann
2023-01-07 22:21 ` Conor Dooley
2023-01-08 16:37 ` Conor Dooley
2023-01-07 22:10 ` Lad, Prabhakar
2023-01-08 0:07 ` Arnd Bergmann
2023-01-09 12:03 ` Lad, Prabhakar [this message]
2023-01-09 12:59 ` Arnd Bergmann
2023-01-09 13:27 ` Conor Dooley
2023-01-10 7:01 ` Christoph Hellwig
2023-01-10 15:03 ` Arnd Bergmann
2023-01-10 15:11 ` Will Deacon
2023-01-13 5:48 ` Christoph Hellwig
2023-01-20 17:04 ` Arnd Bergmann
2023-01-21 14:37 ` Christoph Hellwig
2023-01-21 19:30 ` Arnd Bergmann
2023-01-22 7:27 ` Christoph Hellwig
2023-01-22 11:04 ` Arnd Bergmann
2023-01-23 14:46 ` Christoph Hellwig
2023-01-06 23:47 ` Conor Dooley
2023-01-07 22:36 ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-01-06 18:55 ` [PATCH v6 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-01-06 21:44 ` Conor Dooley
2023-01-06 18:55 ` [PATCH v6 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-01-06 21:53 ` Conor Dooley
2023-01-07 20:43 ` Lad, Prabhakar
2023-01-09 12:15 ` Geert Uytterhoeven
2023-01-09 13:14 ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-01-07 0:09 ` Conor Dooley
2023-01-07 20:49 ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-01-06 23:49 ` Conor Dooley
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