From: Conor Dooley <conor@kernel.org>
To: Prabhakar <prabhakar.csengg@gmail.com>
Cc: Arnd Bergmann <arnd@arndb.de>,
Conor Dooley <conor.dooley@microchip.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>,
open list <linux-kernel@vger.kernel.org>,
devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Jisheng Zhang <jszhang@kernel.org>
Subject: Re: [PATCH v6 3/6] riscv: errata: Add Andes alternative ports
Date: Fri, 6 Jan 2023 21:44:47 +0000 [thread overview]
Message-ID: <Y7iWTwZwNLiU8USP@spud> (raw)
In-Reply-To: <20230106185526.260163-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
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On Fri, Jan 06, 2023 at 06:55:23PM +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add required ports of the Alternative scheme for Andes CPU cores.
>
> I/O Coherence Port (IOCP) provides an AXI interface for connecting external
> non-caching masters, such as DMA controllers. IOCP is a specification
> option and is disabled on the Renesas RZ/Five SoC due to this reason cache
> management needs a software workaround.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v5 -> v6
> * Dropped patching alternative and now just probing IOCP
>
> v4 -> v5
> * Sorted the Kconfig/Makefile/Switch based on Core name
> * Added a comments
> * Introduced RZFIVE_SBI_EXT_IOCP_SW_WORKAROUND SBI EXT ID to check if
> CMO needs to be applied. Is there a way we can access the DTB while patching
> as we can drop this SBI EXT ID and add a DT property instead for cmo?
>
> RFC v3 -> v4
> * New patch
> ---
> arch/riscv/Kconfig.erratas | 22 +++++++++
> arch/riscv/errata/Makefile | 1 +
> arch/riscv/errata/andes/Makefile | 1 +
> arch/riscv/errata/andes/errata.c | 71 ++++++++++++++++++++++++++++
> arch/riscv/include/asm/alternative.h | 3 ++
> arch/riscv/kernel/alternative.c | 5 ++
> 6 files changed, 103 insertions(+)
> create mode 100644 arch/riscv/errata/andes/Makefile
> create mode 100644 arch/riscv/errata/andes/errata.c
>
> diff --git a/arch/riscv/Kconfig.erratas b/arch/riscv/Kconfig.erratas
> index 69621ae6d647..f0f0c1abd52b 100644
> --- a/arch/riscv/Kconfig.erratas
> +++ b/arch/riscv/Kconfig.erratas
> @@ -1,5 +1,27 @@
> menu "CPU errata selection"
>
> +config ERRATA_ANDES
> + bool "Andes AX45MP errata"
> + depends on !XIP_KERNEL
> + select RISCV_ALTERNATIVE
> + help
> + All Andes errata Kconfig depend on this Kconfig. Disabling
> + this Kconfig will disable all Andes errata. Please say "Y"
> + here if your platform uses Andes CPU cores.
> +
> + Otherwise, please say "N" here to avoid unnecessary overhead.
> +
> +config ERRATA_ANDES_CMO
> + bool "Apply Andes cache management errata"
> + depends on ERRATA_ANDES && MMU && ARCH_R9A07G043
> + select RISCV_DMA_NONCOHERENT
> + default y
> + help
> + This will apply the cache management errata to handle the
> + non-standard handling on non-coherent operations on Andes cores.
> +
> + If you don't know what to do here, say "Y".
Ideally we would not need errata to turn this stuff on at all, but, as
you pointed out to me off-list, arch_setup_dma_ops() complains if we
have not set up.
I'm happy to commit to trying to sort that out in follow on work w/ MPFS,
since in that case it really isn't errata, and not require it for this
series as you do fit that particular bill IMO.
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Thanks,
Conor.
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next prev parent reply other threads:[~2023-01-06 21:45 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-06 18:55 [PATCH v6 0/6] RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support for AX45MP Prabhakar
2023-01-06 18:55 ` [RFC PATCH v6 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management Prabhakar
2023-01-06 22:31 ` Arnd Bergmann
2023-01-06 23:29 ` Conor Dooley
2023-01-07 21:52 ` Arnd Bergmann
2023-01-07 22:21 ` Conor Dooley
2023-01-08 16:37 ` Conor Dooley
2023-01-07 22:10 ` Lad, Prabhakar
2023-01-08 0:07 ` Arnd Bergmann
2023-01-09 12:03 ` Lad, Prabhakar
2023-01-09 12:59 ` Arnd Bergmann
2023-01-09 13:27 ` Conor Dooley
2023-01-10 7:01 ` Christoph Hellwig
2023-01-10 15:03 ` Arnd Bergmann
2023-01-10 15:11 ` Will Deacon
2023-01-13 5:48 ` Christoph Hellwig
2023-01-20 17:04 ` Arnd Bergmann
2023-01-21 14:37 ` Christoph Hellwig
2023-01-21 19:30 ` Arnd Bergmann
2023-01-22 7:27 ` Christoph Hellwig
2023-01-22 11:04 ` Arnd Bergmann
2023-01-23 14:46 ` Christoph Hellwig
2023-01-06 23:47 ` Conor Dooley
2023-01-07 22:36 ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-01-06 18:55 ` [PATCH v6 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-01-06 21:44 ` Conor Dooley [this message]
2023-01-06 18:55 ` [PATCH v6 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-01-06 21:53 ` Conor Dooley
2023-01-07 20:43 ` Lad, Prabhakar
2023-01-09 12:15 ` Geert Uytterhoeven
2023-01-09 13:14 ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-01-07 0:09 ` Conor Dooley
2023-01-07 20:49 ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-01-06 23:49 ` Conor Dooley
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