From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Conor Dooley <conor@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko@sntech.de>, Guo Ren <guoren@kernel.org>,
Andrew Jones <ajones@ventanamicro.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
linux-riscv@lists.infradead.org,
linux-renesas-soc@vger.kernel.org, Rob Herring <robh@kernel.org>
Subject: Re: [PATCH v6 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller
Date: Mon, 9 Jan 2023 13:14:47 +0000 [thread overview]
Message-ID: <CA+V-a8vHe5cjxQusxmnXKouw76gxGFdHL1g+n6-5JWFkhVECaA@mail.gmail.com> (raw)
In-Reply-To: <CAMuHMdW7bfJXo4FujuwEOOzNsdEWB60VYurdFdbO8GwTMwb5yA@mail.gmail.com>
Hi Geert,
Thanks for the feedback.
On Mon, Jan 9, 2023 at 12:15 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Sat, Jan 7, 2023 at 9:47 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Fri, Jan 6, 2023 at 9:53 PM Conor Dooley <conor@kernel.org> wrote:
> > > On Fri, Jan 06, 2023 at 06:55:24PM +0000, Prabhakar wrote:
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add DT binding documentation for L2 cache controller found on RZ/Five SoC.
> > > >
> > > > The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> > > > Single) from Andes. The AX45MP core has an L2 cache controller, this patch
> > > > describes the L2 cache block.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > Reviewed-by: Rob Herring <robh@kernel.org>
>
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml
> > > > @@ -0,0 +1,81 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > > > +# Copyright (C) 2022 Renesas Electronics Corp.
> > > > +%YAML 1.2
> > > > +---
> > > > +$id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
> > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > +
> > > > +title: Andestech AX45MP L2 Cache Controller
> > > > +
> > > > +maintainers:
> > > > + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > +
> > > > +description:
> > > > + A level-2 cache (L2C) is used to improve the system performance by providing
> > > > + a large amount of cache line entries and reasonable access delays. The L2C
> > > > + is shared between cores, and a non-inclusive non-exclusive policy is used.
> > > > +
> > > > +select:
> > > > + properties:
> > > > + compatible:
> > > > + contains:
> > > > + enum:
> > > > + - andestech,ax45mp-cache
> > > > +
> > > > + required:
> > > > + - compatible
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - const: andestech,ax45mp-cache
> > > > + - const: cache
> > >
> > > You might find value in a specific compatible for your SoC & enforce
> > > constraints for it. Or you might not & I don't care either way :)
> > >
> > Good point actually. Geert what do you think?
>
> That might be prudent, to cater for the way the standard AX45MP cache
> block is integrated into the RZ/Five (or any other) SoC.
>
> Still, in the absence of an SoC-specific compatible value, you can
> handle integration issues using soc_device_match().
>
Agreed, I'll continue with the current DT bindings.
Cheers,
Prabhakar
next prev parent reply other threads:[~2023-01-09 13:15 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-06 18:55 [PATCH v6 0/6] RISC-V non-coherent function pointer based cache management operations + non-coherent DMA support for AX45MP Prabhakar
2023-01-06 18:55 ` [RFC PATCH v6 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management Prabhakar
2023-01-06 22:31 ` Arnd Bergmann
2023-01-06 23:29 ` Conor Dooley
2023-01-07 21:52 ` Arnd Bergmann
2023-01-07 22:21 ` Conor Dooley
2023-01-08 16:37 ` Conor Dooley
2023-01-07 22:10 ` Lad, Prabhakar
2023-01-08 0:07 ` Arnd Bergmann
2023-01-09 12:03 ` Lad, Prabhakar
2023-01-09 12:59 ` Arnd Bergmann
2023-01-09 13:27 ` Conor Dooley
2023-01-10 7:01 ` Christoph Hellwig
2023-01-10 15:03 ` Arnd Bergmann
2023-01-10 15:11 ` Will Deacon
2023-01-13 5:48 ` Christoph Hellwig
2023-01-20 17:04 ` Arnd Bergmann
2023-01-21 14:37 ` Christoph Hellwig
2023-01-21 19:30 ` Arnd Bergmann
2023-01-22 7:27 ` Christoph Hellwig
2023-01-22 11:04 ` Arnd Bergmann
2023-01-23 14:46 ` Christoph Hellwig
2023-01-06 23:47 ` Conor Dooley
2023-01-07 22:36 ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-01-06 18:55 ` [PATCH v6 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-01-06 21:44 ` Conor Dooley
2023-01-06 18:55 ` [PATCH v6 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-01-06 21:53 ` Conor Dooley
2023-01-07 20:43 ` Lad, Prabhakar
2023-01-09 12:15 ` Geert Uytterhoeven
2023-01-09 13:14 ` Lad, Prabhakar [this message]
2023-01-06 18:55 ` [PATCH v6 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-01-07 0:09 ` Conor Dooley
2023-01-07 20:49 ` Lad, Prabhakar
2023-01-06 18:55 ` [PATCH v6 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-01-06 23:49 ` Conor Dooley
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