Re: [PATCH] x86/i8259: Work around buggy legacy PIC

From: "H. Peter Anvin" <hpa@zytor.com>
To: David Laight <David.Laight@ACULAB.COM>,
	"'Thomas Gleixner'" <tglx@linutronix.de>,
	Maximilian Luz <luzmaximilian@gmail.com>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>
Cc: Sachi King <nakato@nakato.io>, "x86@kernel.org" <x86@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH] x86/i8259: Work around buggy legacy PIC
Date: Fri, 14 May 2021 10:28:30 -0700	[thread overview]
Message-ID: <b29b5c28-c36d-9c03-fc1a-055d8a089bcd@zytor.com> (raw)
In-Reply-To: <f0f52e319c06462ea0b5fbba827df9e0@AcuMS.aculab.com>

On 5/14/21 9:12 AM, David Laight wrote:
> 
> A more interesting probe would be:
> - Write some value to register 1 - the mask.
> - Write 9 to register zero (selects interrupt in service register).
> - Read register 0 - should be zero since we aren't in as ISR.
> - Read register 1 - should get the mask back.
> You can also write 8 to register 0, reads then return the pending interrupts.
> Their might be pending interrupts - so that value can't be checked.
> 
> But if reads start returning the last written value you might only
> have capacitors on the data bus.

What data bus? These things haven't been on a physical parallel bus for 
ages.

> The required initialisation registers are pretty fixed for the PC hardware.
> But finding the values requires a bit of work.
> 
> 	David

And you always risk activating new bugs.

Since this appears to be a specific platform advertising the wrong 
answer in firmware, this is better handled as a quirk.

	-hpa