[PATCH 0/2] Add coresight support for QCOM SC7180 SoC

[PATCH 0/2] Add coresight support for QCOM SC7180 SoC

[Sai Prakash Ranjan]

Patch 1 adds the ETM PIDs for Kryo 4XX CPU cores and
Patch 2 adds the DT nodes for coresight components on SC7180.

Sai Prakash Ranjan (2):
  coresight: etm4x: Add support for Qualcomm SC7180 SoC
  arm64: dts: qcom: sc7180: Add Coresight support

 arch/arm64/boot/dts/qcom/sc7180.dtsi          | 507 ++++++++++++++++++
 drivers/hwtracing/coresight/coresight-etm4x.c |   2 +
 2 files changed, 509 insertions(+)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

[Sai Prakash Ranjan]

Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has
2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU
cores based on Cortex-A55.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index a90d757f7043..a153a65c4c5b 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {
 	CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
 	CS_AMBA_ID(0x000bb802),			/* Qualcomm Kryo 385 Cortex-A55 */
 	CS_AMBA_ID(0x000bb803),			/* Qualcomm Kryo 385 Cortex-A75 */
+	CS_AMBA_ID(0x000bb805),			/* Qualcomm Kryo 4XX Cortex-A55 */
+	CS_AMBA_ID(0x000bb804),			/* Qualcomm Kryo 4XX Cortex-A76 */
 	CS_AMBA_UCI_ID(0x000cc0af, uci_id_etm4),/* Marvell ThunderX2 */
 	{},
 };
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2020-03-20 00:44:28)
> Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has
> 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU
> cores based on Cortex-A55.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Stephen Boyd <swboyd@chromium.org>

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

[Suzuki K Poulose]

On 03/20/2020 07:44 AM, Sai Prakash Ranjan wrote:
> Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has
> 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU
> cores based on Cortex-A55.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>   drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index a90d757f7043..a153a65c4c5b 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {
>   	CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
>   	CS_AMBA_ID(0x000bb802),			/* Qualcomm Kryo 385 Cortex-A55 */
>   	CS_AMBA_ID(0x000bb803),			/* Qualcomm Kryo 385 Cortex-A75 */
> +	CS_AMBA_ID(0x000bb805),			/* Qualcomm Kryo 4XX Cortex-A55 */
> +	CS_AMBA_ID(0x000bb804),			/* Qualcomm Kryo 4XX Cortex-A76 */

Does the DEVARCH indicate that it is an ETMv4 ? (It should !) Please
could we enforce the UCI_ID check for these components ? The
moment you add CTI components to your board this could conflict with
them unless we check the UCI_ID for ETMv4.

Suzuki

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

[Sai Prakash Ranjan]

Hi Suzuki,

On 2020-03-23 15:25, Suzuki K Poulose wrote:
> On 03/20/2020 07:44 AM, Sai Prakash Ranjan wrote:
>> Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has
>> 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU
>> cores based on Cortex-A55.
>> 
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> ---
>>   drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
>>   1 file changed, 2 insertions(+)
>> 
>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c 
>> b/drivers/hwtracing/coresight/coresight-etm4x.c
>> index a90d757f7043..a153a65c4c5b 100644
>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
>> @@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {
>>   	CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
>>   	CS_AMBA_ID(0x000bb802),			/* Qualcomm Kryo 385 Cortex-A55 */
>>   	CS_AMBA_ID(0x000bb803),			/* Qualcomm Kryo 385 Cortex-A75 */
>> +	CS_AMBA_ID(0x000bb805),			/* Qualcomm Kryo 4XX Cortex-A55 */
>> +	CS_AMBA_ID(0x000bb804),			/* Qualcomm Kryo 4XX Cortex-A76 */
> 
> Does the DEVARCH indicate that it is an ETMv4 ? (It should !) Please
> could we enforce the UCI_ID check for these components ? The
> moment you add CTI components to your board this could conflict with
> them unless we check the UCI_ID for ETMv4.
> 

Yes I got these IDs through devarch and it does indicate that it is 
ETMv4.2.

devname=7040000.etm dev->type=0x13 devarch=0x47724a13
devname=7140000.etm dev->type=0x13 devarch=0x47724a13
devname=7240000.etm dev->type=0x13 devarch=0x47724a13
devname=7340000.etm dev->type=0x13 devarch=0x47724a13
devname=7440000.etm dev->type=0x13 devarch=0x47724a13
devname=7540000.etm dev->type=0x13 devarch=0x47724a13
devname=7640000.etm dev->type=0x13 devarch=0x47724a13
devname=7740000.etm dev->type=0x13 devarch=0x47724a13

I will add the UCI_ID as you suggested in next version.

Thanks,
Sai
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

[Suzuki K Poulose]

On 03/23/2020 11:32 AM, Sai Prakash Ranjan wrote:
> Hi Suzuki,
> 
> On 2020-03-23 15:25, Suzuki K Poulose wrote:
>> On 03/20/2020 07:44 AM, Sai Prakash Ranjan wrote:
>>> Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has
>>> 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU
>>> cores based on Cortex-A55.
>>>
>>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>>> ---
>>>   drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
>>>   1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c 
>>> b/drivers/hwtracing/coresight/coresight-etm4x.c
>>> index a90d757f7043..a153a65c4c5b 100644
>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
>>> @@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {
>>>       CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
>>>       CS_AMBA_ID(0x000bb802),            /* Qualcomm Kryo 385 
>>> Cortex-A55 */
>>>       CS_AMBA_ID(0x000bb803),            /* Qualcomm Kryo 385 
>>> Cortex-A75 */
>>> +    CS_AMBA_ID(0x000bb805),            /* Qualcomm Kryo 4XX 
>>> Cortex-A55 */
>>> +    CS_AMBA_ID(0x000bb804),            /* Qualcomm Kryo 4XX 
>>> Cortex-A76 */
>>
>> Does the DEVARCH indicate that it is an ETMv4 ? (It should !) Please
>> could we enforce the UCI_ID check for these components ? The
>> moment you add CTI components to your board this could conflict with
>> them unless we check the UCI_ID for ETMv4.
>>
> 
> Yes I got these IDs through devarch and it does indicate that it is 
> ETMv4.2.
> 
> devname=7040000.etm dev->type=0x13 devarch=0x47724a13
> devname=7140000.etm dev->type=0x13 devarch=0x47724a13
> devname=7240000.etm dev->type=0x13 devarch=0x47724a13
> devname=7340000.etm dev->type=0x13 devarch=0x47724a13
> devname=7440000.etm dev->type=0x13 devarch=0x47724a13
> devname=7540000.etm dev->type=0x13 devarch=0x47724a13
> devname=7640000.etm dev->type=0x13 devarch=0x47724a13
> devname=7740000.etm dev->type=0x13 devarch=0x47724a13
> 
> I will add the UCI_ID as you suggested in next version.

If you do have access to the Kryo 385 variants, please fix
them as well.

Cheers
Suzuki

Re: [PATCH 1/2] coresight: etm4x: Add support for Qualcomm SC7180 SoC

[Sai Prakash Ranjan]

On 2020-03-23 17:09, Suzuki K Poulose wrote:
> On 03/23/2020 11:32 AM, Sai Prakash Ranjan wrote:
>> Hi Suzuki,
>> 
>> On 2020-03-23 15:25, Suzuki K Poulose wrote:
>>> On 03/20/2020 07:44 AM, Sai Prakash Ranjan wrote:
>>>> Add ETM Peripheral IDs for Qualcomm SC7180 SoC. It has
>>>> 2 big CPU cores based on Cortex-A76 and 6 LITTLE CPU
>>>> cores based on Cortex-A55.
>>>> 
>>>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>>>> ---
>>>>   drivers/hwtracing/coresight/coresight-etm4x.c | 2 ++
>>>>   1 file changed, 2 insertions(+)
>>>> 
>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c 
>>>> b/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> index a90d757f7043..a153a65c4c5b 100644
>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
>>>> @@ -1556,6 +1556,8 @@ static const struct amba_id etm4_ids[] = {
>>>>       CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
>>>>       CS_AMBA_ID(0x000bb802),            /* Qualcomm Kryo 385 
>>>> Cortex-A55 */
>>>>       CS_AMBA_ID(0x000bb803),            /* Qualcomm Kryo 385 
>>>> Cortex-A75 */
>>>> +    CS_AMBA_ID(0x000bb805),            /* Qualcomm Kryo 4XX 
>>>> Cortex-A55 */
>>>> +    CS_AMBA_ID(0x000bb804),            /* Qualcomm Kryo 4XX 
>>>> Cortex-A76 */
>>> 
>>> Does the DEVARCH indicate that it is an ETMv4 ? (It should !) Please
>>> could we enforce the UCI_ID check for these components ? The
>>> moment you add CTI components to your board this could conflict with
>>> them unless we check the UCI_ID for ETMv4.
>>> 
>> 
>> Yes I got these IDs through devarch and it does indicate that it is 
>> ETMv4.2.
>> 
>> devname=7040000.etm dev->type=0x13 devarch=0x47724a13
>> devname=7140000.etm dev->type=0x13 devarch=0x47724a13
>> devname=7240000.etm dev->type=0x13 devarch=0x47724a13
>> devname=7340000.etm dev->type=0x13 devarch=0x47724a13
>> devname=7440000.etm dev->type=0x13 devarch=0x47724a13
>> devname=7540000.etm dev->type=0x13 devarch=0x47724a13
>> devname=7640000.etm dev->type=0x13 devarch=0x47724a13
>> devname=7740000.etm dev->type=0x13 devarch=0x47724a13
>> 
>> I will add the UCI_ID as you suggested in next version.
> 
> If you do have access to the Kryo 385 variants, please fix
> them as well.
> 

Sure, will do.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

[PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

[Sai Prakash Ranjan]

Add coresight components found on Qualcomm SC7180 SoC.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 +++++++++++++++++++++++++++
 1 file changed, 507 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 998f101ad623..d8fe960d6ace 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -1294,6 +1294,513 @@
 			};
 		};
 
+		stm@6002000 {
+			compatible = "arm,coresight-stm", "arm,primecell";
+			reg = <0 0x06002000 0 0x1000>,
+			      <0 0x16280000 0 0x180000>;
+			reg-names = "stm-base", "stm-stimulus-base";
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					stm_out: endpoint {
+						remote-endpoint =
+						  <&funnel0_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@6041000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06041000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					funnel0_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in0>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+					funnel0_in7: endpoint {
+						remote-endpoint =
+						  <&stm_out>;
+					};
+				};
+			};
+		};
+
+		funnel@6042000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06042000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					funnel1_out: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_in1>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@4 {
+					reg = <4>;
+					funnel1_in4: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_out>;
+					};
+				};
+			};
+		};
+
+		funnel@6045000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06045000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					merge_funnel_out: endpoint {
+						remote-endpoint =
+						  <&swao_funnel_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					merge_funnel_in0: endpoint {
+						remote-endpoint =
+						  <&funnel0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					merge_funnel_in1: endpoint {
+						remote-endpoint =
+						  <&funnel1_out>;
+					};
+				};
+			};
+		};
+
+		replicator@6046000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0 0x06046000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					replicator_out: endpoint {
+						remote-endpoint =
+						  <&etr_in>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					replicator_in: endpoint {
+						remote-endpoint =
+						  <&swao_replicator_out>;
+					};
+				};
+			};
+		};
+
+		etr@6048000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0 0x06048000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+			arm,scatter-gather;
+
+			in-ports {
+				port {
+					etr_in: endpoint {
+						remote-endpoint =
+						  <&replicator_out>;
+					};
+				};
+			};
+		};
+
+		funnel@6b04000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x06b04000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					swao_funnel_out: endpoint {
+						remote-endpoint =
+						  <&etf_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@7 {
+					reg = <7>;
+					swao_funnel_in: endpoint {
+						remote-endpoint =
+						  <&merge_funnel_out>;
+					};
+				};
+			};
+		};
+
+		etf@6b05000 {
+			compatible = "arm,coresight-tmc", "arm,primecell";
+			reg = <0 0x06b05000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etf_out: endpoint {
+						remote-endpoint =
+						  <&swao_replicator_in>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					etf_in: endpoint {
+						remote-endpoint =
+						  <&swao_funnel_out>;
+					};
+				};
+			};
+		};
+
+		replicator@6b06000 {
+			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+			reg = <0 0x06b06000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					swao_replicator_out: endpoint {
+						remote-endpoint =
+						  <&replicator_in>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					swao_replicator_in: endpoint {
+						remote-endpoint =
+						  <&etf_out>;
+					};
+				};
+			};
+		};
+
+		etm@7040000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07040000 0 0x1000>;
+
+			cpu = <&CPU0>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm0_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in0>;
+					};
+				};
+			};
+		};
+
+		etm@7140000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07140000 0 0x1000>;
+
+			cpu = <&CPU1>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm1_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in1>;
+					};
+				};
+			};
+		};
+
+		etm@7240000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07240000 0 0x1000>;
+
+			cpu = <&CPU2>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm2_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in2>;
+					};
+				};
+			};
+		};
+
+		etm@7340000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07340000 0 0x1000>;
+
+			cpu = <&CPU3>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm3_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in3>;
+					};
+				};
+			};
+		};
+
+		etm@7440000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07440000 0 0x1000>;
+
+			cpu = <&CPU4>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm4_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in4>;
+					};
+				};
+			};
+		};
+
+		etm@7540000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07540000 0 0x1000>;
+
+			cpu = <&CPU5>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm5_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in5>;
+					};
+				};
+			};
+		};
+
+		etm@7640000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07640000 0 0x1000>;
+
+			cpu = <&CPU6>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm6_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in6>;
+					};
+				};
+			};
+		};
+
+		etm@7740000 {
+			compatible = "arm,coresight-etm4x", "arm,primecell";
+			reg = <0 0x07740000 0 0x1000>;
+
+			cpu = <&CPU7>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					etm7_out: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_in7>;
+					};
+				};
+			};
+		};
+
+		funnel@7800000 { /* APSS Funnel */
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x07800000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					apss_funnel_out: endpoint {
+						remote-endpoint =
+						  <&apss_merge_funnel_in>;
+					};
+				};
+			};
+
+			in-ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					apss_funnel_in0: endpoint {
+						remote-endpoint =
+						  <&etm0_out>;
+					};
+				};
+
+				port@1 {
+					reg = <1>;
+					apss_funnel_in1: endpoint {
+						remote-endpoint =
+						  <&etm1_out>;
+					};
+				};
+
+				port@2 {
+					reg = <2>;
+					apss_funnel_in2: endpoint {
+						remote-endpoint =
+						  <&etm2_out>;
+					};
+				};
+
+				port@3 {
+					reg = <3>;
+					apss_funnel_in3: endpoint {
+						remote-endpoint =
+						  <&etm3_out>;
+					};
+				};
+
+				port@4 {
+					reg = <4>;
+					apss_funnel_in4: endpoint {
+						remote-endpoint =
+						  <&etm4_out>;
+					};
+				};
+
+				port@5 {
+					reg = <5>;
+					apss_funnel_in5: endpoint {
+						remote-endpoint =
+						  <&etm5_out>;
+					};
+				};
+
+				port@6 {
+					reg = <6>;
+					apss_funnel_in6: endpoint {
+						remote-endpoint =
+						  <&etm6_out>;
+					};
+				};
+
+				port@7 {
+					reg = <7>;
+					apss_funnel_in7: endpoint {
+						remote-endpoint =
+						  <&etm7_out>;
+					};
+				};
+			};
+		};
+
+		funnel@7810000 {
+			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+			reg = <0 0x07810000 0 0x1000>;
+
+			clocks = <&aoss_qmp>;
+			clock-names = "apb_pclk";
+
+			out-ports {
+				port {
+					apss_merge_funnel_out: endpoint {
+						remote-endpoint =
+						  <&funnel1_in4>;
+					};
+				};
+			};
+
+			in-ports {
+				port {
+					apss_merge_funnel_in: endpoint {
+						remote-endpoint =
+						  <&apss_funnel_out>;
+					};
+				};
+			};
+		};
+
 		sdhc_2: sdhci@8804000 {
 			compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 			reg = <0 0x08804000 0 0x1000>;
-- 
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Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2020-03-20 00:44:29)
> Add coresight components found on Qualcomm SC7180 SoC.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Tested-by: Stephen Boyd <swboyd@chromium.org>

One nit below.

>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 +++++++++++++++++++++++++++
>  1 file changed, 507 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 998f101ad623..d8fe960d6ace 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1294,6 +1294,513 @@
>                         };
>                 };
>  
> +               stm@6002000 {
> +                       compatible = "arm,coresight-stm", "arm,primecell";
> +                       reg = <0 0x06002000 0 0x1000>,
> +                             <0 0x16280000 0 0x180000>;
> +                       reg-names = "stm-base", "stm-stimulus-base";
> +
> +                       clocks = <&aoss_qmp>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       stm_out: endpoint {
> +                                               remote-endpoint =
> +                                                 <&funnel0_in7>;

Given that this is DT I'd say we just put this remote-endpoint all on
one line. Makes it more readable and I don't think we really care about
the line length in these cases. We're nested pretty deep because it's a
graph binding.

> +                                       };
> +                               };
> +                       };
> +               };
> +

Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

[Sai Prakash Ranjan]

On 2020-03-22 03:40, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2020-03-20 00:44:29)
>> Add coresight components found on Qualcomm SC7180 SoC.
>> 
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> ---
> 
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> Tested-by: Stephen Boyd <swboyd@chromium.org>
> 
> One nit below.
> 
>>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 
>> +++++++++++++++++++++++++++
>>  1 file changed, 507 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index 998f101ad623..d8fe960d6ace 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -1294,6 +1294,513 @@
>>                         };
>>                 };
>> 
>> +               stm@6002000 {
>> +                       compatible = "arm,coresight-stm", 
>> "arm,primecell";
>> +                       reg = <0 0x06002000 0 0x1000>,
>> +                             <0 0x16280000 0 0x180000>;
>> +                       reg-names = "stm-base", "stm-stimulus-base";
>> +
>> +                       clocks = <&aoss_qmp>;
>> +                       clock-names = "apb_pclk";
>> +
>> +                       out-ports {
>> +                               port {
>> +                                       stm_out: endpoint {
>> +                                               remote-endpoint =
>> +                                                 <&funnel0_in7>;
> 
> Given that this is DT I'd say we just put this remote-endpoint all on
> one line. Makes it more readable and I don't think we really care about
> the line length in these cases. We're nested pretty deep because it's a
> graph binding.
> 

Thanks for the review and test, I will make this change.

-Sai

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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a 
member
of Code Aurora Forum, hosted by The Linux Foundation

Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

[Stephen Boyd]

Quoting Sai Prakash Ranjan (2020-03-20 00:44:29)
> Add coresight components found on Qualcomm SC7180 SoC.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 +++++++++++++++++++++++++++
>  1 file changed, 507 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 998f101ad623..d8fe960d6ace 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -1294,6 +1294,513 @@
>                         };
>                 };
>  
> +               stm@6002000 {
> +                       compatible = "arm,coresight-stm", "arm,primecell";

Does this SoC have a cpu-debug coresight component? Specifically
wondering if there's an 'arm,coresight-cpu-debug' compatible node that
can be added to this dtsi file.

Re: [PATCH 2/2] arm64: dts: qcom: sc7180: Add Coresight support

[Sai Prakash Ranjan]

On 2020-04-09 12:49, Stephen Boyd wrote:
> Quoting Sai Prakash Ranjan (2020-03-20 00:44:29)
>> Add coresight components found on Qualcomm SC7180 SoC.
>> 
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> ---
>>  arch/arm64/boot/dts/qcom/sc7180.dtsi | 507 
>> +++++++++++++++++++++++++++
>>  1 file changed, 507 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> index 998f101ad623..d8fe960d6ace 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
>> @@ -1294,6 +1294,513 @@
>>                         };
>>                 };
>> 
>> +               stm@6002000 {
>> +                       compatible = "arm,coresight-stm", 
>> "arm,primecell";
> 
> Does this SoC have a cpu-debug coresight component? Specifically
> wondering if there's an 'arm,coresight-cpu-debug' compatible node that
> can be added to this dtsi file.

There is no coresight cpu-debug component on SC7180 and SDM845.

  -Sai

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member
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