* [PATCH v2 0/3] Update gpios, nvme i2c busses and uefi partition
@ 2021-10-19 6:01 Quan Nguyen
2021-10-19 6:01 ` [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios Quan Nguyen
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Quan Nguyen @ 2021-10-19 6:01 UTC (permalink / raw)
To: Rob Herring, Joel Stanley, Andrew Jeffery, devicetree,
linux-arm-kernel, linux-aspeed, linux-kernel, OpenBMC Maillist
Cc: Open Source Submission, Thang Q . Nguyen, Phong Vo
This patchset adds gpios, i2c configuration busses for NVMe
slots and uefi spi nor partition for BMC on Mt.Jade hardware
reference platform.
v2:
+ Added changes for NVMe slot i2c busses and uefi partition [Quan]
v1:
+ Add some gpios [Quan]
https://lore.kernel.org/r/all/20210917082945.19111-1-quan@os.amperecomputing.com
Quan Nguyen (3):
ARM: dts: aspeed: mtjade: Add some gpios
ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices
ARM: dts: aspeed: mtjade: Add uefi partition
.../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 288 +++++++++++++++++-
1 file changed, 287 insertions(+), 1 deletion(-)
--
2.28.0
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios 2021-10-19 6:01 [PATCH v2 0/3] Update gpios, nvme i2c busses and uefi partition Quan Nguyen @ 2021-10-19 6:01 ` Quan Nguyen 2021-10-19 6:46 ` Joel Stanley 2021-10-19 6:01 ` [PATCH v2 2/3] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices Quan Nguyen 2021-10-19 6:01 ` [PATCH v2 3/3] ARM: dts: aspeed: mtjade: Add uefi partition Quan Nguyen 2 siblings, 1 reply; 11+ messages in thread From: Quan Nguyen @ 2021-10-19 6:01 UTC (permalink / raw) To: Rob Herring, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, OpenBMC Maillist Cc: Open Source Submission, Thang Q . Nguyen, Phong Vo Add S0_SCP_AUTH_FAIL, S1_SCP_AUTH_FAIL gpios to indicates firmware authentication fail on each socket. Add gpio RTC_BAT_SEN_EN to enable RTC battery adc sensor. Add BMC_I2C4_O_EN gpio to go high at boot to enable access to I2C4 bus. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Signed-off-by: Thang Nguyen <thang@os.amperecomputing.com> --- v2: - None .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 21 ++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 57b0c45a2298..3515d55bd312 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -86,6 +86,18 @@ S0_cpu_fault { linux,code = <ASPEED_GPIO(J, 1)>; }; + S0_scp_auth_fail { + label = "S0_SCP_AUTH_FAIL"; + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(J, 2)>; + }; + + S1_scp_auth_fail { + label = "S1_SCP_AUTH_FAIL"; + gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>; + linux,code = <ASPEED_GPIO(Z, 5)>; + }; + S1_overtemp { label = "S1_OVERTEMP"; gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; @@ -590,7 +602,7 @@ &gpio { /*Q0-Q7*/ "","","","","","UID_BUTTON","","", /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", "OCP_MAIN_PWREN","RESET_BUTTON","","", - /*S0-S7*/ "","","","","","","","", + /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","", /*T0-T7*/ "","","","","","","","", /*U0-U7*/ "","","","","","","","", /*V0-V7*/ "","","","","","","","", @@ -604,4 +616,11 @@ &gpio { "S1_BMC_DDR_ADR","","","","", /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", "BMC_OCP_PG"; + + i2c4_o_en { + gpio-hog; + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; + output-high; + line-name = "BMC_I2C4_O_EN"; + }; }; -- 2.28.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios 2021-10-19 6:01 ` [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios Quan Nguyen @ 2021-10-19 6:46 ` Joel Stanley 2021-10-19 10:37 ` Thang Nguyen 2021-10-25 4:44 ` Quan Nguyen 0 siblings, 2 replies; 11+ messages in thread From: Joel Stanley @ 2021-10-19 6:46 UTC (permalink / raw) To: Quan Nguyen Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist, Thang Q . Nguyen, Linux Kernel Mailing List, Phong Vo, Rob Herring, Open Source Submission, Linux ARM On Tue, 19 Oct 2021 at 06:02, Quan Nguyen <quan@os.amperecomputing.com> wrote: > > Add S0_SCP_AUTH_FAIL, S1_SCP_AUTH_FAIL gpios to indicates firmware > authentication fail on each socket. These use the gpio-keys API to expose the GPIOs. I think OpenBMC is moving away from this abstraction, and instead reading the GPIOs with the gpio chardev interface. > > Add gpio RTC_BAT_SEN_EN to enable RTC battery adc sensor. > > Add BMC_I2C4_O_EN gpio to go high at boot to enable access to I2C4 bus. OpenBMC has started a process to document GPIOs that are exposed to userspace, initially so a common userspace can be used across machines. I like doing it for the additional reason that it provides consistency in the naming. https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md If you could take a look at that document and add your GPIOs where possible, and then update the device tree. > > Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> > Signed-off-by: Thang Nguyen <thang@os.amperecomputing.com> > --- > v2: > - None > > .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 21 ++++++++++++++++++- > 1 file changed, 20 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > index 57b0c45a2298..3515d55bd312 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > @@ -86,6 +86,18 @@ S0_cpu_fault { > linux,code = <ASPEED_GPIO(J, 1)>; > }; > > + S0_scp_auth_fail { > + label = "S0_SCP_AUTH_FAIL"; > + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; > + linux,code = <ASPEED_GPIO(J, 2)>; > + }; > + > + S1_scp_auth_fail { > + label = "S1_SCP_AUTH_FAIL"; > + gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>; > + linux,code = <ASPEED_GPIO(Z, 5)>; > + }; > + > S1_overtemp { > label = "S1_OVERTEMP"; > gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; > @@ -590,7 +602,7 @@ &gpio { > /*Q0-Q7*/ "","","","","","UID_BUTTON","","", > /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", > "OCP_MAIN_PWREN","RESET_BUTTON","","", > - /*S0-S7*/ "","","","","","","","", > + /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","", I suggest you create a proposal to call this one battery-voltage-read-enable. I know that some of the IBM machines intend to have this same GPIO. > /*T0-T7*/ "","","","","","","","", > /*U0-U7*/ "","","","","","","","", > /*V0-V7*/ "","","","","","","","", > @@ -604,4 +616,11 @@ &gpio { > "S1_BMC_DDR_ADR","","","","", > /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", > "BMC_OCP_PG"; > + > + i2c4_o_en { > + gpio-hog; > + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; > + output-high; > + line-name = "BMC_I2C4_O_EN"; > + }; > }; > -- > 2.28.0 > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios 2021-10-19 6:46 ` Joel Stanley @ 2021-10-19 10:37 ` Thang Nguyen 2021-10-25 4:44 ` Quan Nguyen 1 sibling, 0 replies; 11+ messages in thread From: Thang Nguyen @ 2021-10-19 10:37 UTC (permalink / raw) To: Joel Stanley, Quan Nguyen Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist, Thang Q . Nguyen, Linux Kernel Mailing List, Phong Vo, Rob Herring, Open Source Submission, Linux ARM On 19/10/2021 13:46, Joel Stanley wrote: > On Tue, 19 Oct 2021 at 06:02, Quan Nguyen <quan@os.amperecomputing.com> wrote: >> >> Add S0_SCP_AUTH_FAIL, S1_SCP_AUTH_FAIL gpios to indicates firmware >> authentication fail on each socket. > > These use the gpio-keys API to expose the GPIOs. I think OpenBMC is > moving away from this abstraction, and instead reading the GPIOs with > the gpio chardev interface. Can you give an example of the suggested change? > >> >> Add gpio RTC_BAT_SEN_EN to enable RTC battery adc sensor. >> >> Add BMC_I2C4_O_EN gpio to go high at boot to enable access to I2C4 bus. > > OpenBMC has started a process to document GPIOs that are exposed to > userspace, initially so a common userspace can be used across > machines. I like doing it for the additional reason that it provides > consistency in the naming. [Thang] The BMC_I2C4_O_EN GPIO is used in kernel only which enabling access to all I2C devices in I2C4 bus, like FRU EEPROM. As it is used as gpio-hog, no userspace access is allowed/intended. It can't be configured in userspace as FRU EEPROM is probed only in kernel boot. > > https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md > > If you could take a look at that document and add your GPIOs where > possible, and then update the device tree. [Thang] I am aware of this GPIO naming convention document. But I think it is to define common name for special GPIOs that applications can use. >> >> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> >> Signed-off-by: Thang Nguyen <thang@os.amperecomputing.com> >> --- >> v2: >> - None >> >> .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 21 ++++++++++++++++++- >> 1 file changed, 20 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >> index 57b0c45a2298..3515d55bd312 100644 >> --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >> +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >> @@ -86,6 +86,18 @@ S0_cpu_fault { >> linux,code = <ASPEED_GPIO(J, 1)>; >> }; >> >> + S0_scp_auth_fail { >> + label = "S0_SCP_AUTH_FAIL"; >> + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; >> + linux,code = <ASPEED_GPIO(J, 2)>; >> + }; >> + >> + S1_scp_auth_fail { >> + label = "S1_SCP_AUTH_FAIL"; >> + gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>; >> + linux,code = <ASPEED_GPIO(Z, 5)>; >> + }; >> + >> S1_overtemp { >> label = "S1_OVERTEMP"; >> gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; >> @@ -590,7 +602,7 @@ &gpio { >> /*Q0-Q7*/ "","","","","","UID_BUTTON","","", >> /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", >> "OCP_MAIN_PWREN","RESET_BUTTON","","", >> - /*S0-S7*/ "","","","","","","","", >> + /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","", > > I suggest you create a proposal to call this one > battery-voltage-read-enable. I know that some of the IBM machines > intend to have this same GPIO. [Thang] is there any application to use this pin name? > >> /*T0-T7*/ "","","","","","","","", >> /*U0-U7*/ "","","","","","","","", >> /*V0-V7*/ "","","","","","","","", >> @@ -604,4 +616,11 @@ &gpio { >> "S1_BMC_DDR_ADR","","","","", >> /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", >> "BMC_OCP_PG"; >> + >> + i2c4_o_en { >> + gpio-hog; >> + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; >> + output-high; >> + line-name = "BMC_I2C4_O_EN"; >> + }; >> }; >> -- >> 2.28.0 >> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios 2021-10-19 6:46 ` Joel Stanley 2021-10-19 10:37 ` Thang Nguyen @ 2021-10-25 4:44 ` Quan Nguyen 2021-11-01 9:25 ` Quan Nguyen 1 sibling, 1 reply; 11+ messages in thread From: Quan Nguyen @ 2021-10-25 4:44 UTC (permalink / raw) To: Joel Stanley Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist, Thang Q . Nguyen, Linux Kernel Mailing List, Phong Vo, Rob Herring, Open Source Submission, Linux ARM On 19/10/2021 13:46, Joel Stanley wrote: > On Tue, 19 Oct 2021 at 06:02, Quan Nguyen <quan@os.amperecomputing.com> wrote: >> >> Add S0_SCP_AUTH_FAIL, S1_SCP_AUTH_FAIL gpios to indicates firmware >> authentication fail on each socket. > > These use the gpio-keys API to expose the GPIOs. I think OpenBMC is > moving away from this abstraction, and instead reading the GPIOs with > the gpio chardev interface. > Thanks Joel for the review, Yes, will switch to use gpio chardev interface and will remove these gpio-keys defined in next version >> >> Add gpio RTC_BAT_SEN_EN to enable RTC battery adc sensor. >> >> Add BMC_I2C4_O_EN gpio to go high at boot to enable access to I2C4 bus. > > OpenBMC has started a process to document GPIOs that are exposed to > userspace, initially so a common userspace can be used across > machines. I like doing it for the additional reason that it provides > consistency in the naming. > > https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md > > If you could take a look at that document and add your GPIOs where > possible, and then update the device tree. > There is on-going discussion about naming of the RTC voltage sensing enable gpio pin in [1], So I'd like to address this change later in separate patch when this is settled. Hence, I will remove this changes in next version. [1] https://gerrit.openbmc-project.xyz/c/openbmc/docs/+/48018 About the BMC_I2C4_O_EN, this is needed as gpio-hog to make the i2c bus accessible at boot time so I will keep this in next version. In fact, I'm still a bit of confuse if this pin needs a common name as it is just to enable the bus access and does not serve for any particular common purpose. Thanks, - Quan >> >> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> >> Signed-off-by: Thang Nguyen <thang@os.amperecomputing.com> >> --- >> v2: >> - None >> >> .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 21 ++++++++++++++++++- >> 1 file changed, 20 insertions(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >> index 57b0c45a2298..3515d55bd312 100644 >> --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >> +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >> @@ -86,6 +86,18 @@ S0_cpu_fault { >> linux,code = <ASPEED_GPIO(J, 1)>; >> }; >> >> + S0_scp_auth_fail { >> + label = "S0_SCP_AUTH_FAIL"; >> + gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>; >> + linux,code = <ASPEED_GPIO(J, 2)>; >> + }; >> + >> + S1_scp_auth_fail { >> + label = "S1_SCP_AUTH_FAIL"; >> + gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>; >> + linux,code = <ASPEED_GPIO(Z, 5)>; >> + }; >> + >> S1_overtemp { >> label = "S1_OVERTEMP"; >> gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>; >> @@ -590,7 +602,7 @@ &gpio { >> /*Q0-Q7*/ "","","","","","UID_BUTTON","","", >> /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", >> "OCP_MAIN_PWREN","RESET_BUTTON","","", >> - /*S0-S7*/ "","","","","","","","", >> + /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","", > > I suggest you create a proposal to call this one > battery-voltage-read-enable. I know that some of the IBM machines > intend to have this same GPIO. > >> /*T0-T7*/ "","","","","","","","", >> /*U0-U7*/ "","","","","","","","", >> /*V0-V7*/ "","","","","","","","", >> @@ -604,4 +616,11 @@ &gpio { >> "S1_BMC_DDR_ADR","","","","", >> /*AC0-AC7*/ "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", >> "BMC_OCP_PG"; >> + >> + i2c4_o_en { >> + gpio-hog; >> + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; >> + output-high; >> + line-name = "BMC_I2C4_O_EN"; >> + }; >> }; >> -- >> 2.28.0 >> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios 2021-10-25 4:44 ` Quan Nguyen @ 2021-11-01 9:25 ` Quan Nguyen 2021-11-16 5:24 ` Joel Stanley 0 siblings, 1 reply; 11+ messages in thread From: Quan Nguyen @ 2021-11-01 9:25 UTC (permalink / raw) To: Joel Stanley Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist, Thang Q . Nguyen, Linux Kernel Mailing List, Phong Vo, Rob Herring, Open Source Submission, Linux ARM Dear Joel, I found this patch appears in linux-next tree as in [1], can we expect the remain two patches in this patchset ([2] and [3]) will be merged soon? [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20211029&id=0b32c1b4071c482f2cf98b717cfc7380423ec619 [2] https://www.spinics.net/lists/kernel/msg4115571.html [3] https://www.spinics.net/lists/kernel/msg4115572.html Thanks, - Quan On 25/10/2021 11:44, Quan Nguyen wrote: > On 19/10/2021 13:46, Joel Stanley wrote: >> On Tue, 19 Oct 2021 at 06:02, Quan Nguyen >> <quan@os.amperecomputing.com> wrote: >>> >>> Add S0_SCP_AUTH_FAIL, S1_SCP_AUTH_FAIL gpios to indicates firmware >>> authentication fail on each socket. >> >> These use the gpio-keys API to expose the GPIOs. I think OpenBMC is >> moving away from this abstraction, and instead reading the GPIOs with >> the gpio chardev interface. >> > Thanks Joel for the review, > Yes, will switch to use gpio chardev interface and will remove these > gpio-keys defined in next version > >>> >>> Add gpio RTC_BAT_SEN_EN to enable RTC battery adc sensor. >>> >>> Add BMC_I2C4_O_EN gpio to go high at boot to enable access to I2C4 bus. >> >> OpenBMC has started a process to document GPIOs that are exposed to >> userspace, initially so a common userspace can be used across >> machines. I like doing it for the additional reason that it provides >> consistency in the naming. >> >> https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md >> >> >> If you could take a look at that document and add your GPIOs where >> possible, and then update the device tree. >> > > There is on-going discussion about naming of the RTC voltage sensing > enable gpio pin in [1], So I'd like to address this change later in > separate patch when this is settled. Hence, I will remove this changes > in next version. > > [1] https://gerrit.openbmc-project.xyz/c/openbmc/docs/+/48018 > > About the BMC_I2C4_O_EN, this is needed as gpio-hog to make the i2c bus > accessible at boot time so I will keep this in next version. > In fact, I'm still a bit of confuse if this pin needs a common name as > it is just to enable the bus access and does not serve for any > particular common purpose. > > Thanks, > - Quan > >>> >>> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> >>> Signed-off-by: Thang Nguyen <thang@os.amperecomputing.com> >>> --- >>> v2: >>> - None >>> >>> .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 21 ++++++++++++++++++- >>> 1 file changed, 20 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >>> b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >>> index 57b0c45a2298..3515d55bd312 100644 >>> --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >>> +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts >>> @@ -86,6 +86,18 @@ S0_cpu_fault { >>> linux,code = <ASPEED_GPIO(J, 1)>; >>> }; >>> >>> + S0_scp_auth_fail { >>> + label = "S0_SCP_AUTH_FAIL"; >>> + gpios = <&gpio ASPEED_GPIO(J, 2) >>> GPIO_ACTIVE_LOW>; >>> + linux,code = <ASPEED_GPIO(J, 2)>; >>> + }; >>> + >>> + S1_scp_auth_fail { >>> + label = "S1_SCP_AUTH_FAIL"; >>> + gpios = <&gpio ASPEED_GPIO(Z, 5) >>> GPIO_ACTIVE_LOW>; >>> + linux,code = <ASPEED_GPIO(Z, 5)>; >>> + }; >>> + >>> S1_overtemp { >>> label = "S1_OVERTEMP"; >>> gpios = <&gpio ASPEED_GPIO(Z, 6) >>> GPIO_ACTIVE_LOW>; >>> @@ -590,7 +602,7 @@ &gpio { >>> /*Q0-Q7*/ "","","","","","UID_BUTTON","","", >>> /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", >>> "OCP_MAIN_PWREN","RESET_BUTTON","","", >>> - /*S0-S7*/ "","","","","","","","", >>> + /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","", >> >> I suggest you create a proposal to call this one >> battery-voltage-read-enable. I know that some of the IBM machines >> intend to have this same GPIO. >> >>> /*T0-T7*/ "","","","","","","","", >>> /*U0-U7*/ "","","","","","","","", >>> /*V0-V7*/ "","","","","","","","", >>> @@ -604,4 +616,11 @@ &gpio { >>> "S1_BMC_DDR_ADR","","","","", >>> /*AC0-AC7*/ >>> "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", >>> "BMC_OCP_PG"; >>> + >>> + i2c4_o_en { >>> + gpio-hog; >>> + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; >>> + output-high; >>> + line-name = "BMC_I2C4_O_EN"; >>> + }; >>> }; >>> -- >>> 2.28.0 >>> > ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios 2021-11-01 9:25 ` Quan Nguyen @ 2021-11-16 5:24 ` Joel Stanley 0 siblings, 0 replies; 11+ messages in thread From: Joel Stanley @ 2021-11-16 5:24 UTC (permalink / raw) To: Quan Nguyen Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist, Thang Q . Nguyen, Linux Kernel Mailing List, Phong Vo, Rob Herring, Open Source Submission, Linux ARM On Mon, 1 Nov 2021 at 09:32, Quan Nguyen <quan@os.amperecomputing.com> wrote: > > Dear Joel, > > I found this patch appears in linux-next tree as in [1], can we expect > the remain two patches in this patchset ([2] and [3]) will be merged soon? I am not sure why I merged the first patch but not the next two. I think this was a mistake. They are queued for merging in v5.17. > > [1] > https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20211029&id=0b32c1b4071c482f2cf98b717cfc7380423ec619 > > [2] https://www.spinics.net/lists/kernel/msg4115571.html > [3] https://www.spinics.net/lists/kernel/msg4115572.html > > Thanks, > - Quan > > On 25/10/2021 11:44, Quan Nguyen wrote: > > On 19/10/2021 13:46, Joel Stanley wrote: > >> On Tue, 19 Oct 2021 at 06:02, Quan Nguyen > >> <quan@os.amperecomputing.com> wrote: > >>> > >>> Add S0_SCP_AUTH_FAIL, S1_SCP_AUTH_FAIL gpios to indicates firmware > >>> authentication fail on each socket. > >> > >> These use the gpio-keys API to expose the GPIOs. I think OpenBMC is > >> moving away from this abstraction, and instead reading the GPIOs with > >> the gpio chardev interface. > >> > > Thanks Joel for the review, > > Yes, will switch to use gpio chardev interface and will remove these > > gpio-keys defined in next version > > > >>> > >>> Add gpio RTC_BAT_SEN_EN to enable RTC battery adc sensor. > >>> > >>> Add BMC_I2C4_O_EN gpio to go high at boot to enable access to I2C4 bus. > >> > >> OpenBMC has started a process to document GPIOs that are exposed to > >> userspace, initially so a common userspace can be used across > >> machines. I like doing it for the additional reason that it provides > >> consistency in the naming. > >> > >> https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-naming.md > >> > >> > >> If you could take a look at that document and add your GPIOs where > >> possible, and then update the device tree. > >> > > > > There is on-going discussion about naming of the RTC voltage sensing > > enable gpio pin in [1], So I'd like to address this change later in > > separate patch when this is settled. Hence, I will remove this changes > > in next version. > > > > [1] https://gerrit.openbmc-project.xyz/c/openbmc/docs/+/48018 > > > > About the BMC_I2C4_O_EN, this is needed as gpio-hog to make the i2c bus > > accessible at boot time so I will keep this in next version. > > In fact, I'm still a bit of confuse if this pin needs a common name as > > it is just to enable the bus access and does not serve for any > > particular common purpose. > > > > Thanks, > > - Quan > > > >>> > >>> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> > >>> Signed-off-by: Thang Nguyen <thang@os.amperecomputing.com> > >>> --- > >>> v2: > >>> - None > >>> > >>> .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 21 ++++++++++++++++++- > >>> 1 file changed, 20 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > >>> b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > >>> index 57b0c45a2298..3515d55bd312 100644 > >>> --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > >>> +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > >>> @@ -86,6 +86,18 @@ S0_cpu_fault { > >>> linux,code = <ASPEED_GPIO(J, 1)>; > >>> }; > >>> > >>> + S0_scp_auth_fail { > >>> + label = "S0_SCP_AUTH_FAIL"; > >>> + gpios = <&gpio ASPEED_GPIO(J, 2) > >>> GPIO_ACTIVE_LOW>; > >>> + linux,code = <ASPEED_GPIO(J, 2)>; > >>> + }; > >>> + > >>> + S1_scp_auth_fail { > >>> + label = "S1_SCP_AUTH_FAIL"; > >>> + gpios = <&gpio ASPEED_GPIO(Z, 5) > >>> GPIO_ACTIVE_LOW>; > >>> + linux,code = <ASPEED_GPIO(Z, 5)>; > >>> + }; > >>> + > >>> S1_overtemp { > >>> label = "S1_OVERTEMP"; > >>> gpios = <&gpio ASPEED_GPIO(Z, 6) > >>> GPIO_ACTIVE_LOW>; > >>> @@ -590,7 +602,7 @@ &gpio { > >>> /*Q0-Q7*/ "","","","","","UID_BUTTON","","", > >>> /*R0-R7*/ "","","BMC_EXT_HIGHTEMP_L","OCP_AUX_PWREN", > >>> "OCP_MAIN_PWREN","RESET_BUTTON","","", > >>> - /*S0-S7*/ "","","","","","","","", > >>> + /*S0-S7*/ "","","","","RTC_BAT_SEN_EN","","","", > >> > >> I suggest you create a proposal to call this one > >> battery-voltage-read-enable. I know that some of the IBM machines > >> intend to have this same GPIO. > >> > >>> /*T0-T7*/ "","","","","","","","", > >>> /*U0-U7*/ "","","","","","","","", > >>> /*V0-V7*/ "","","","","","","","", > >>> @@ -604,4 +616,11 @@ &gpio { > >>> "S1_BMC_DDR_ADR","","","","", > >>> /*AC0-AC7*/ > >>> "SYS_PWR_GD","","","","","BMC_READY","SLAVE_PRESENT_L", > >>> "BMC_OCP_PG"; > >>> + > >>> + i2c4_o_en { > >>> + gpio-hog; > >>> + gpios = <ASPEED_GPIO(Y, 2) GPIO_ACTIVE_HIGH>; > >>> + output-high; > >>> + line-name = "BMC_I2C4_O_EN"; > >>> + }; > >>> }; > >>> -- > >>> 2.28.0 > >>> > > > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 2/3] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices 2021-10-19 6:01 [PATCH v2 0/3] Update gpios, nvme i2c busses and uefi partition Quan Nguyen 2021-10-19 6:01 ` [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios Quan Nguyen @ 2021-10-19 6:01 ` Quan Nguyen 2021-10-19 6:46 ` Joel Stanley 2021-10-19 6:01 ` [PATCH v2 3/3] ARM: dts: aspeed: mtjade: Add uefi partition Quan Nguyen 2 siblings, 1 reply; 11+ messages in thread From: Quan Nguyen @ 2021-10-19 6:01 UTC (permalink / raw) To: Rob Herring, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, OpenBMC Maillist Cc: Open Source Submission, Thang Q . Nguyen, Phong Vo This commit adds configuration i2c busses for 24 NVMe slots and 2 M2 NVMe slots found on Mt.Jade hardware reference platform with Ampere's Altra processor family. Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> --- v2: + Introduced in v2 .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 258 ++++++++++++++++++ 1 file changed, 258 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 3515d55bd312..723c7063c223 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -7,6 +7,50 @@ / { model = "Ampere Mt. Jade BMC"; compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; + aliases { + /* + * i2c bus 50-57 assigned to NVMe slot 0-7 + */ + i2c50 = &nvmeslot_0; + i2c51 = &nvmeslot_1; + i2c52 = &nvmeslot_2; + i2c53 = &nvmeslot_3; + i2c54 = &nvmeslot_4; + i2c55 = &nvmeslot_5; + i2c56 = &nvmeslot_6; + i2c57 = &nvmeslot_7; + + /* + * i2c bus 60-67 assigned to NVMe slot 8-15 + */ + i2c60 = &nvmeslot_8; + i2c61 = &nvmeslot_9; + i2c62 = &nvmeslot_10; + i2c63 = &nvmeslot_11; + i2c64 = &nvmeslot_12; + i2c65 = &nvmeslot_13; + i2c66 = &nvmeslot_14; + i2c67 = &nvmeslot_15; + + /* + * i2c bus 70-77 assigned to NVMe slot 16-23 + */ + i2c70 = &nvmeslot_16; + i2c71 = &nvmeslot_17; + i2c72 = &nvmeslot_18; + i2c73 = &nvmeslot_19; + i2c74 = &nvmeslot_20; + i2c75 = &nvmeslot_21; + i2c76 = &nvmeslot_22; + i2c77 = &nvmeslot_23; + + /* + * i2c bus 80-81 assigned to NVMe M2 slot 0-1 + */ + i2c80 = &nvme_m2_0; + i2c81 = &nvme_m2_1; + }; + chosen { stdout-path = &uart5; bootargs = "console=ttyS4,115200 earlycon"; @@ -445,6 +489,220 @@ rtc@51 { &i2c5 { status = "okay"; + i2c-mux@70 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + nvmeslot_0_7: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x71>; + i2c-mux-idle-disconnect; + + nvmeslot_8_15: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + + nvmeslot_16_23: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + + }; + + i2c-mux@72 { + compatible = "nxp,pca9545"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x72>; + i2c-mux-idle-disconnect; + + nvme_m2_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + + nvme_m2_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + }; +}; + +&nvmeslot_0_7 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_4: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_5: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_6: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_7: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + + }; +}; + +&nvmeslot_8_15 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_8: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_9: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_10: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_11: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_12: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_13: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_14: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_15: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; +}; + +&nvmeslot_16_23 { + status = "okay"; + + i2c-mux@75 { + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c-mux-idle-disconnect; + + nvmeslot_16: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + }; + nvmeslot_17: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + }; + nvmeslot_18: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + }; + nvmeslot_19: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + }; + nvmeslot_20: i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + }; + nvmeslot_21: i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x5>; + }; + nvmeslot_22: i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + }; + nvmeslot_23: i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + }; + }; }; &i2c6 { -- 2.28.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/3] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices 2021-10-19 6:01 ` [PATCH v2 2/3] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices Quan Nguyen @ 2021-10-19 6:46 ` Joel Stanley 0 siblings, 0 replies; 11+ messages in thread From: Joel Stanley @ 2021-10-19 6:46 UTC (permalink / raw) To: Quan Nguyen Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist, Thang Q . Nguyen, Linux Kernel Mailing List, Phong Vo, Rob Herring, Open Source Submission, Linux ARM On Tue, 19 Oct 2021 at 06:02, Quan Nguyen <quan@os.amperecomputing.com> wrote: > > This commit adds configuration i2c busses for 24 NVMe slots and > 2 M2 NVMe slots found on Mt.Jade hardware reference platform > with Ampere's Altra processor family. > > Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> > --- > v2: > + Introduced in v2 > > .../arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 258 ++++++++++++++++++ > 1 file changed, 258 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > index 3515d55bd312..723c7063c223 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > @@ -7,6 +7,50 @@ / { > model = "Ampere Mt. Jade BMC"; > compatible = "ampere,mtjade-bmc", "aspeed,ast2500"; > > + aliases { > + /* > + * i2c bus 50-57 assigned to NVMe slot 0-7 > + */ > + i2c50 = &nvmeslot_0; > + i2c51 = &nvmeslot_1; > + i2c52 = &nvmeslot_2; > + i2c53 = &nvmeslot_3; > + i2c54 = &nvmeslot_4; > + i2c55 = &nvmeslot_5; > + i2c56 = &nvmeslot_6; > + i2c57 = &nvmeslot_7; > + > + /* > + * i2c bus 60-67 assigned to NVMe slot 8-15 > + */ > + i2c60 = &nvmeslot_8; > + i2c61 = &nvmeslot_9; > + i2c62 = &nvmeslot_10; > + i2c63 = &nvmeslot_11; > + i2c64 = &nvmeslot_12; > + i2c65 = &nvmeslot_13; > + i2c66 = &nvmeslot_14; > + i2c67 = &nvmeslot_15; > + > + /* > + * i2c bus 70-77 assigned to NVMe slot 16-23 > + */ > + i2c70 = &nvmeslot_16; > + i2c71 = &nvmeslot_17; > + i2c72 = &nvmeslot_18; > + i2c73 = &nvmeslot_19; > + i2c74 = &nvmeslot_20; > + i2c75 = &nvmeslot_21; > + i2c76 = &nvmeslot_22; > + i2c77 = &nvmeslot_23; > + > + /* > + * i2c bus 80-81 assigned to NVMe M2 slot 0-1 > + */ > + i2c80 = &nvme_m2_0; > + i2c81 = &nvme_m2_1; > + }; > + > chosen { > stdout-path = &uart5; > bootargs = "console=ttyS4,115200 earlycon"; > @@ -445,6 +489,220 @@ rtc@51 { > > &i2c5 { > status = "okay"; > + i2c-mux@70 { > + compatible = "nxp,pca9548"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x70>; > + i2c-mux-idle-disconnect; > + > + nvmeslot_0_7: i2c@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x3>; > + }; > + }; > + > + i2c-mux@71 { > + compatible = "nxp,pca9548"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x71>; > + i2c-mux-idle-disconnect; > + > + nvmeslot_8_15: i2c@4 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x4>; > + }; > + > + nvmeslot_16_23: i2c@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x3>; > + }; > + > + }; > + > + i2c-mux@72 { > + compatible = "nxp,pca9545"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x72>; > + i2c-mux-idle-disconnect; > + > + nvme_m2_0: i2c@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0>; > + }; > + > + nvme_m2_1: i2c@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x1>; > + }; > + }; > +}; > + > +&nvmeslot_0_7 { > + status = "okay"; > + > + i2c-mux@75 { > + compatible = "nxp,pca9548"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x75>; > + i2c-mux-idle-disconnect; > + > + nvmeslot_0: i2c@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0>; > + }; > + nvmeslot_1: i2c@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x1>; > + }; > + nvmeslot_2: i2c@2 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x2>; > + }; > + nvmeslot_3: i2c@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x3>; > + }; > + nvmeslot_4: i2c@4 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x4>; > + }; > + nvmeslot_5: i2c@5 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x5>; > + }; > + nvmeslot_6: i2c@6 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x6>; > + }; > + nvmeslot_7: i2c@7 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x7>; > + }; > + > + }; > +}; > + > +&nvmeslot_8_15 { > + status = "okay"; > + > + i2c-mux@75 { > + compatible = "nxp,pca9548"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x75>; > + i2c-mux-idle-disconnect; > + > + nvmeslot_8: i2c@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0>; > + }; > + nvmeslot_9: i2c@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x1>; > + }; > + nvmeslot_10: i2c@2 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x2>; > + }; > + nvmeslot_11: i2c@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x3>; > + }; > + nvmeslot_12: i2c@4 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x4>; > + }; > + nvmeslot_13: i2c@5 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x5>; > + }; > + nvmeslot_14: i2c@6 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x6>; > + }; > + nvmeslot_15: i2c@7 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x7>; > + }; > + }; > +}; > + > +&nvmeslot_16_23 { > + status = "okay"; > + > + i2c-mux@75 { > + compatible = "nxp,pca9548"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x75>; > + i2c-mux-idle-disconnect; > + > + nvmeslot_16: i2c@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x0>; > + }; > + nvmeslot_17: i2c@1 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x1>; > + }; > + nvmeslot_18: i2c@2 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x2>; > + }; > + nvmeslot_19: i2c@3 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x3>; > + }; > + nvmeslot_20: i2c@4 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x4>; > + }; > + nvmeslot_21: i2c@5 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x5>; > + }; > + nvmeslot_22: i2c@6 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x6>; > + }; > + nvmeslot_23: i2c@7 { > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0x7>; > + }; > + }; > }; > > &i2c6 { > -- > 2.28.0 > ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 3/3] ARM: dts: aspeed: mtjade: Add uefi partition 2021-10-19 6:01 [PATCH v2 0/3] Update gpios, nvme i2c busses and uefi partition Quan Nguyen 2021-10-19 6:01 ` [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios Quan Nguyen 2021-10-19 6:01 ` [PATCH v2 2/3] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices Quan Nguyen @ 2021-10-19 6:01 ` Quan Nguyen 2021-10-19 6:46 ` Joel Stanley 2 siblings, 1 reply; 11+ messages in thread From: Quan Nguyen @ 2021-10-19 6:01 UTC (permalink / raw) To: Rob Herring, Joel Stanley, Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, OpenBMC Maillist Cc: Open Source Submission, Thang Q . Nguyen, Phong Vo Add SPI NOR partition for uefi. Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> --- v2: + Introdued in v2 arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts index 723c7063c223..4c3c3f1a12ea 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts @@ -374,6 +374,15 @@ flash@0 { m25p,fast-read; label = "pnor"; /* spi-max-frequency = <100000000>; */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + uefi@400000 { + reg = <0x400000 0x1C00000>; + label = "pnor-uefi"; + }; + }; }; }; -- 2.28.0 ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] ARM: dts: aspeed: mtjade: Add uefi partition 2021-10-19 6:01 ` [PATCH v2 3/3] ARM: dts: aspeed: mtjade: Add uefi partition Quan Nguyen @ 2021-10-19 6:46 ` Joel Stanley 0 siblings, 0 replies; 11+ messages in thread From: Joel Stanley @ 2021-10-19 6:46 UTC (permalink / raw) To: Quan Nguyen Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist, Thang Q . Nguyen, Linux Kernel Mailing List, Phong Vo, Rob Herring, Open Source Submission, Linux ARM On Tue, 19 Oct 2021 at 06:02, Quan Nguyen <quan@os.amperecomputing.com> wrote: > > Add SPI NOR partition for uefi. > > Signed-off-by: Thang Q. Nguyen <thang@os.amperecomputing.com> > Signed-off-by: Quan Nguyen <quan@os.amperecomputing.com> Reviewed-by: Joel Stanley <joel@jms.id.au> > --- > v2: > + Introdued in v2 > > arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > index 723c7063c223..4c3c3f1a12ea 100644 > --- a/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > +++ b/arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts > @@ -374,6 +374,15 @@ flash@0 { > m25p,fast-read; > label = "pnor"; > /* spi-max-frequency = <100000000>; */ > + partitions { > + compatible = "fixed-partitions"; > + #address-cells = <1>; > + #size-cells = <1>; > + uefi@400000 { > + reg = <0x400000 0x1C00000>; > + label = "pnor-uefi"; > + }; > + }; > }; > }; > > -- > 2.28.0 > ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-11-16 5:26 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-19 6:01 [PATCH v2 0/3] Update gpios, nvme i2c busses and uefi partition Quan Nguyen 2021-10-19 6:01 ` [PATCH v2 1/3] ARM: dts: aspeed: mtjade: Add some gpios Quan Nguyen 2021-10-19 6:46 ` Joel Stanley 2021-10-19 10:37 ` Thang Nguyen 2021-10-25 4:44 ` Quan Nguyen 2021-11-01 9:25 ` Quan Nguyen 2021-11-16 5:24 ` Joel Stanley 2021-10-19 6:01 ` [PATCH v2 2/3] ARM: dts: aspeed: mtjade: Add I2C buses for NVMe devices Quan Nguyen 2021-10-19 6:46 ` Joel Stanley 2021-10-19 6:01 ` [PATCH v2 3/3] ARM: dts: aspeed: mtjade: Add uefi partition Quan Nguyen 2021-10-19 6:46 ` Joel Stanley
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