From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Subject: [Qemu-devel] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property
Date: Sun, 18 Aug 2019 22:11:34 -0700 [thread overview]
Message-ID: <1566191521-7820-2-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1566191521-7820-1-git-send-email-bmeng.cn@gmail.com>
"linux,phandle" property is optional. Remove all instances in the
sifive_u, virt and spike machine device trees.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
Changes in v4:
- remove 2 more "linux,phandle" instances in sifive_u.c and spike.c
after rebasing on Palmer's QEMU RISC-V tree
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_u.c | 4 ----
hw/riscv/spike.c | 1 -
hw/riscv/virt.c | 3 ---
3 files changed, 8 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 64e233d..afe304f 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -126,7 +126,6 @@ static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
qemu_fdt_add_subnode(fdt, intc);
qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
- qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
@@ -185,7 +184,6 @@ static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
- qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(cells);
g_free(nodename);
@@ -198,7 +196,6 @@ static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
SIFIVE_U_GEM_CLOCK_FREQ);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
- qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle);
ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(nodename);
@@ -234,7 +231,6 @@ static void *create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle);
- qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", uartclk_phandle);
uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(nodename);
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 2991b34..14acaef 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -112,7 +112,6 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
qemu_fdt_add_subnode(fdt, intc);
qemu_fdt_setprop_cell(fdt, intc, "phandle", 1);
- qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1);
qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 25faf3b..00be05a 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -170,11 +170,9 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
- qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
intc_phandle = phandle++;
qemu_fdt_add_subnode(fdt, intc);
qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
- qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
@@ -250,7 +248,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV);
qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle);
- qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
g_free(cells);
g_free(nodename);
--
2.7.4
next prev parent reply other threads:[~2019-08-19 5:14 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-19 5:11 [Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-19 5:11 ` Bin Meng [this message]
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-19 20:08 ` Alistair Francis
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-22 22:40 ` Alistair Francis
2019-08-23 1:57 ` Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-19 20:21 ` Alistair Francis
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-19 20:22 ` Alistair Francis
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-20 18:26 ` Alistair Francis
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 21/28] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 23/28] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-22 22:41 ` Alistair Francis
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-08-19 5:11 ` [Qemu-devel] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-19 5:12 ` [Qemu-devel] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-22 22:39 ` Alistair Francis
2019-08-19 5:12 ` [Qemu-devel] [PATCH v4 28/28] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng
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