QEMU-Devel Archive on lore.kernel.org
 help / color / Atom feed
From: Alistair Francis <alistair23@gmail.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Palmer Dabbelt <palmer@sifive.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array
Date: Thu, 22 Aug 2019 15:40:05 -0700
Message-ID: <CAKmqyKO-FvyWnMimAGNAEwSRqrswkY9QW1=iiaaSZMh6kgXLCg@mail.gmail.com> (raw)
In-Reply-To: <1566191521-7820-14-git-send-email-bmeng.cn@gmail.com>

On Sun, Aug 18, 2019 at 10:27 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> At present each hart's hartid in a RISC-V hart array is assigned
> the same value of its index in the hart array. But for a system
> that has multiple hart arrays, this is not the case any more.
>
> Add a new "hartid-base" property so that hartid number can be
> assigned based on the property value.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Why do we need this patch?

Alistair

>
> ---
>
> Changes in v4:
> - new patch to add a "hartid-base" property to RISC-V hart array
>
> Changes in v3: None
> Changes in v2: None
>
>  hw/riscv/riscv_hart.c         | 8 +++++---
>  include/hw/riscv/riscv_hart.h | 1 +
>  2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index 9deef869..52ab86a 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -27,6 +27,7 @@
>
>  static Property riscv_harts_props[] = {
>      DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
> +    DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
>      DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
>      DEFINE_PROP_END_OF_LIST(),
>  };
> @@ -37,7 +38,7 @@ static void riscv_harts_cpu_reset(void *opaque)
>      cpu_reset(CPU(cpu));
>  }
>
> -static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
> +static void riscv_hart_realize(RISCVHartArrayState *s, int idx, uint32_t hartid,
>                                 char *cpu_type, Error **errp)
>  {
>      Error *err = NULL;
> @@ -45,7 +46,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
>      object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
>                              sizeof(RISCVCPU), cpu_type,
>                              &error_abort, NULL);
> -    s->harts[idx].env.mhartid = idx;
> +    s->harts[idx].env.mhartid = hartid;
>      qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
>      object_property_set_bool(OBJECT(&s->harts[idx]), true,
>                               "realized", &err);
> @@ -58,12 +59,13 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
>  static void riscv_harts_realize(DeviceState *dev, Error **errp)
>  {
>      RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
> +    uint32_t hartid = s->hartid_base;
>      int n;
>
>      s->harts = g_new0(RISCVCPU, s->num_harts);
>
>      for (n = 0; n < s->num_harts; n++) {
> -        riscv_hart_realize(s, n, s->cpu_type, errp);
> +        riscv_hart_realize(s, n, hartid + n, s->cpu_type, errp);
>      }
>  }
>
> diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
> index 0671d88..1984e30 100644
> --- a/include/hw/riscv/riscv_hart.h
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -32,6 +32,7 @@ typedef struct RISCVHartArrayState {
>
>      /*< public >*/
>      uint32_t num_harts;
> +    uint32_t hartid_base;
>      char *cpu_type;
>      RISCVCPU *harts;
>  } RISCVHartArrayState;
> --
> 2.7.4
>
>


  reply index

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-19  5:11 [Qemu-devel] [PATCH v4 00/28] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 01/28] riscv: hw: Remove superfluous "linux, phandle" property Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 02/28] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 03/28] riscv: hw: Remove not needed PLIC properties in device tree Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 04/28] riscv: hw: Change create_fdt() to return void Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 05/28] riscv: roms: Remove executable attribute of opensbi images Bin Meng
2019-08-19 20:08   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 06/28] riscv: sifive_u: Remove the unnecessary include of prci header Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 07/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 08/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 09/28] riscv: sifive_e: prci: Update the PRCI register block size Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 11/28] riscv: Add a sifive_cpu.h to include both E and U cpu type defines Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 12/28] riscv: hart: Extract hart realize to a separate routine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 13/28] riscv: hart: Add a "hartid-base" property to RISC-V hart array Bin Meng
2019-08-22 22:40   ` Alistair Francis [this message]
2019-08-23  1:57     ` Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 14/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 15/28] riscv: sifive_u: Set the minimum number of cpus to 2 Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 16/28] riscv: sifive_u: Update PLIC hart topology configuration string Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 17/28] riscv: sifive: Implement PRCI model for FU540 Bin Meng
2019-08-19 20:21   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 18/28] riscv: sifive_u: Generate hfclk and rtcclk nodes Bin Meng
2019-08-19 20:22   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 19/28] riscv: sifive_u: Add PRCI block to the SoC Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 20/28] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes Bin Meng
2019-08-20 18:26   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 21/28] riscv: sifive_u: Update UART base addresses and IRQs Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 22/28] riscv: sifive_u: Change UART node name in device tree Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 23/28] riscv: roms: Update default bios for sifive_u machine Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 24/28] riscv: sifive: Implement a model for SiFive FU540 OTP Bin Meng
2019-08-22 22:41   ` Alistair Francis
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 25/28] riscv: sifive_u: Instantiate OTP memory with a serial number Bin Meng
2019-08-19  5:11 ` [Qemu-devel] [PATCH v4 26/28] riscv: sifive_u: Fix broken GEM support Bin Meng
2019-08-19  5:12 ` [Qemu-devel] [PATCH v4 27/28] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet Bin Meng
2019-08-22 22:39   ` Alistair Francis
2019-08-19  5:12 ` [Qemu-devel] [PATCH v4 28/28] riscv: sifive_u: Update model and compatible strings in device tree Bin Meng

Reply instructions:

You may reply publically to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to='CAKmqyKO-FvyWnMimAGNAEwSRqrswkY9QW1=iiaaSZMh6kgXLCg@mail.gmail.com' \
    --to=alistair23@gmail.com \
    --cc="qemu-devel@nongnu.org \
    --cc=Alistair.Francis@wdc.com \
    --cc=bmeng.cn@gmail.com \
    --cc=palmer@sifive.com \
    --cc=qemu-riscv@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

QEMU-Devel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/qemu-devel/0 qemu-devel/git/0.git
	git clone --mirror https://lore.kernel.org/qemu-devel/1 qemu-devel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 qemu-devel qemu-devel/ https://lore.kernel.org/qemu-devel \
		qemu-devel@nongnu.org qemu-devel@archiver.kernel.org
	public-inbox-index qemu-devel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.nongnu.qemu-devel


AGPL code for this site: git clone https://public-inbox.org/ public-inbox