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From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: riku.voipio@iki.fi, richard.henderson@linaro.org,
	laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>,
	philmd@redhat.com, aleksandar.m.mail@gmail.com
Subject: [RFC PATCH v2 49/67] Hexagon TCG generation - step 11
Date: Fri, 28 Feb 2020 10:43:45 -0600	[thread overview]
Message-ID: <1582908244-304-50-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com>

Override compare, transfer, conditional jump instructions

Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
 target/hexagon/helper_overrides.h | 119 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/target/hexagon/helper_overrides.h b/target/hexagon/helper_overrides.h
index d3311be..ad9a88c 100644
--- a/target/hexagon/helper_overrides.h
+++ b/target/hexagon/helper_overrides.h
@@ -1432,4 +1432,123 @@
 #define fWRAP_J4_cmpeq_tp0_jump_t(GENHLPR, SHORTCODE) \
     gen_cmpnd_cmp_jmp(0, TCG_COND_EQ, true, RsV, RtV, riV)
 
+/* p0 = cmp.eq(r0, #7) */
+#define fWRAP_SA1_cmpeqi(GENHLPR, SHORTCODE) \
+    do { \
+        TCGv tmp = tcg_temp_new(); \
+        gen_comparei(TCG_COND_EQ, tmp, RsV, uiV); \
+        gen_log_pred_write(0, tmp); \
+        tcg_temp_free(tmp); \
+    } while (0)
+
+/* r0 = add(r29,#8) */
+#define fWRAP_SA1_addsp(GENHLPR, SHORTCODE) \
+    tcg_gen_addi_tl(RdV, hex_gpr[HEX_REG_SP], IMMNO(0))
+
+/* r0 = add(r0, r1) */
+#define fWRAP_SA1_addrx(GENHLPR, SHORTCODE) \
+    tcg_gen_add_tl(RxV, RxV, RsV)
+
+#define fWRAP_A2_add(GENHLPR, SHORTCODE) \
+    tcg_gen_add_tl(RdV, RsV, RtV)
+
+#define fWRAP_A2_sub(GENHLPR, SHORTCODE) \
+    tcg_gen_sub_tl(RdV, RtV, RsV)
+
+/* r0 = sub(#10, r1) */
+#define fWRAP_A2_subri(GENHLPR, SHORTCODE) \
+    tcg_gen_subfi_tl(RdV, siV, RsV)
+
+#define fWRAP_A2_addi(GENHLPR, SHORTCODE) \
+    tcg_gen_addi_tl(RdV, RsV, siV)
+
+#define fWRAP_A2_and(GENHLPR, SHORTCODE) \
+    tcg_gen_and_tl(RdV, RsV, RtV)
+
+#define fWRAP_A2_andir(GENHLPR, SHORTCODE) \
+    tcg_gen_andi_tl(RdV, RsV, siV)
+
+#define fWRAP_A2_xor(GENHLPR, SHORTCODE) \
+    tcg_gen_xor_tl(RdV, RsV, RtV)
+
+/* Transfer instructions */
+#define fWRAP_A2_tfr(GENHLPR, SHORTCODE) \
+    tcg_gen_mov_tl(RdV, RsV)
+#define fWRAP_SA1_tfr(GENHLPR, SHORTCODE) \
+    tcg_gen_mov_tl(RdV, RsV)
+#define fWRAP_A2_tfrsi(GENHLPR, SHORTCODE) \
+    tcg_gen_movi_tl(RdV, siV)
+#define fWRAP_A2_tfrcrr(GENHLPR, SHORTCODE) \
+    tcg_gen_mov_tl(RdV, CsV)
+#define fWRAP_A2_tfrrcr(GENHLPR, SHORTCODE) \
+    tcg_gen_mov_tl(CdV, RsV)
+
+#define fWRAP_A2_nop(GENHLPR, SHORTCODE) \
+    do { } while (0)
+
+/* Compare instructions */
+#define fWRAP_C2_cmpeq(GENHLPR, SHORTCODE) \
+    gen_compare(TCG_COND_EQ, PdV, RsV, RtV)
+#define fWRAP_C4_cmpneq(GENHLPR, SHORTCODE) \
+    gen_compare(TCG_COND_NE, PdV, RsV, RtV)
+#define fWRAP_C2_cmpgt(GENHLPR, SHORTCODE) \
+    gen_compare(TCG_COND_GT, PdV, RsV, RtV)
+#define fWRAP_C2_cmpgtu(GENHLPR, SHORTCODE) \
+    gen_compare(TCG_COND_GTU, PdV, RsV, RtV)
+#define fWRAP_C4_cmplte(GENHLPR, SHORTCODE) \
+    gen_compare(TCG_COND_LE, PdV, RsV, RtV)
+#define fWRAP_C4_cmplteu(GENHLPR, SHORTCODE) \
+    gen_compare(TCG_COND_LEU, PdV, RsV, RtV)
+#define fWRAP_C2_cmpeqp(GENHLPR, SHORTCODE) \
+    gen_compare_i64(TCG_COND_EQ, PdV, RssV, RttV)
+#define fWRAP_C2_cmpgtp(GENHLPR, SHORTCODE) \
+    gen_compare_i64(TCG_COND_GT, PdV, RssV, RttV)
+#define fWRAP_C2_cmpgtup(GENHLPR, SHORTCODE) \
+    gen_compare_i64(TCG_COND_GTU, PdV, RssV, RttV)
+#define fWRAP_C2_cmpeqi(GENHLPR, SHORTCODE) \
+    gen_comparei(TCG_COND_EQ, PdV, RsV, siV)
+#define fWRAP_C2_cmpgti(GENHLPR, SHORTCODE) \
+    gen_comparei(TCG_COND_GT, PdV, RsV, siV)
+#define fWRAP_C2_cmpgtui(GENHLPR, SHORTCODE) \
+    gen_comparei(TCG_COND_GTU, PdV, RsV, uiV)
+
+#define fWRAP_SA1_zxtb(GENHLPR, SHORTCODE) \
+    tcg_gen_ext8u_tl(RdV, RsV)
+
+#define fWRAP_J2_jump(GENHLPR, SHORTCODE) \
+    gen_jump(riV)
+#define fWRAP_J2_jumpr(GENHLPR, SHORTCODE) \
+    gen_write_new_pc(RsV)
+
+#define fWRAP_cond_jump(COND) \
+    do { \
+        TCGv LSB = tcg_temp_new(); \
+        COND; \
+        gen_cond_jump(LSB, riV); \
+        tcg_temp_free(LSB); \
+    } while (0)
+
+#define fWRAP_J2_jumpt(GENHLPR, SHORTCODE) \
+    fWRAP_cond_jump(fLSBOLD(PuV))
+#define fWRAP_J2_jumpf(GENHLPR, SHORTCODE) \
+    fWRAP_cond_jump(fLSBOLDNOT(PuV))
+#define fWRAP_J2_jumpfnewpt(GENHLPR, SHORTCODE) \
+    fWRAP_cond_jump(fLSBNEWNOT(PuN))
+#define fWRAP_J2_jumpfnew(GENHLPR, SHORTCODE) \
+    fWRAP_cond_jump(fLSBNEWNOT(PuN))
+
+#define fWRAP_J2_jumprfnew(GENHLPR, SHORTCODE) \
+    do { \
+        TCGv LSB = tcg_temp_new(); \
+        tcg_gen_andi_tl(LSB, PuN, 1); \
+        tcg_gen_xori_tl(LSB, LSB, 1); \
+        gen_cond_jumpr(LSB, RsV); \
+        tcg_temp_free(LSB); \
+    } while (0)
+
+#define fWRAP_J2_jumptnew(GENHLPR, SHORTCODE) \
+    gen_cond_jump(PuN, riV)
+#define fWRAP_J2_jumptnewpt(GENHLPR, SHORTCODE) \
+    gen_cond_jump(PuN, riV)
+
 #endif
-- 
2.7.4


  parent reply	other threads:[~2020-02-28 17:24 UTC|newest]

Thread overview: 72+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-28 16:42 [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 01/67] Hexagon Maintainers Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 02/67] Hexagon README Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 03/67] Hexagon ELF Machine Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 04/67] Hexagon CPU Scalar Core Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 05/67] Hexagon register names Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 06/67] Hexagon Disassembler Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 08/67] Hexagon GDB Stub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 09/67] Hexagon architecture types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 10/67] Hexagon instruction and packet types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 11/67] Hexagon register fields Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 12/67] Hexagon instruction attributes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 13/67] Hexagon register map Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 14/67] Hexagon instruction/packet decode Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 15/67] Hexagon instruction printing Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 17/67] Hexagon arch import - macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 19/67] Hexagon instruction class definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 20/67] Hexagon instruction utility functions Taylor Simpson
2020-04-09 18:53   ` Brian Cain
2020-04-09 20:22     ` Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 21/67] Hexagon generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 24/67] Hexagon generator phase 2 - opcodes_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 30/67] Hexagon opcode data structures Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 31/67] Hexagon macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 33/67] Hexagon instruction classes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 34/67] Hexagon TCG generation helpers - step 1 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 35/67] Hexagon TCG generation helpers - step 2 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 36/67] Hexagon TCG generation helpers - step 3 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 39/67] Hexagon TCG generation - step 01 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 40/67] Hexagon TCG generation - step 02 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 41/67] Hexagon TCG generation - step 03 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 42/67] Hexagon TCG generation - step 04 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 43/67] Hexagon TCG generation - step 05 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 44/67] Hexagon TCG generation - step 06 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 45/67] Hexagon TCG generation - step 07 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 46/67] Hexagon TCG generation - step 08 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 47/67] Hexagon TCG generation - step 09 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 48/67] Hexagon TCG generation - step 10 Taylor Simpson
2020-02-28 16:43 ` Taylor Simpson [this message]
2020-02-28 16:43 ` [RFC PATCH v2 50/67] Hexagon TCG generation - step 12 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 51/67] Hexagon translation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 52/67] Hexagon Linux user emulation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 53/67] Hexagon build infrastructure Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 55/67] Hexagon HVX support in gdbstub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 56/67] Hexagon HVX import instruction encodings Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 57/67] Hexagon HVX import semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 58/67] Hexagon HVX import macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 59/67] Hexagon HVX semantics generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 60/67] Hexagon HVX instruction decoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 61/67] Hexagon HVX instruction utility functions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 63/67] Hexagon HVX macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 65/67] Hexagon HVX TCG generation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 66/67] Hexagon HVX translation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 67/67] Hexagon HVX build infrastructure Taylor Simpson
2020-03-25 21:13 ` [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-04-30 20:53   ` Taylor Simpson

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