From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: riku.voipio@iki.fi, richard.henderson@linaro.org,
laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>,
philmd@redhat.com, aleksandar.m.mail@gmail.com
Subject: [RFC PATCH v2 65/67] Hexagon HVX TCG generation
Date: Fri, 28 Feb 2020 10:44:01 -0600 [thread overview]
Message-ID: <1582908244-304-66-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/genptr_helpers.h | 202 ++++++++++++++++++++++++++++++++++++++++
target/hexagon/genptr.c | 1 +
2 files changed, 203 insertions(+)
diff --git a/target/hexagon/genptr_helpers.h b/target/hexagon/genptr_helpers.h
index e342f29..84479f8 100644
--- a/target/hexagon/genptr_helpers.h
+++ b/target/hexagon/genptr_helpers.h
@@ -844,4 +844,206 @@ static inline void gen_lshiftr_4_4u(TCGv dst, TCGv src, int32_t shift_amt)
}
}
+static inline uint32_t new_temp_vreg_offset(DisasContext *ctx, int num)
+{
+ uint32_t offset =
+ offsetof(CPUHexagonState, temp_vregs[ctx->ctx_temp_vregs_idx]);
+
+ HEX_DEBUG_LOG("new_temp_vreg_offset: %d\n", ctx->ctx_temp_vregs_idx);
+ g_assert(ctx->ctx_temp_vregs_idx + num - 1 < TEMP_VECTORS_MAX);
+ ctx->ctx_temp_vregs_idx += num;
+ return offset;
+}
+
+static inline uint32_t new_temp_qreg_offset(DisasContext *ctx)
+{
+ uint32_t offset =
+ offsetof(CPUHexagonState, temp_qregs[ctx->ctx_temp_qregs_idx]);
+
+ HEX_DEBUG_LOG("new_temp_qreg_offset: %d\n", ctx->ctx_temp_qregs_idx);
+ g_assert(ctx->ctx_temp_qregs_idx < TEMP_VECTORS_MAX);
+ ctx->ctx_temp_qregs_idx++;
+ return offset;
+}
+
+static inline void gen_read_qreg(TCGv_ptr var, int num, int vtmp)
+{
+ uint32_t offset = offsetof(CPUHexagonState, QRegs[(num)]);
+ TCGv_ptr src = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(src, cpu_env, offset);
+ gen_memcpy(var, src, sizeof(mmqreg_t));
+ tcg_temp_free_ptr(src);
+}
+
+static inline void gen_read_vreg_ptr_src(TCGv_ptr ptr_src, int num, int vtmp)
+{
+ TCGv zero = tcg_const_tl(0);
+ TCGv offset_future =
+ tcg_const_tl(offsetof(CPUHexagonState, future_VRegs[num]));
+ TCGv offset_vregs =
+ tcg_const_tl(offsetof(CPUHexagonState, VRegs[num]));
+ TCGv offset_tmp_vregs =
+ tcg_const_tl(offsetof(CPUHexagonState, tmp_VRegs[num]));
+ TCGv offset = tcg_temp_new();
+ TCGv_ptr offset_ptr = tcg_temp_new_ptr();
+ TCGv new_written = tcg_temp_new();
+ TCGv tmp_written = tcg_temp_new();
+
+ /*
+ * new_written = (hex_VRegs_select >> num) & 1;
+ * offset = new_written ? offset_future, offset_vregs;
+ */
+ tcg_gen_shri_tl(new_written, hex_VRegs_select, num);
+ tcg_gen_andi_tl(new_written, new_written, 1);
+ tcg_gen_movcond_tl(TCG_COND_NE, offset, new_written, zero,
+ offset_future, offset_vregs);
+
+ /*
+ * tmp_written = (hex_VRegs_updated_tmp >> num) & 1;
+ * if (tmp_written) offset = offset_tmp_vregs;
+ */
+ tcg_gen_shri_tl(tmp_written, hex_VRegs_updated_tmp, num);
+ tcg_gen_andi_tl(tmp_written, tmp_written, 1);
+ tcg_gen_movcond_tl(TCG_COND_NE, offset, tmp_written, zero,
+ offset_tmp_vregs, offset);
+
+ if (vtmp == EXT_TMP) {
+ TCGv vregs_updated = tcg_temp_new();
+ TCGv temp = tcg_temp_new();
+
+ /*
+ * vregs_updated = hex_VRegs_updates & (1 << num);
+ * if (vregs_updated) {
+ * offset = offset_future;
+ * hex_VRegs_updated ^= (1 << num);
+ * }
+ */
+ tcg_gen_andi_tl(vregs_updated, hex_VRegs_updated, 1 << num);
+ tcg_gen_movcond_tl(TCG_COND_NE, offset, vregs_updated, zero,
+ offset_future, offset);
+ tcg_gen_xori_tl(temp, hex_VRegs_updated, 1 << num);
+ tcg_gen_movcond_tl(TCG_COND_NE, hex_VRegs_updated, vregs_updated, zero,
+ temp, hex_VRegs_updated);
+
+ tcg_temp_free(vregs_updated);
+ tcg_temp_free(temp);
+ }
+
+ tcg_gen_ext_i32_ptr(offset_ptr, offset);
+ tcg_gen_add_ptr(ptr_src, cpu_env, offset_ptr);
+
+ tcg_temp_free(zero);
+ tcg_temp_free(offset_future);
+ tcg_temp_free(offset_vregs);
+ tcg_temp_free(offset_tmp_vregs);
+ tcg_temp_free(offset);
+ tcg_temp_free_ptr(offset_ptr);
+ tcg_temp_free(new_written);
+ tcg_temp_free(tmp_written);
+}
+
+static inline void gen_read_vreg_readonly(TCGv_ptr var, int num, int vtmp)
+{
+ TCGv_ptr ptr_src = tcg_temp_new_ptr();
+ gen_read_vreg_ptr_src(ptr_src, num, vtmp);
+ tcg_gen_addi_ptr(var, ptr_src, 0);
+ tcg_temp_free_ptr(ptr_src);
+}
+
+static inline void gen_read_vreg(TCGv_ptr var, int num, int vtmp)
+{
+ TCGv_ptr ptr_src = tcg_temp_new_ptr();
+ gen_read_vreg_ptr_src(ptr_src, num, vtmp);
+ gen_memcpy(var, ptr_src, sizeof(mmvector_t));
+ tcg_temp_free_ptr(ptr_src);
+}
+
+static inline void gen_read_vreg_pair(TCGv_ptr var, int num, int vtmp)
+{
+ TCGv_ptr v0 = tcg_temp_new_ptr();
+ TCGv_ptr v1 = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(v0, var, offsetof(mmvector_pair_t, v[0]));
+ gen_read_vreg(v0, num ^ 0, vtmp);
+ tcg_gen_addi_ptr(v1, var, offsetof(mmvector_pair_t, v[1]));
+ gen_read_vreg(v1, num ^ 1, vtmp);
+ tcg_temp_free_ptr(v0);
+ tcg_temp_free_ptr(v1);
+}
+
+static inline void gen_log_vreg_write(TCGv_ptr var, int num, int vnew,
+ int slot_num)
+{
+ TCGv cancelled = tcg_temp_local_new();
+ TCGLabel *label_end = gen_new_label();
+
+ /* Don't do anything if the slot was cancelled */
+ gen_slot_cancelled_check(cancelled, slot_num);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
+ {
+ TCGv mask = tcg_const_tl(1 << num);
+ TCGv_ptr dst = tcg_temp_new_ptr();
+ if (vnew != EXT_TMP) {
+ tcg_gen_or_tl(hex_VRegs_updated, hex_VRegs_updated, mask);
+ }
+ if (vnew == EXT_NEW) {
+ tcg_gen_or_tl(hex_VRegs_select, hex_VRegs_select, mask);
+ }
+ if (vnew == EXT_TMP) {
+ tcg_gen_or_tl(hex_VRegs_updated_tmp, hex_VRegs_updated_tmp, mask);
+ }
+ tcg_gen_addi_ptr(dst, cpu_env,
+ offsetof(CPUHexagonState, future_VRegs[num]));
+ gen_memcpy(dst, var, sizeof(mmvector_t));
+ if (vnew == EXT_TMP) {
+ TCGv_ptr src = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(dst, cpu_env,
+ offsetof(CPUHexagonState, tmp_VRegs[num]));
+ tcg_gen_addi_ptr(src, cpu_env,
+ offsetof(CPUHexagonState, future_VRegs[num]));
+ gen_memcpy(dst, src, sizeof(mmvector_t));
+ tcg_temp_free_ptr(src);
+ }
+ tcg_temp_free(mask);
+ tcg_temp_free_ptr(dst);
+ }
+ gen_set_label(label_end);
+
+ tcg_temp_free(cancelled);
+}
+
+static inline void gen_log_vreg_write_pair(TCGv_ptr var, int num, int vnew,
+ int slot_num)
+{
+ TCGv_ptr v0 = tcg_temp_local_new_ptr();
+ TCGv_ptr v1 = tcg_temp_local_new_ptr();
+ tcg_gen_addi_ptr(v0, var, offsetof(mmvector_pair_t, v[0]));
+ gen_log_vreg_write(v0, num ^ 0, vnew, slot_num);
+ tcg_gen_addi_ptr(v1, var, offsetof(mmvector_pair_t, v[1]));
+ gen_log_vreg_write(v1, num ^ 1, vnew, slot_num);
+ tcg_temp_free_ptr(v0);
+ tcg_temp_free_ptr(v1);
+}
+
+static inline void gen_log_qreg_write(TCGv_ptr var, int num, int vnew,
+ int slot_num)
+{
+ TCGv cancelled = tcg_temp_local_new();
+ TCGLabel *label_end = gen_new_label();
+
+ /* Don't do anything if the slot was cancelled */
+ gen_slot_cancelled_check(cancelled, slot_num);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cancelled, 0, label_end);
+ {
+ TCGv_ptr dst = tcg_temp_new_ptr();
+ tcg_gen_addi_ptr(dst, cpu_env,
+ offsetof(CPUHexagonState, future_QRegs[num]));
+ gen_memcpy(dst, var, sizeof(mmqreg_t));
+ tcg_gen_ori_tl(hex_QRegs_updated, hex_QRegs_updated, 1 << num);
+ tcg_temp_free_ptr(dst);
+ }
+ gen_set_label(label_end);
+
+ tcg_temp_free(cancelled);
+}
+
#endif
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 6b9cc0d..588360d 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -25,6 +25,7 @@
#include "opcodes.h"
#include "translate.h"
#include "macros.h"
+#include "mmvec/macros.h"
#include "genptr_helpers.h"
#include "helper_overrides.h"
--
2.7.4
next prev parent reply other threads:[~2020-02-28 17:26 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 16:42 [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 01/67] Hexagon Maintainers Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 02/67] Hexagon README Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 03/67] Hexagon ELF Machine Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 04/67] Hexagon CPU Scalar Core Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 05/67] Hexagon register names Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 06/67] Hexagon Disassembler Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 08/67] Hexagon GDB Stub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 09/67] Hexagon architecture types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 10/67] Hexagon instruction and packet types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 11/67] Hexagon register fields Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 12/67] Hexagon instruction attributes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 13/67] Hexagon register map Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 14/67] Hexagon instruction/packet decode Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 15/67] Hexagon instruction printing Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 17/67] Hexagon arch import - macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 19/67] Hexagon instruction class definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 20/67] Hexagon instruction utility functions Taylor Simpson
2020-04-09 18:53 ` Brian Cain
2020-04-09 20:22 ` Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 21/67] Hexagon generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 24/67] Hexagon generator phase 2 - opcodes_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 30/67] Hexagon opcode data structures Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 31/67] Hexagon macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 33/67] Hexagon instruction classes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 34/67] Hexagon TCG generation helpers - step 1 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 35/67] Hexagon TCG generation helpers - step 2 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 36/67] Hexagon TCG generation helpers - step 3 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 39/67] Hexagon TCG generation - step 01 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 40/67] Hexagon TCG generation - step 02 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 41/67] Hexagon TCG generation - step 03 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 42/67] Hexagon TCG generation - step 04 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 43/67] Hexagon TCG generation - step 05 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 44/67] Hexagon TCG generation - step 06 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 45/67] Hexagon TCG generation - step 07 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 46/67] Hexagon TCG generation - step 08 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 47/67] Hexagon TCG generation - step 09 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 48/67] Hexagon TCG generation - step 10 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 49/67] Hexagon TCG generation - step 11 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 50/67] Hexagon TCG generation - step 12 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 51/67] Hexagon translation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 52/67] Hexagon Linux user emulation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 53/67] Hexagon build infrastructure Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 55/67] Hexagon HVX support in gdbstub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 56/67] Hexagon HVX import instruction encodings Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 57/67] Hexagon HVX import semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 58/67] Hexagon HVX import macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 59/67] Hexagon HVX semantics generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 60/67] Hexagon HVX instruction decoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 61/67] Hexagon HVX instruction utility functions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 63/67] Hexagon HVX macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Taylor Simpson
2020-02-28 16:44 ` Taylor Simpson [this message]
2020-02-28 16:44 ` [RFC PATCH v2 66/67] Hexagon HVX translation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 67/67] Hexagon HVX build infrastructure Taylor Simpson
2020-03-25 21:13 ` [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-04-30 20:53 ` Taylor Simpson
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