From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: riku.voipio@iki.fi, richard.henderson@linaro.org,
laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>,
philmd@redhat.com, aleksandar.m.mail@gmail.com
Subject: [RFC PATCH v2 61/67] Hexagon HVX instruction utility functions
Date: Fri, 28 Feb 2020 10:43:57 -0600 [thread overview]
Message-ID: <1582908244-304-62-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com>
Functions to support scatter/gather
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/mmvec/system_ext_mmvec.h | 38 +++++
target/hexagon/mmvec/system_ext_mmvec.c | 263 ++++++++++++++++++++++++++++++++
2 files changed, 301 insertions(+)
create mode 100644 target/hexagon/mmvec/system_ext_mmvec.h
create mode 100644 target/hexagon/mmvec/system_ext_mmvec.c
diff --git a/target/hexagon/mmvec/system_ext_mmvec.h b/target/hexagon/mmvec/system_ext_mmvec.h
new file mode 100644
index 0000000..4f35966
--- /dev/null
+++ b/target/hexagon/mmvec/system_ext_mmvec.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HEXAGON_SYSTEM_EXT_MMVEC_H
+#define HEXAGON_SYSTEM_EXT_MMVEC_H
+
+extern void mem_load_vector_oddva(CPUHexagonState *env, vaddr_t vaddr,
+ vaddr_t lookup_vaddr, int slot, int size,
+ size1u_t *data, int use_full_va);
+extern void mem_store_vector_oddva(CPUHexagonState *env, vaddr_t vaddr,
+ vaddr_t lookup_vaddr, int slot, int size,
+ size1u_t *data, size1u_t* mask, unsigned invert,
+ int use_full_va);
+extern void mem_vector_scatter_init(CPUHexagonState *env, int slot,
+ vaddr_t base_vaddr, int length,
+ int element_size);
+extern void mem_vector_scatter_finish(CPUHexagonState *env, int slot, int op);
+extern void mem_vector_gather_finish(CPUHexagonState *env, int slot);
+extern void mem_vector_gather_init(CPUHexagonState *env, int slot,
+ vaddr_t base_vaddr, int length,
+ int element_size);
+
+
+#endif
diff --git a/target/hexagon/mmvec/system_ext_mmvec.c b/target/hexagon/mmvec/system_ext_mmvec.c
new file mode 100644
index 0000000..e0df96e
--- /dev/null
+++ b/target/hexagon/mmvec/system_ext_mmvec.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "opcodes.h"
+#include "insn.h"
+#include "mmvec/macros.h"
+#include "qemu.h"
+
+#define TYPE_LOAD 'L'
+#define TYPE_STORE 'S'
+#define TYPE_FETCH 'F'
+#define TYPE_ICINVA 'I'
+
+enum mem_access_types {
+ access_type_INVALID = 0,
+ access_type_unknown = 1,
+ access_type_load = 2,
+ access_type_store = 3,
+ access_type_fetch = 4,
+ access_type_dczeroa = 5,
+ access_type_dccleana = 6,
+ access_type_dcinva = 7,
+ access_type_dccleaninva = 8,
+ access_type_icinva = 9,
+ access_type_ictagr = 10,
+ access_type_ictagw = 11,
+ access_type_icdatar = 12,
+ access_type_dcfetch = 13,
+ access_type_l2fetch = 14,
+ access_type_l2cleanidx = 15,
+ access_type_l2cleaninvidx = 16,
+ access_type_l2tagr = 17,
+ access_type_l2tagw = 18,
+ access_type_dccleanidx = 19,
+ access_type_dcinvidx = 20,
+ access_type_dccleaninvidx = 21,
+ access_type_dctagr = 22,
+ access_type_dctagw = 23,
+ access_type_k0unlock = 24,
+ access_type_l2locka = 25,
+ access_type_l2unlocka = 26,
+ access_type_l2kill = 27,
+ access_type_l2gclean = 28,
+ access_type_l2gcleaninv = 29,
+ access_type_l2gunlock = 30,
+ access_type_synch = 31,
+ access_type_isync = 32,
+ access_type_pause = 33,
+ access_type_load_phys = 34,
+ access_type_load_locked = 35,
+ access_type_store_conditional = 36,
+ access_type_barrier = 37,
+ access_type_memcpy_load = 39,
+ access_type_memcpy_store = 40,
+
+ NUM_CORE_ACCESS_TYPES
+};
+
+enum ext_mem_access_types {
+ access_type_vload = NUM_CORE_ACCESS_TYPES,
+ access_type_vstore,
+ access_type_vload_nt,
+ access_type_vstore_nt,
+ access_type_vgather_load,
+ access_type_vscatter_store,
+ access_type_vscatter_release,
+ access_type_vgather_release,
+ access_type_vfetch,
+ NUM_EXT_ACCESS_TYPES
+};
+
+static inline
+target_ulong mem_init_access(CPUHexagonState *env, int slot, size4u_t vaddr,
+ int width, enum mem_access_types mtype,
+ int type_for_xlate)
+{
+#ifdef CONFIG_USER_ONLY
+ /* Nothing to do for Linux user mode in qemu */
+ return vaddr;
+#else
+#error System mode not yet implemented for Hexagon
+#endif
+}
+
+static inline int check_gather_store(CPUHexagonState *env)
+{
+ /* First check to see if temp vreg has been updated */
+ int check = env->gather_issued;
+ check &= env->is_gather_store_insn;
+
+ /* In case we don't have store, suppress gather */
+ if (!check) {
+ env->gather_issued = 0;
+ env->vtcm_pending = 0; /* Suppress any gather writes to memory */
+ }
+ return check;
+}
+
+void mem_store_vector_oddva(CPUHexagonState *env, vaddr_t vaddr,
+ vaddr_t lookup_vaddr, int slot, int size,
+ size1u_t *data, size1u_t *mask, unsigned invert,
+ int use_full_va)
+{
+ int i;
+
+ if (!use_full_va) {
+ lookup_vaddr = vaddr;
+ }
+
+ if (!size) {
+ return;
+ }
+
+ int is_gather_store = check_gather_store(env);
+ if (is_gather_store) {
+ memcpy(data, &env->tmp_VRegs[0].ub[0], size);
+ env->VRegs_updated_tmp = 0;
+ env->gather_issued = 0;
+ }
+
+ /*
+ * If it's a gather store update store data from temporary register
+ * And clear flag
+ */
+ env->vstore_pending[slot] = 1;
+ env->vstore[slot].va = vaddr;
+ env->vstore[slot].size = size;
+ memcpy(&env->vstore[slot].data.ub[0], data, size);
+ if (!mask) {
+ memset(&env->vstore[slot].mask.ub[0], invert ? 0 : -1, size);
+ } else if (invert) {
+ for (i = 0; i < size; i++) {
+ env->vstore[slot].mask.ub[i] = !mask[i];
+ }
+ } else {
+ memcpy(&env->vstore[slot].mask.ub[0], mask, size);
+ }
+ /* On a gather store, overwrite the store mask to emulate dropped gathers */
+ if (is_gather_store) {
+ memcpy(&env->vstore[slot].mask.ub[0], &env->vtcm_log.mask.ub[0], size);
+ }
+ for (i = 0; i < size; i++) {
+ env->mem_access[slot].cdata[i] = data[i];
+ }
+}
+
+void mem_load_vector_oddva(CPUHexagonState *env, vaddr_t vaddr,
+ vaddr_t lookup_vaddr, int slot, int size,
+ size1u_t *data, int use_full_va)
+{
+ int i;
+
+ if (!use_full_va) {
+ lookup_vaddr = vaddr;
+ }
+
+ if (!size) {
+ return;
+ }
+
+ for (i = 0; i < size; i++) {
+ get_user_u8(data[i], vaddr);
+ vaddr++;
+ }
+}
+
+void mem_vector_scatter_init(CPUHexagonState *env, int slot, vaddr_t base_vaddr,
+ int length, int element_size)
+{
+ enum ext_mem_access_types access_type = access_type_vscatter_store;
+ int i;
+
+ /* Translation for Store Address on Slot 1 - maybe any slot? */
+ mem_init_access(env, slot, base_vaddr, 1, access_type, TYPE_STORE);
+ mem_access_info_t *maptr = &env->mem_access[slot];
+ if (EXCEPTION_DETECTED) {
+ return;
+ }
+
+ maptr->range = length;
+
+ for (i = 0; i < fVECSIZE(); i++) {
+ env->vtcm_log.offsets.ub[i] = 0; /* Mark invalid */
+ env->vtcm_log.data.ub[i] = 0;
+ env->vtcm_log.mask.ub[i] = 0;
+ }
+ env->vtcm_log.va_base = base_vaddr;
+
+ env->vtcm_pending = 1;
+ env->vtcm_log.oob_access = 0;
+ env->vtcm_log.op = 0;
+ env->vtcm_log.op_size = 0;
+ return;
+}
+
+void mem_vector_gather_init(CPUHexagonState *env, int slot, vaddr_t base_vaddr,
+ int length, int element_size)
+{
+ enum ext_mem_access_types access_type = access_type_vgather_load;
+ int i;
+
+ mem_init_access(env, slot, base_vaddr, 1, access_type, TYPE_LOAD);
+ mem_access_info_t *maptr = &env->mem_access[slot];
+
+ if (EXCEPTION_DETECTED) {
+ return;
+ }
+
+ maptr->range = length;
+
+ for (i = 0; i < 2 * fVECSIZE(); i++) {
+ env->vtcm_log.offsets.ub[i] = 0x0;
+ }
+ for (i = 0; i < fVECSIZE(); i++) {
+ env->vtcm_log.data.ub[i] = 0;
+ env->vtcm_log.mask.ub[i] = 0;
+ env->vtcm_log.va[i] = 0;
+ env->tmp_VRegs[0].ub[i] = 0;
+ }
+ env->vtcm_log.oob_access = 0;
+ env->vtcm_log.op = 0;
+ env->vtcm_log.op_size = 0;
+
+ env->vtcm_log.va_base = base_vaddr;
+
+ /*
+ * Temp Reg gets updated
+ * This allows Store .new to grab the correct result
+ */
+ env->VRegs_updated_tmp = 1;
+ env->gather_issued = 1;
+
+ return;
+}
+
+void mem_vector_scatter_finish(CPUHexagonState *env, int slot, int op)
+{
+ env->store_pending[slot] = 0;
+ env->vstore_pending[slot] = 0;
+ env->vtcm_log.size = fVECSIZE();
+
+ memcpy(env->mem_access[slot].cdata, &env->vtcm_log.offsets.ub[0], 256);
+}
+
+void mem_vector_gather_finish(CPUHexagonState *env, int slot)
+{
+ memcpy(env->mem_access[slot].cdata, &env->vtcm_log.offsets.ub[0], 256);
+}
--
2.7.4
next prev parent reply other threads:[~2020-02-28 17:22 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 16:42 [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 01/67] Hexagon Maintainers Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 02/67] Hexagon README Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 03/67] Hexagon ELF Machine Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 04/67] Hexagon CPU Scalar Core Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 05/67] Hexagon register names Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 06/67] Hexagon Disassembler Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 08/67] Hexagon GDB Stub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 09/67] Hexagon architecture types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 10/67] Hexagon instruction and packet types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 11/67] Hexagon register fields Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 12/67] Hexagon instruction attributes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 13/67] Hexagon register map Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 14/67] Hexagon instruction/packet decode Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 15/67] Hexagon instruction printing Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 17/67] Hexagon arch import - macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 19/67] Hexagon instruction class definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 20/67] Hexagon instruction utility functions Taylor Simpson
2020-04-09 18:53 ` Brian Cain
2020-04-09 20:22 ` Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 21/67] Hexagon generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 24/67] Hexagon generator phase 2 - opcodes_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 30/67] Hexagon opcode data structures Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 31/67] Hexagon macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 33/67] Hexagon instruction classes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 34/67] Hexagon TCG generation helpers - step 1 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 35/67] Hexagon TCG generation helpers - step 2 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 36/67] Hexagon TCG generation helpers - step 3 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 39/67] Hexagon TCG generation - step 01 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 40/67] Hexagon TCG generation - step 02 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 41/67] Hexagon TCG generation - step 03 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 42/67] Hexagon TCG generation - step 04 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 43/67] Hexagon TCG generation - step 05 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 44/67] Hexagon TCG generation - step 06 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 45/67] Hexagon TCG generation - step 07 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 46/67] Hexagon TCG generation - step 08 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 47/67] Hexagon TCG generation - step 09 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 48/67] Hexagon TCG generation - step 10 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 49/67] Hexagon TCG generation - step 11 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 50/67] Hexagon TCG generation - step 12 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 51/67] Hexagon translation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 52/67] Hexagon Linux user emulation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 53/67] Hexagon build infrastructure Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 55/67] Hexagon HVX support in gdbstub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 56/67] Hexagon HVX import instruction encodings Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 57/67] Hexagon HVX import semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 58/67] Hexagon HVX import macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 59/67] Hexagon HVX semantics generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 60/67] Hexagon HVX instruction decoding Taylor Simpson
2020-02-28 16:43 ` Taylor Simpson [this message]
2020-02-28 16:43 ` [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 63/67] Hexagon HVX macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 65/67] Hexagon HVX TCG generation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 66/67] Hexagon HVX translation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 67/67] Hexagon HVX build infrastructure Taylor Simpson
2020-03-25 21:13 ` [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-04-30 20:53 ` Taylor Simpson
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