From: Taylor Simpson <tsimpson@quicinc.com>
To: qemu-devel@nongnu.org
Cc: riku.voipio@iki.fi, richard.henderson@linaro.org,
laurent@vivier.eu, Taylor Simpson <tsimpson@quicinc.com>,
philmd@redhat.com, aleksandar.m.mail@gmail.com
Subject: [RFC PATCH v2 50/67] Hexagon TCG generation - step 12
Date: Fri, 28 Feb 2020 10:43:46 -0600 [thread overview]
Message-ID: <1582908244-304-51-git-send-email-tsimpson@quicinc.com> (raw)
In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com>
Override miscellaneous instructions identified during profiling
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
---
target/hexagon/helper_overrides.h | 296 ++++++++++++++++++++++++++++++++++++++
1 file changed, 296 insertions(+)
diff --git a/target/hexagon/helper_overrides.h b/target/hexagon/helper_overrides.h
index ad9a88c..b796ced 100644
--- a/target/hexagon/helper_overrides.h
+++ b/target/hexagon/helper_overrides.h
@@ -1551,4 +1551,300 @@
#define fWRAP_J2_jumptnewpt(GENHLPR, SHORTCODE) \
gen_cond_jump(PuN, riV)
+/*
+ * New value compare & jump instructions
+ * if ([!]COND(r0.new, r1) jump:t address
+ * if ([!]COND(r0.new, #7) jump:t address
+ */
+#define fWRAP_J4_cmpgt_f_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmp_jumpnv(TCG_COND_LE, NsX, RtV, riV)
+#define fWRAP_J4_cmpeq_f_jumpnv_nt(GENHLPR, SHORTCODE) \
+ gen_cmp_jumpnv(TCG_COND_NE, NsX, RtV, riV)
+#define fWRAP_J4_cmpgt_t_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmp_jumpnv(TCG_COND_GT, NsX, RtV, riV)
+#define fWRAP_J4_cmpeqi_t_jumpnv_nt(GENHLPR, SHORTCODE) \
+ gen_cmpi_jumpnv(TCG_COND_EQ, NsX, UiV, riV)
+#define fWRAP_J4_cmpltu_f_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmp_jumpnv(TCG_COND_GEU, NsX, RtV, riV)
+#define fWRAP_J4_cmpgtui_t_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmpi_jumpnv(TCG_COND_GTU, NsX, UiV, riV)
+#define fWRAP_J4_cmpeq_f_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmp_jumpnv(TCG_COND_NE, NsX, RtV, riV)
+#define fWRAP_J4_cmpeqi_f_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmpi_jumpnv(TCG_COND_NE, NsX, UiV, riV)
+#define fWRAP_J4_cmpgtu_t_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmp_jumpnv(TCG_COND_GTU, NsX, RtV, riV)
+#define fWRAP_J4_cmpgtu_f_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmp_jumpnv(TCG_COND_LEU, NsX, RtV, riV)
+#define fWRAP_J4_cmplt_t_jumpnv_t(GENHLPR, SHORTCODE) \
+ gen_cmp_jumpnv(TCG_COND_LT, NsX, RtV, riV)
+
+/* r0 = r1 ; jump address */
+#define fWRAP_J4_jumpsetr(GENHLPR, SHORTCODE) \
+ do { \
+ tcg_gen_mov_tl(RdV, RsV); \
+ gen_jump(riV); \
+ } while (0)
+
+/* r0 = lsr(r1, #5) */
+#define fWRAP_S2_lsr_i_r(GENHLPR, SHORTCODE) \
+ fLSHIFTR(RdV, RsV, IMMNO(0), 4_4)
+
+/* r0 += lsr(r1, #5) */
+#define fWRAP_S2_lsr_i_r_acc(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ fLSHIFTR(tmp, RsV, IMMNO(0), 4_4); \
+ tcg_gen_add_tl(RxV, RxV, tmp); \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+/* r0 ^= lsr(r1, #5) */
+#define fWRAP_S2_lsr_i_r_xacc(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ fLSHIFTR(tmp, RsV, IMMNO(0), 4_4); \
+ tcg_gen_xor_tl(RxV, RxV, tmp); \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+/* r0 = asr(r1, #5) */
+#define fWRAP_S2_asr_i_r(GENHLPR, SHORTCODE) \
+ fASHIFTR(RdV, RsV, IMMNO(0), 4_4)
+
+/* r0 = addasl(r1, r2, #3) */
+#define fWRAP_S2_addasl_rrri(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ fASHIFTL(tmp, RsV, IMMNO(0), 4_4); \
+ tcg_gen_add_tl(RdV, RtV, tmp); \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+/* r0 |= asl(r1, r2) */
+#define fWRAP_S2_asl_r_r_or(GENHLPR, SHORTCODE) \
+ gen_asl_r_r_or(RxV, RsV, RtV)
+
+/* r0 = asl(r1, #5) */
+#define fWRAP_S2_asl_i_r(GENHLPR, SHORTCODE) \
+ fASHIFTL(RdV, RsV, IMMNO(0), 4_4)
+
+/* r0 |= asl(r1, #5) */
+#define fWRAP_S2_asl_i_r_or(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ fASHIFTL(tmp, RsV, IMMNO(0), 4_4); \
+ tcg_gen_or_tl(RxV, RxV, tmp); \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+/* r0 = vsplatb(r1) */
+#define fWRAP_S2_vsplatrb(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ int i; \
+ tcg_gen_movi_tl(RdV, 0); \
+ tcg_gen_andi_tl(tmp, RsV, 0xff); \
+ for (i = 0; i < 4; i++) { \
+ tcg_gen_shli_tl(RdV, RdV, 8); \
+ tcg_gen_or_tl(RdV, RdV, tmp); \
+ } \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+#define fWRAP_SA1_seti(GENHLPR, SHORTCODE) \
+ tcg_gen_movi_tl(RdV, IMMNO(0))
+
+#define fWRAP_S2_insert(GENHLPR, SHORTCODE) \
+ tcg_gen_deposit_i32(RxV, RxV, RsV, IMMNO(1), IMMNO(0))
+
+#define fWRAP_S2_extractu(GENHLPR, SHORTCODE) \
+ tcg_gen_extract_i32(RdV, RsV, IMMNO(1), IMMNO(0))
+
+#define fWRAP_A2_combinew(GENHLPR, SHORTCODE) \
+ tcg_gen_concat_i32_i64(RddV, RtV, RsV)
+#define fWRAP_A2_combineii(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp_lo = tcg_const_tl(SiV); \
+ TCGv tmp_hi = tcg_const_tl(siV); \
+ tcg_gen_concat_i32_i64(RddV, tmp_lo, tmp_hi); \
+ tcg_temp_free(tmp_lo); \
+ tcg_temp_free(tmp_hi); \
+ } while (0)
+#define fWRAP_A4_combineri(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp_lo = tcg_const_tl(siV); \
+ tcg_gen_concat_i32_i64(RddV, tmp_lo, RsV); \
+ tcg_temp_free(tmp_lo); \
+ } while (0)
+#define fWRAP_A4_combineir(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp_hi = tcg_const_tl(siV); \
+ tcg_gen_concat_i32_i64(RddV, RsV, tmp_hi); \
+ tcg_temp_free(tmp_hi); \
+ } while (0)
+#define fWRAP_A4_combineii(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp_lo = tcg_const_tl(UiV); \
+ TCGv tmp_hi = tcg_const_tl(siV); \
+ tcg_gen_concat_i32_i64(RddV, tmp_lo, tmp_hi); \
+ tcg_temp_free(tmp_lo); \
+ tcg_temp_free(tmp_hi); \
+ } while (0)
+
+#define fWRAP_SA1_combine0i(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp_lo = tcg_const_tl(uiV); \
+ TCGv zero = tcg_const_tl(0); \
+ tcg_gen_concat_i32_i64(RddV, tmp_lo, zero); \
+ tcg_temp_free(tmp_lo); \
+ tcg_temp_free(zero); \
+ } while (0)
+
+/* r0 = or(#8, asl(r1, #5)) */
+#define fWRAP_S4_ori_asl_ri(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ tcg_gen_shli_tl(tmp, RxV, IMMNO(1)); \
+ tcg_gen_ori_tl(RxV, tmp, IMMNO(0)); \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+/* r0 = add(r1, sub(#6, r2)) */
+#define fWRAP_S4_subaddi(GENHLPR, SHORTCODE) \
+ do { \
+ tcg_gen_sub_tl(RdV, RsV, RuV); \
+ tcg_gen_addi_tl(RdV, RdV, IMMNO(0)); \
+ } while (0)
+
+#define fWRAP_SA1_inc(GENHLPR, SHORTCODE) \
+ tcg_gen_addi_tl(RdV, RsV, 1)
+
+#define fWRAP_SA1_dec(GENHLPR, SHORTCODE) \
+ tcg_gen_subi_tl(RdV, RsV, 1)
+
+/* if (p0.new) r0 = #0 */
+#define fWRAP_SA1_clrtnew(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv mask = tcg_temp_new(); \
+ TCGv zero = tcg_const_tl(0); \
+ tcg_gen_movi_tl(RdV, 0); \
+ tcg_gen_movi_tl(mask, 1 << insn->slot); \
+ tcg_gen_or_tl(mask, hex_slot_cancelled, mask); \
+ tcg_gen_movcond_tl(TCG_COND_EQ, hex_slot_cancelled, \
+ hex_new_pred_value[0], zero, \
+ mask, hex_slot_cancelled); \
+ tcg_temp_free(mask); \
+ tcg_temp_free(zero); \
+ } while (0)
+
+/* r0 = add(r1 , mpyi(#6, r2)) */
+#define fWRAP_M4_mpyri_addr_u2(GENHLPR, SHORTCODE) \
+ do { \
+ tcg_gen_muli_tl(RdV, RsV, IMMNO(0)); \
+ tcg_gen_add_tl(RdV, RuV, RdV); \
+ } while (0)
+
+/* Predicated add instructions */
+#define WRAP_padd(PRED, ADD) \
+ do { \
+ TCGv LSB = tcg_temp_new(); \
+ TCGv mask = tcg_temp_new(); \
+ TCGv zero = tcg_const_tl(0); \
+ PRED; \
+ ADD; \
+ tcg_gen_movi_tl(mask, 1 << insn->slot); \
+ tcg_gen_or_tl(mask, hex_slot_cancelled, mask); \
+ tcg_gen_movcond_tl(TCG_COND_NE, hex_slot_cancelled, LSB, zero, \
+ hex_slot_cancelled, mask); \
+ tcg_temp_free(LSB); \
+ tcg_temp_free(mask); \
+ tcg_temp_free(zero); \
+ } while (0)
+
+#define fWRAP_A2_paddt(GENHLPR, SHORTCODE) \
+ WRAP_padd(fLSBOLD(PuV), tcg_gen_add_tl(RdV, RsV, RtV))
+#define fWRAP_A2_paddf(GENHLPR, SHORTCODE) \
+ WRAP_padd(fLSBOLDNOT(PuV), tcg_gen_add_tl(RdV, RsV, RtV))
+#define fWRAP_A2_paddit(GENHLPR, SHORTCODE) \
+ WRAP_padd(fLSBOLD(PuV), tcg_gen_addi_tl(RdV, RsV, IMMNO(0)))
+#define fWRAP_A2_paddif(GENHLPR, SHORTCODE) \
+ WRAP_padd(fLSBOLDNOT(PuV), tcg_gen_addi_tl(RdV, RsV, IMMNO(0)))
+#define fWRAP_A2_padditnew(GENHLPR, SHORTCODE) \
+ WRAP_padd(fLSBNEW(PuN), tcg_gen_addi_tl(RdV, RsV, IMMNO(0)))
+
+/* Conditional move instructions */
+#define fWRAP_COND_MOVE(VAL, COND) \
+ do { \
+ TCGv LSB = tcg_temp_new(); \
+ TCGv zero = tcg_const_tl(0); \
+ TCGv mask = tcg_temp_new(); \
+ TCGv value = tcg_const_tl(siV); \
+ VAL; \
+ tcg_gen_movcond_tl(COND, RdV, LSB, zero, value, zero); \
+ tcg_gen_movi_tl(mask, 1 << insn->slot); \
+ tcg_gen_movcond_tl(TCG_COND_EQ, mask, LSB, zero, mask, zero); \
+ tcg_gen_or_tl(hex_slot_cancelled, hex_slot_cancelled, mask); \
+ tcg_temp_free(LSB); \
+ tcg_temp_free(zero); \
+ tcg_temp_free(mask); \
+ tcg_temp_free(value); \
+ } while (0)
+
+#define fWRAP_C2_cmoveit(GENHLPR, SHORTCODE) \
+ fWRAP_COND_MOVE(fLSBOLD(PuV), TCG_COND_NE)
+#define fWRAP_C2_cmovenewit(GENHLPR, SHORTCODE) \
+ fWRAP_COND_MOVE(fLSBNEW(PuN), TCG_COND_NE)
+#define fWRAP_C2_cmovenewif(GENHLPR, SHORTCODE) \
+ fWRAP_COND_MOVE(fLSBNEWNOT(PuN), TCG_COND_NE)
+
+/* p0 = tstbit(r0, #5) */
+#define fWRAP_S2_tstbit_i(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ tcg_gen_andi_tl(tmp, RsV, (1 << IMMNO(0))); \
+ gen_8bitsof(PdV, tmp); \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+/* p0 = !tstbit(r0, #5) */
+#define fWRAP_S4_ntstbit_i(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ tcg_gen_andi_tl(tmp, RsV, (1 << IMMNO(0))); \
+ gen_8bitsof(PdV, tmp); \
+ tcg_gen_xori_tl(PdV, PdV, 0xff); \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+/* r0 = setbit(r1, #5) */
+#define fWRAP_S2_setbit_i(GENHLPR, SHORTCODE) \
+ tcg_gen_ori_tl(RdV, RsV, 1 << IMMNO(0))
+
+/* r0 += add(r1, #8) */
+#define fWRAP_M2_accii(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ tcg_gen_add_tl(tmp, RxV, RsV); \
+ tcg_gen_addi_tl(RxV, tmp, IMMNO(0)); \
+ tcg_temp_free(tmp); \
+ } while (0)
+
+/* p0 = bitsclr(r1, #6) */
+#define fWRAP_C2_bitsclri(GENHLPR, SHORTCODE) \
+ do { \
+ TCGv tmp = tcg_temp_new(); \
+ TCGv zero = tcg_const_tl(0); \
+ tcg_gen_andi_tl(tmp, RsV, IMMNO(0)); \
+ gen_compare(TCG_COND_EQ, PdV, tmp, zero); \
+ tcg_temp_free(tmp); \
+ tcg_temp_free(zero); \
+ } while (0)
+
+#define fWRAP_SL2_jumpr31(GENHLPR, SHORTCODE) \
+ gen_write_new_pc(hex_gpr[HEX_REG_LR])
+
+#define fWRAP_SL2_jumpr31_tnew(GENHLPR, SHORTCODE) \
+ gen_cond_jumpr(hex_new_pred_value[0], hex_gpr[HEX_REG_LR])
+
#endif
--
2.7.4
next prev parent reply other threads:[~2020-02-28 17:33 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-02-28 16:42 [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 01/67] Hexagon Maintainers Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 02/67] Hexagon README Taylor Simpson
2020-02-28 16:42 ` [RFC PATCH v2 03/67] Hexagon ELF Machine Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 04/67] Hexagon CPU Scalar Core Definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 05/67] Hexagon register names Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 06/67] Hexagon Disassembler Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 07/67] Hexagon CPU Scalar Core Helpers Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 08/67] Hexagon GDB Stub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 09/67] Hexagon architecture types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 10/67] Hexagon instruction and packet types Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 11/67] Hexagon register fields Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 12/67] Hexagon instruction attributes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 13/67] Hexagon register map Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 14/67] Hexagon instruction/packet decode Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 15/67] Hexagon instruction printing Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 16/67] Hexagon arch import - instruction semantics definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 17/67] Hexagon arch import - macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 18/67] Hexagon arch import - instruction encoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 19/67] Hexagon instruction class definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 20/67] Hexagon instruction utility functions Taylor Simpson
2020-04-09 18:53 ` Brian Cain
2020-04-09 20:22 ` Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 21/67] Hexagon generator phase 1 - C preprocessor for semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 22/67] Hexagon generator phase 2 - qemu_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 23/67] Hexagon generator phase 2 - qemu_wrap_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 24/67] Hexagon generator phase 2 - opcodes_def_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 25/67] Hexagon generator phase 2 - op_attribs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 26/67] Hexagon generator phase 2 - op_regs_generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 27/67] Hexagon generator phase 2 - printinsn-generated.h Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 28/67] Hexagon generator phase 3 - C preprocessor for decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 29/67] Hexagon generater phase 4 - Decode tree Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 30/67] Hexagon opcode data structures Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 31/67] Hexagon macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 32/67] Hexagon macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 33/67] Hexagon instruction classes Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 34/67] Hexagon TCG generation helpers - step 1 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 35/67] Hexagon TCG generation helpers - step 2 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 36/67] Hexagon TCG generation helpers - step 3 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 37/67] Hexagon TCG generation helpers - step 4 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 38/67] Hexagon TCG generation helpers - step 5 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 39/67] Hexagon TCG generation - step 01 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 40/67] Hexagon TCG generation - step 02 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 41/67] Hexagon TCG generation - step 03 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 42/67] Hexagon TCG generation - step 04 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 43/67] Hexagon TCG generation - step 05 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 44/67] Hexagon TCG generation - step 06 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 45/67] Hexagon TCG generation - step 07 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 46/67] Hexagon TCG generation - step 08 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 47/67] Hexagon TCG generation - step 09 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 48/67] Hexagon TCG generation - step 10 Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 49/67] Hexagon TCG generation - step 11 Taylor Simpson
2020-02-28 16:43 ` Taylor Simpson [this message]
2020-02-28 16:43 ` [RFC PATCH v2 51/67] Hexagon translation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 52/67] Hexagon Linux user emulation Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 53/67] Hexagon build infrastructure Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 55/67] Hexagon HVX support in gdbstub Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 56/67] Hexagon HVX import instruction encodings Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 57/67] Hexagon HVX import semantics Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 58/67] Hexagon HVX import macro definitions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 59/67] Hexagon HVX semantics generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 60/67] Hexagon HVX instruction decoding Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 61/67] Hexagon HVX instruction utility functions Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 62/67] Hexagon HVX macros to interface with the generator Taylor Simpson
2020-02-28 16:43 ` [RFC PATCH v2 63/67] Hexagon HVX macros referenced in instruction semantics Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 64/67] Hexagon HVX helper to commit vector stores (masked and scatter/gather) Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 65/67] Hexagon HVX TCG generation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 66/67] Hexagon HVX translation Taylor Simpson
2020-02-28 16:44 ` [RFC PATCH v2 67/67] Hexagon HVX build infrastructure Taylor Simpson
2020-03-25 21:13 ` [RFC PATCH v2 00/67] Hexagon patch series Taylor Simpson
2020-04-30 20:53 ` Taylor Simpson
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