From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Palmer Dabbelt <palmerdabbelt@google.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>, Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH 02/18] hw/riscv: hart: Add a new 'resetvec' property
Date: Sat, 15 Aug 2020 00:40:40 +0800 [thread overview]
Message-ID: <1597423256-14847-3-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1597423256-14847-1-git-send-email-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
RISC-V machines do not instantiate RISC-V CPUs directly, instead
they do that via the hart array. Add a new property for the reset
vector address to allow the value to be passed to the CPU, before
CPU is realized.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
---
hw/riscv/riscv_hart.c | 3 +++
include/hw/riscv/riscv_hart.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index f59fe52..613ea2a 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -31,6 +31,8 @@ static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
+ DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
+ DEFAULT_RSTVEC),
DEFINE_PROP_END_OF_LIST(),
};
@@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
char *cpu_type, Error **errp)
{
object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
+ qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
s->harts[idx].env.mhartid = s->hartid_base + idx;
qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index c75856f..77aa4bc 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState {
uint32_t num_harts;
uint32_t hartid_base;
char *cpu_type;
+ uint64_t resetvec;
RISCVCPU *harts;
} RISCVHartArrayState;
--
2.7.4
next prev parent reply other threads:[~2020-08-14 16:42 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-14 16:40 [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-08-14 16:40 ` [PATCH 01/18] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-08-17 17:49 ` Alistair Francis
2020-08-14 16:40 ` Bin Meng [this message]
2020-08-17 17:49 ` [PATCH 02/18] hw/riscv: hart: " Alistair Francis
2020-08-14 16:40 ` [PATCH 03/18] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-08-17 17:52 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 04/18] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-08-17 19:39 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 05/18] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-08-17 20:51 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 06/18] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-08-17 21:06 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch status data structure Bin Meng
2020-08-15 7:58 ` Philippe Mathieu-Daudé
2020-08-18 16:30 ` Sai Pavan Boddu
2020-08-21 10:09 ` Sai Pavan Boddu
2020-08-21 10:08 ` Bin Meng
2020-08-24 4:13 ` Sai Pavan Boddu
2020-08-14 16:40 ` [PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit Bin Meng
2020-08-15 8:38 ` Philippe Mathieu-Daudé
2020-08-16 8:54 ` Bin Meng
2020-08-14 16:40 ` [PATCH 09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible Bin Meng
2020-08-15 7:51 ` Philippe Mathieu-Daudé
2020-08-16 8:50 ` Bin Meng
2020-08-16 11:06 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 10/18] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-08-15 8:51 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-08-15 8:55 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 12/18] hw/dma: Add Microchip PolarFire Soc DMA controller emulation Bin Meng
2020-08-14 16:40 ` [PATCH 13/18] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-08-15 9:00 ` Philippe Mathieu-Daudé
2020-08-16 8:57 ` Bin Meng
2020-08-16 11:08 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-08-15 9:06 ` Philippe Mathieu-Daudé
2020-08-16 8:29 ` Bin Meng
2020-08-16 11:14 ` Philippe Mathieu-Daudé
2020-08-16 12:08 ` Nathan Rossi
2020-08-16 13:42 ` Bin Meng
2020-08-16 16:31 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-08-21 18:46 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-08-21 18:47 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-08-25 18:33 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing Bin Meng
2020-08-21 18:51 ` Alistair Francis
2020-08-14 17:44 ` [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Anup Patel
2020-08-17 10:30 ` Bin Meng
2020-08-17 15:44 ` via
2020-08-17 19:28 ` Alistair Francis
2020-08-17 19:53 ` via
2020-08-18 6:17 ` Anup Patel
2020-08-18 13:09 ` via
2020-08-18 13:55 ` Anup Patel
2020-08-19 1:34 ` Bin Meng
2020-08-19 10:13 ` via
2020-08-21 18:23 ` Alistair Francis
2020-08-14 18:10 ` no-reply
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