Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support

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To: <alistair23@gmail.com>
Cc: <bmeng.cn@gmail.com>, <anup@brainfault.org>,
	<Alistair.Francis@wdc.com>, <kbastian@mail.uni-paderborn.de>,
	<palmerdabbelt@google.com>, <sagark@eecs.berkeley.edu>,
	<qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>,
	 <peter.maydell@linaro.org>, <alistair@alistair23.me>,
	<qemu-block@nongnu.org>, <jasowang@redhat.com>,
	<bin.meng@windriver.com>, <pbonzini@redhat.com>,
	<palmer@dabbelt.com>, <qemu-arm@nongnu.org>,
	<marcandre.lureau@redhat.com>, <edgar.iglesias@gmail.com>,
	<philmd@redhat.com>
Subject: Re: [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support
Date: Mon, 17 Aug 2020 19:53:46 +0000	[thread overview]
Message-ID: <d3f61c2c-a489-887e-0143-4d9a1e66e6f2@microchip.com> (raw)
In-Reply-To: <CAKmqyKM3nm0rhxgDvWKWfO+4b23ZLSkHW2TzmcVZ_ZFy4L7MRg@mail.gmail.com>

On 8/17/20 8:28 PM, Alistair Francis wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On Mon, Aug 17, 2020 at 11:12 AM via <qemu-devel@nongnu.org> wrote:
>> Hi Anup,
>>
>> On 8/17/20 11:30 AM, Bin Meng wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> Hi Anup,
>>>
>>> On Sat, Aug 15, 2020 at 1:44 AM Anup Patel <anup@brainfault.org> wrote:
>>>> On Fri, Aug 14, 2020 at 10:12 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>>>> From: Bin Meng <bin.meng@windriver.com>
>>>>>
>>>>> This adds support for Microchip PolarFire SoC Icicle Kit board.
>>>>> The Icicle Kit board integrates a PolarFire SoC, with one SiFive's
>>>>> E51 plus four U54 cores and many on-chip peripherals and an FPGA.
>>>> Nice Work !!! This is very helpful.
>>> Thanks!
>>>
>>>> The Microchip HSS is quite convoluted. It has:
>>>> 1. DDR Init
>>>> 2. Boot device support
>>>> 3. SBI support using OpenSBI as library
>>>> 4. Simple TEE support
>>>>
>>>> I think point 1) and 2) above should be part of U-Boot SPL.
>>>> The point 3) can be OpenSBI FW_DYNAMIC.
>>>>
>>>> Lastly,for point 4), we are working on a new OpenSBI feature using
>>>> which we can run independent Secure OS and Non-Secure OS using
>>>> U-Boot_SPL+OpenSBI (for both SiFive Unleashed and Microchip
>>>> PolarFire).
>>>>
>>>> Do you have plans for adding U-Boot SPL support for this board ??
>>> + Cyril Jean from Microchip
>>>
>>> I will have to leave this question to Cyril to comment.
>>>
>> I currently do not have a plan to support U-Boot SPL. The idea of the
>> HSS is to contain all the silicon specific initialization and
>> configuration code within the HSS before jumping to U-Boot S-mode. I
>> would rather keep all this within the HSS for the time being. I would
>> wait until we reach production silicon before attempting to move this to
>> U-Boot SPL as the HSS is likely to contain some opaque silicon related
>> changes for another while.
> That is unfortunate, a lot of work has gone into making the boot flow
> simple and easy to use.
>
> QEMU now includes OpenSBI by default to make it easy for users to boot
> Linux. The Icicle Kit board is now the most difficult QEMU board to
> boot Linux on. Not to mention it makes it hard to impossible to
> support it in standard tool flows such as meta-riscv.
>
> Alistair

If it is such a problem we can add a U-Boot SPL stage and the HSS can be 
treated as standard SoC ROM code.

Cyril.