Re: [PATCH 03/18] target/riscv: cpu: Set reset vector based on the configured property value

[Alistair Francis <alistair23@gmail.com>]

On Fri, Aug 14, 2020 at 9:45 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> Now that we have the newly introduced 'resetvec' property in the
> RISC-V CPU and HART, instead of hard-coding the reset vector addr
> in the CPU's instance_init(), move that to riscv_cpu_realize()
> based on the configured property value from the RISC-V machines.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>
>  hw/riscv/opentitan.c | 1 +
>  hw/riscv/sifive_e.c  | 1 +
>  hw/riscv/sifive_u.c  | 2 ++
>  target/riscv/cpu.c   | 7 ++-----
>  4 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index a8f0039..b0a4eae 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -111,6 +111,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>                              &error_abort);
>      object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
>                              &error_abort);
> +    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort);
>      sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
>
>      /* Boot ROM */
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index c8b0604..c84d407 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -177,6 +177,7 @@ static void sifive_e_soc_init(Object *obj)
>      object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);
>      object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
>                              &error_abort);
> +    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort);
>      object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio,
>                              TYPE_SIFIVE_GPIO);
>  }
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 18301e6..e256da2 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -611,6 +611,7 @@ static void sifive_u_soc_instance_init(Object *obj)
>      qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
>      qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
>      qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
> +    qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
>
>      object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
>      qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1);
> @@ -620,6 +621,7 @@ static void sifive_u_soc_instance_init(Object *obj)
>      qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1);
>      qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1);
>      qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU);
> +    qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
>
>      object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI);
>      object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP);
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 8067a26..bd41286 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -128,7 +128,6 @@ static void riscv_any_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
>      set_priv_version(env, PRIV_VERSION_1_11_0);
> -    set_resetvec(env, DEFAULT_RSTVEC);
>  }
>
>  static void riscv_base_cpu_init(Object *obj)
> @@ -136,7 +135,6 @@ static void riscv_base_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      /* We set this in the realise function */
>      set_misa(env, 0);
> -    set_resetvec(env, DEFAULT_RSTVEC);
>  }
>
>  static void rvxx_sifive_u_cpu_init(Object *obj)
> @@ -144,7 +142,6 @@ static void rvxx_sifive_u_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
> -    set_resetvec(env, 0x1004);
>  }
>
>  static void rvxx_sifive_e_cpu_init(Object *obj)
> @@ -152,7 +149,6 @@ static void rvxx_sifive_e_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
> -    set_resetvec(env, 0x1004);
>      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>  }
>
> @@ -163,7 +159,6 @@ static void rv32_ibex_cpu_init(Object *obj)
>      CPURISCVState *env = &RISCV_CPU(obj)->env;
>      set_misa(env, RV32 | RVI | RVM | RVC | RVU);
>      set_priv_version(env, PRIV_VERSION_1_10_0);
> -    set_resetvec(env, 0x8090);
>      qdev_prop_set_bit(DEVICE(obj), "mmu", false);
>  }
>
> @@ -373,6 +368,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>          set_feature(env, RISCV_FEATURE_PMP);
>      }
>
> +    set_resetvec(env, cpu->cfg.resetvec);
> +
>      /* If misa isn't set (rv32 and rv64 machines) set it here */
>      if (!env->misa) {
>          /* Do some ISA extension error checking */
> --
> 2.7.4
>
>