From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
To: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
Cc: "Bin Meng" <bin.meng@windriver.com>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>,
"qemu-block@nongnu.org" <qemu-block@nongnu.org>,
"Sagar Karandikar" <sagark@eecs.berkeley.edu>,
"Bastian Koppelmann" <kbastian@mail.uni-paderborn.de>,
"Palmer Dabbelt" <palmerdabbelt@google.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
saipava@xilinx.com, "Alistair Francis" <Alistair.Francis@wdc.com>,
"Bin Meng" <bmeng.cn@gmail.com>
Subject: Re: [PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch status data structure
Date: Fri, 21 Aug 2020 15:39:40 +0530 [thread overview]
Message-ID: <20200821100940.GA30457@xhdsaipava40.xilinx.com> (raw)
In-Reply-To: <BY5PR02MB67720168B25F53370840545BCA5C0@BY5PR02MB6772.namprd02.prod.outlook.com>
Hi Philippe,
First two patch of SD look good. Tested them over zynqmp and versal
platforms.
Thanks,
Sai Pavan
On Tue, Aug 18, 2020 at 04:30:15PM +0000, Sai Pavan Boddu wrote:
> Thanks Philippe,
>
> I would test this and get back.
>
> Regards,
> Sai Pavan
>
> > -----Original Message-----
> > From: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> On
> > Behalf Of Philippe Mathieu-Daudé
> > Sent: Saturday, August 15, 2020 1:29 PM
> > To: Bin Meng <bmeng.cn@gmail.com>; Alistair Francis
> > <Alistair.Francis@wdc.com>; Bastian Koppelmann <kbastian@mail.uni-
> > paderborn.de>; Palmer Dabbelt <palmerdabbelt@google.com>; Sagar
> > Karandikar <sagark@eecs.berkeley.edu>; qemu-devel@nongnu.org; qemu-
> > riscv@nongnu.org; Sai Pavan Boddu <saipava@xilinx.com>
> > Cc: Bin Meng <bin.meng@windriver.com>; qemu-block@nongnu.org
> > Subject: Re: [PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch
> > status data structure
> >
> > +Sai Pavan
> >
> > On 8/14/20 6:40 PM, Bin Meng wrote:
> > > From: Bin Meng <bin.meng@windriver.com>
> > >
> > > At present the function switch status data structure bit [399:376] are
> > > wrongly pupulated. These 3 bytes encode function switch status for the
> > > 6 function groups, with 4 bits per group, starting from function group
> > > 6 at bit 399, then followed by function group 5 at bit 395, and so on.
> > >
> > > However the codes mistakenly fills in the function group 1 status at
> > > bit 399. This fixes the code logic.
> > >
> >
> > Fixes: a1bb27b1e9 ("SD card emulation (initial implementation)")
> >
> > > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > > ---
> > >
> > > hw/sd/sd.c | 6 +++++-
> > > 1 file changed, 5 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/hw/sd/sd.c b/hw/sd/sd.c
> > > index fad9cf1..51f5900 100644
> > > --- a/hw/sd/sd.c
> > > +++ b/hw/sd/sd.c
> > > @@ -806,11 +806,15 @@ static void sd_function_switch(SDState *sd,
> > uint32_t arg)
> > > sd->data[11] = 0x43;
> > > sd->data[12] = 0x80; /* Supported group 1 functions */
> > > sd->data[13] = 0x03;
> > > +
> > > + sd->data[14] = 0;
> > > + sd->data[15] = 0;
> > > + sd->data[16] = 0;
> >
> > Pointless zero initialization.
> >
> > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> >
> > I'll wait until next week in case Sai Pavan wants to test this patch (I don't have
> > access to the Xilinx images anymore) then I'll queue this via my sd-next tree.
> >
> > Regards,
> >
> > Phil.
> >
> > > for (i = 0; i < 6; i ++) {
> > > new_func = (arg >> (i * 4)) & 0x0f;
> > > if (mode && new_func != 0x0f)
> > > sd->function_group[i] = new_func;
> > > - sd->data[14 + (i >> 1)] = new_func << ((i * 4) & 4);
> > > + sd->data[16 - (i >> 1)] |= new_func << ((i % 2) * 4);
> > > }
> > > memset(&sd->data[17], 0, 47);
> > > stw_be_p(sd->data + 64, sd_crc16(sd->data, 64));
> > >
>
next prev parent reply other threads:[~2020-08-21 10:20 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-14 16:40 [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-08-14 16:40 ` [PATCH 01/18] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-08-17 17:49 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 02/18] hw/riscv: hart: " Bin Meng
2020-08-17 17:49 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 03/18] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-08-17 17:52 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 04/18] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-08-17 19:39 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 05/18] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-08-17 20:51 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 06/18] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-08-17 21:06 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch status data structure Bin Meng
2020-08-15 7:58 ` Philippe Mathieu-Daudé
2020-08-18 16:30 ` Sai Pavan Boddu
2020-08-21 10:09 ` Sai Pavan Boddu [this message]
2020-08-21 10:08 ` Bin Meng
2020-08-24 4:13 ` Sai Pavan Boddu
2020-08-14 16:40 ` [PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit Bin Meng
2020-08-15 8:38 ` Philippe Mathieu-Daudé
2020-08-16 8:54 ` Bin Meng
2020-08-14 16:40 ` [PATCH 09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible Bin Meng
2020-08-15 7:51 ` Philippe Mathieu-Daudé
2020-08-16 8:50 ` Bin Meng
2020-08-16 11:06 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 10/18] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-08-15 8:51 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-08-15 8:55 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 12/18] hw/dma: Add Microchip PolarFire Soc DMA controller emulation Bin Meng
2020-08-14 16:40 ` [PATCH 13/18] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-08-15 9:00 ` Philippe Mathieu-Daudé
2020-08-16 8:57 ` Bin Meng
2020-08-16 11:08 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-08-15 9:06 ` Philippe Mathieu-Daudé
2020-08-16 8:29 ` Bin Meng
2020-08-16 11:14 ` Philippe Mathieu-Daudé
2020-08-16 12:08 ` Nathan Rossi
2020-08-16 13:42 ` Bin Meng
2020-08-16 16:31 ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-08-21 18:46 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-08-21 18:47 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-08-25 18:33 ` Alistair Francis
2020-08-14 16:40 ` [PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing Bin Meng
2020-08-21 18:51 ` Alistair Francis
2020-08-14 17:44 ` [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Anup Patel
2020-08-17 10:30 ` Bin Meng
2020-08-17 15:44 ` via
2020-08-17 19:28 ` Alistair Francis
2020-08-17 19:53 ` via
2020-08-18 6:17 ` Anup Patel
2020-08-18 13:09 ` via
2020-08-18 13:55 ` Anup Patel
2020-08-19 1:34 ` Bin Meng
2020-08-19 10:13 ` via
2020-08-21 18:23 ` Alistair Francis
2020-08-14 18:10 ` no-reply
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