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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: Bin Meng <bmeng.cn@gmail.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Palmer Dabbelt <palmerdabbelt@google.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>, qemu-block@nongnu.org
Subject: Re: [PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit
Date: Sat, 15 Aug 2020 10:38:24 +0200	[thread overview]
Message-ID: <3b8ef426-77ce-d3b2-594b-045cae5ec94f@amsat.org> (raw)
In-Reply-To: <1597423256-14847-9-git-send-email-bmeng.cn@gmail.com>

On 8/14/20 6:40 PM, Bin Meng wrote:
> From: Bin Meng <bin.meng@windriver.com>
> 
> Per the SD spec, Standard Capacity SD Memory Card (SDSC) supports
> capacity up to and including 2 GiB.
> 

Fixes: 2d7adea4fe ("hw/sd: Support SDHC size cards")

> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
> 
>  hw/sd/sd.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/sd/sd.c b/hw/sd/sd.c
> index 51f5900..5e7fc3f 100644
> --- a/hw/sd/sd.c
> +++ b/hw/sd/sd.c
> @@ -313,7 +313,7 @@ static void sd_ocr_powerup(void *opaque)
>      /* card power-up OK */
>      sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_POWER_UP, 1);
>  
> -    if (sd->size > 1 * GiB) {
> +    if (sd->size > 2 * GiB) {

But you need to fix sd_set_csd() too, else this is incomplete.

Thanks,

Phil.

>          sd->ocr = FIELD_DP32(sd->ocr, OCR, CARD_CAPACITY, 1);
>      }
>  }
> 



  reply	other threads:[~2020-08-15 15:59 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-14 16:40 [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Bin Meng
2020-08-14 16:40 ` [PATCH 01/18] target/riscv: cpu: Add a new 'resetvec' property Bin Meng
2020-08-17 17:49   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 02/18] hw/riscv: hart: " Bin Meng
2020-08-17 17:49   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 03/18] target/riscv: cpu: Set reset vector based on the configured property value Bin Meng
2020-08-17 17:52   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 04/18] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Bin Meng
2020-08-17 19:39   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 05/18] hw/char: Add Microchip PolarFire SoC MMUART emulation Bin Meng
2020-08-17 20:51   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 06/18] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Bin Meng
2020-08-17 21:06   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 07/18] hw/sd: sd: Fix incorrect populated function switch status data structure Bin Meng
2020-08-15  7:58   ` Philippe Mathieu-Daudé
2020-08-18 16:30     ` Sai Pavan Boddu
2020-08-21 10:09       ` Sai Pavan Boddu
2020-08-21 10:08         ` Bin Meng
2020-08-24  4:13           ` Sai Pavan Boddu
2020-08-14 16:40 ` [PATCH 08/18] hw/sd: sd: Correctly set the high capacity bit Bin Meng
2020-08-15  8:38   ` Philippe Mathieu-Daudé [this message]
2020-08-16  8:54     ` Bin Meng
2020-08-14 16:40 ` [PATCH 09/18] hw/sd: sdhci: Make sdhci_poweron_reset() internal visible Bin Meng
2020-08-15  7:51   ` Philippe Mathieu-Daudé
2020-08-16  8:50     ` Bin Meng
2020-08-16 11:06       ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 10/18] hw/sd: Add Cadence SDHCI emulation Bin Meng
2020-08-15  8:51   ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 11/18] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Bin Meng
2020-08-15  8:55   ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 12/18] hw/dma: Add Microchip PolarFire Soc DMA controller emulation Bin Meng
2020-08-14 16:40 ` [PATCH 13/18] hw/riscv: microchip_pfsoc: Connect a DMA controller Bin Meng
2020-08-15  9:00   ` Philippe Mathieu-Daudé
2020-08-16  8:57     ` Bin Meng
2020-08-16 11:08       ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 14/18] hw/net: cadence_gem: Add a new 'phy-addr' property Bin Meng
2020-08-15  9:06   ` Philippe Mathieu-Daudé
2020-08-16  8:29     ` Bin Meng
2020-08-16 11:14       ` Philippe Mathieu-Daudé
2020-08-16 12:08       ` Nathan Rossi
2020-08-16 13:42         ` Bin Meng
2020-08-16 16:31           ` Philippe Mathieu-Daudé
2020-08-14 16:40 ` [PATCH 15/18] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Bin Meng
2020-08-21 18:46   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 16/18] hw/riscv: microchip_pfsoc: Hook GPIO controllers Bin Meng
2020-08-21 18:47   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 17/18] hw/riscv: clint: Avoid using hard-coded timebase frequency Bin Meng
2020-08-25 18:33   ` Alistair Francis
2020-08-14 16:40 ` [PATCH 18/18] hw/riscv: microchip_pfsoc: Document the software used for testing Bin Meng
2020-08-21 18:51   ` Alistair Francis
2020-08-14 17:44 ` [PATCH 00/18] hw/riscv: Add Microchip PolarFire SoC Icicle Kit board support Anup Patel
2020-08-17 10:30   ` Bin Meng
2020-08-17 15:44     ` via
2020-08-17 19:28       ` Alistair Francis
2020-08-17 19:53         ` via
2020-08-18  6:17           ` Anup Patel
2020-08-18 13:09             ` via
2020-08-18 13:55               ` Anup Patel
2020-08-19  1:34                 ` Bin Meng
2020-08-19 10:13                   ` via
2020-08-21 18:23                     ` Alistair Francis
2020-08-14 18:10 ` no-reply

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