[PATCH v4 11/21] target/loongarch: Add floating point comparison instruction translation

[Song Gao <gaosong@loongson.cn>]

This patch implement floating point comparison instruction translation.

This includes:
- FCMP.cond.{S/D}

Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: XiaoJuan Yang <yangxiaojuan@loongson.cn>
---
 target/loongarch/fpu_helper.c            | 110 ++++++++++++
 target/loongarch/helper.h                |   9 +
 target/loongarch/insn_trans/trans_fcmp.c | 279 +++++++++++++++++++++++++++++++
 target/loongarch/insns.decode            |  10 ++
 target/loongarch/translate.c             |   1 +
 target/loongarch/translate.h             |   5 +
 6 files changed, 414 insertions(+)
 create mode 100644 target/loongarch/insn_trans/trans_fcmp.c

diff --git a/target/loongarch/fpu_helper.c b/target/loongarch/fpu_helper.c
index c3bee57..bad7238 100644
--- a/target/loongarch/fpu_helper.c
+++ b/target/loongarch/fpu_helper.c
@@ -436,3 +436,113 @@ uint64_t helper_fmuladd_d(CPULoongArchState *env, uint64_t fj,
     update_fcsr0(env, GETPC());
     return fd;
 }
+
+/* fcmp_cXXX_s */
+uint64_t helper_fcmp_c_s(CPULoongArchState *env, uint64_t fj,
+                         uint64_t fk, uint32_t flags)
+{
+    uint32_t t0, t1;
+    uint64_t cmp = 0;
+    t0 = (uint32_t)fj;
+    t1 = (uint32_t)fk;
+
+    if (flags) {
+        if (flags & FCMP_LT) {
+            cmp |= float32_lt_quiet(t0, t1, &env->fp_status);
+        }
+        if (flags & FCMP_EQ) {
+            cmp |= float32_eq_quiet(t0, t1, &env->fp_status);
+        }
+        if (flags & FCMP_GT) {
+            cmp |= float32_lt_quiet(t1, t0, &env->fp_status);
+        }
+        if (flags & FCMP_UN) {
+            cmp |= float32_unordered_quiet(t1, t0, &env->fp_status);
+        }
+    } else {
+        cmp = (float32_unordered_quiet(t1, t0, &env->fp_status), 0);
+    }
+    update_fcsr0(env, GETPC());
+    return cmp;
+}
+
+/* fcmp_sXXX_s */
+uint64_t helper_fcmp_s_s(CPULoongArchState *env, uint64_t fj,
+                         uint64_t fk, uint32_t flags)
+{
+    uint32_t t0, t1;
+    uint64_t cmp = 0;
+    t0 = (uint32_t)fj;
+    t1 = (uint32_t)fk;
+
+    if (flags) {
+        if (flags & FCMP_LT) {
+            cmp |= float32_lt(t0, t1, &env->fp_status);
+        }
+        if (flags & FCMP_EQ) {
+            cmp |= float32_eq(t0, t1, &env->fp_status);
+        }
+        if (flags & FCMP_GT) {
+            cmp |= float32_lt(t1, t0, &env->fp_status);
+        }
+        if (flags & FCMP_UN) {
+            cmp |= float32_unordered(t1, t0, &env->fp_status);
+        }
+    } else {
+        cmp = (float32_unordered(t1, t0, &env->fp_status), 0);
+    }
+    update_fcsr0(env, GETPC());
+    return cmp;
+}
+
+/* fcmp_cXXX_d */
+uint64_t helper_fcmp_c_d(CPULoongArchState *env, uint64_t fj,
+                         uint64_t fk, uint32_t flags)
+{
+    uint64_t cmp = 0;
+
+    if (flags) {
+        if (flags & FCMP_LT) {
+            cmp |= float64_lt_quiet(fj, fk, &env->fp_status);
+        }
+        if (flags & FCMP_EQ) {
+            cmp |= float64_eq_quiet(fj, fk, &env->fp_status);
+        }
+        if (flags & FCMP_GT) {
+            cmp |= float64_lt_quiet(fk, fj, &env->fp_status);
+        }
+        if (flags & FCMP_UN) {
+            cmp |= float64_unordered_quiet(fk, fj, &env->fp_status);
+        }
+    } else {
+        cmp = (float64_unordered_quiet(fk, fj, &env->fp_status), 0);
+    }
+    update_fcsr0(env, GETPC());
+    return cmp;
+}
+
+/* fcmp_sXXX_d */
+uint64_t helper_fcmp_s_d(CPULoongArchState *env, uint64_t fj,
+                         uint64_t fk, uint32_t flags)
+{
+    uint64_t cmp = 0;
+
+    if (flags) {
+        if (flags & FCMP_LT) {
+            cmp |= float64_lt(fj, fk, &env->fp_status);
+        }
+        if (flags & FCMP_EQ) {
+            cmp |= float64_eq(fj, fk, &env->fp_status);
+        }
+        if (flags & FCMP_GT) {
+            cmp |= float64_lt(fk, fj, &env->fp_status);
+        }
+        if (flags & FCMP_UN) {
+            cmp |= float64_unordered(fk, fj, &env->fp_status);
+        }
+    } else {
+        cmp = (float64_unordered(fk, fj, &env->fp_status), 0);
+    }
+    update_fcsr0(env, GETPC());
+    return cmp;
+}
diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
index 62c262e..5f6e60d 100644
--- a/target/loongarch/helper.h
+++ b/target/loongarch/helper.h
@@ -60,3 +60,12 @@ DEF_HELPER_2(frecip_d, i64, env, i64)
 
 DEF_HELPER_FLAGS_2(fclass_s, TCG_CALL_NO_RWG_SE, i64, env, i64)
 DEF_HELPER_FLAGS_2(fclass_d, TCG_CALL_NO_RWG_SE, i64, env, i64)
+
+/* fcmp.cXXX.s */
+DEF_HELPER_4(fcmp_c_s, i64, env, i64, i64, i32)
+/* fcmp.sXXX.s */
+DEF_HELPER_4(fcmp_s_s, i64, env, i64, i64, i32)
+/* fcmp.cXXX.d */
+DEF_HELPER_4(fcmp_c_d, i64, env, i64, i64, i32)
+/* fcmp.sXXX.d */
+DEF_HELPER_4(fcmp_s_d, i64, env, i64, i64, i32)
diff --git a/target/loongarch/insn_trans/trans_fcmp.c b/target/loongarch/insn_trans/trans_fcmp.c
new file mode 100644
index 0000000..e9d7c3b
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_fcmp.c
@@ -0,0 +1,279 @@
+/*
+ * LoongArch translate functions
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)
+{
+    TCGv var = tcg_temp_new();
+    TCGv_i32 flags = NULL;
+
+    switch (a->fcond) {
+    /* caf */
+    case  0:
+        flags = tcg_constant_i32(0);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* saf */
+    case 1:
+        flags = tcg_constant_i32(0);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* clt */
+    case 2:
+        flags = tcg_constant_i32(FCMP_LT);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* slt */
+    case 3:
+        flags = tcg_constant_i32(FCMP_LT);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* ceq */
+    case 4:
+        flags = tcg_constant_i32(FCMP_EQ);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* seq */
+    case 5:
+        flags = tcg_constant_i32(FCMP_EQ);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* cle */
+    case 6:
+        flags = tcg_constant_i32(FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* sle */
+    case 7:
+        flags = tcg_constant_i32(FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* cun */
+    case 8:
+        flags = tcg_constant_i32(FCMP_UN);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* sun */
+    case 9:
+        flags = tcg_constant_i32(FCMP_UN);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* cult */
+    case 10:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_LT);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* sult */
+    case 11:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_LT);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* cueq */
+    case 12:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_EQ);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* sueq */
+    case 13:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_EQ);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* cule */
+    case 14:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* sule */
+    case 15:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* cne */
+    case 16:
+        flags = tcg_constant_i32(FCMP_GT | FCMP_LT);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* sne */
+    case 17:
+        flags = tcg_constant_i32(FCMP_GT | FCMP_LT);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* cor */
+    case 20:
+        flags = tcg_constant_i32(FCMP_GT | FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* sor */
+    case 21:
+        flags = tcg_constant_i32(FCMP_GT | FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* cune */
+    case 24:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_GT | FCMP_LT);
+        gen_helper_fcmp_c_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    /* sune */
+    case 25:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_GT | FCMP_LT);
+        gen_helper_fcmp_s_s(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    default:
+        abort();
+    }
+
+    tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
+    tcg_temp_free(var);
+    return true;
+}
+
+static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)
+{
+    TCGv var = tcg_temp_new();
+    TCGv_i32 flags = NULL;
+
+    switch (a->fcond) {
+    case 0:
+        flags = tcg_constant_i32(0);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 1:
+        flags = tcg_constant_i32(0);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 2:
+        flags = tcg_constant_i32(FCMP_LT);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 3:
+        flags = tcg_constant_i32(FCMP_LT);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 4:
+        flags = tcg_constant_i32(FCMP_EQ);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 5:
+        flags = tcg_constant_i32(FCMP_EQ);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 6:
+        flags = tcg_constant_i32(FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 7:
+        flags = tcg_constant_i32(FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 8:
+        flags = tcg_constant_i32(FCMP_UN);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 9:
+        flags = tcg_constant_i32(FCMP_UN);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 10:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_LT);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 11:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_LT);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 12:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_EQ);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 13:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_EQ);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 14:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 15:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 16:
+        flags = tcg_constant_i32(FCMP_GT | FCMP_LT);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 17:
+        flags = tcg_constant_i32(FCMP_GT | FCMP_LT);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 20:
+        flags = tcg_constant_i32(FCMP_GT | FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 21:
+        flags = tcg_constant_i32(FCMP_GT | FCMP_LT | FCMP_EQ);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 24:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_GT | FCMP_LT);
+        gen_helper_fcmp_c_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    case 25:
+        flags = tcg_constant_i32(FCMP_UN | FCMP_GT | FCMP_LT);
+        gen_helper_fcmp_s_d(var, cpu_env, cpu_fpr[a->fj],
+                            cpu_fpr[a->fk], flags);
+        break;
+    default:
+        abort();
+    }
+
+    tcg_gen_st8_tl(var, cpu_env, offsetof(CPULoongArchState, cf[a->cd & 0x7]));
+    tcg_temp_free(var);
+    return true;
+}
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 9e6a727..8aadcfd 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -32,6 +32,8 @@
 %fj      5:5
 %fk      10:5
 %fa      15:5
+%cd      0:3
+%fcond   15:5
 
 #
 # Argument sets
@@ -56,6 +58,7 @@
 &fmt_fdfjfk         fd fj fk
 &fmt_fdfjfkfa       fd fj fk fa
 &fmt_fdfj           fd fj
+&fmt_cdfjfkfcond    cd fj fk fcond
 
 #
 # Formats
@@ -80,6 +83,7 @@
 @fmt_fdfjfk          .... ........ ..... ..... ..... .....    &fmt_fdfjfk         %fd %fj %fk
 @fmt_fdfjfkfa        .... ........ ..... ..... ..... .....    &fmt_fdfjfkfa       %fd %fj %fk %fa
 @fmt_fdfj            .... ........ ..... ..... ..... .....    &fmt_fdfj           %fd %fj
+@fmt_cdfjfkfcond     .... ........ ..... ..... ..... .. ...   &fmt_cdfjfkfcond    %cd %fj %fk %fcond
 
 #
 # Fixed point arithmetic operation instruction
@@ -341,3 +345,9 @@ fcopysign_s      0000 00010001 00101 ..... ..... .....    @fmt_fdfjfk
 fcopysign_d      0000 00010001 00110 ..... ..... .....    @fmt_fdfjfk
 fclass_s         0000 00010001 01000 01101 ..... .....    @fmt_fdfj
 fclass_d         0000 00010001 01000 01110 ..... .....    @fmt_fdfj
+
+#
+# Floating point compare instruction
+#
+fcmp_cond_s      0000 11000001 ..... ..... ..... 00 ...   @fmt_cdfjfkfcond
+fcmp_cond_d      0000 11000010 ..... ..... ..... 00 ...   @fmt_cdfjfkfcond
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index d3e6f8a..be99fb7 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -206,6 +206,7 @@ static bool gen_f2(DisasContext *ctx, arg_fmt_fdfj *a,
 #include "insn_trans/trans_atomic.c"
 #include "insn_trans/trans_extra.c"
 #include "insn_trans/trans_farith.c"
+#include "insn_trans/trans_fcmp.c"
 
 static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
 {
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index 99ab329..16e570c 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -11,6 +11,11 @@
 
 #include "exec/translator.h"
 
+#define FCMP_LT   0x0001  /* fp0 < fp1 */
+#define FCMP_EQ   0x0010  /* fp0 = fp1 */
+#define FCMP_GT   0x0100  /* fp1 < fp0 */
+#define FCMP_UN   0x1000  /* unordered */
+
 #define TRANS(NAME, FUNC, ...) \
     static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
     { return FUNC(ctx, a, __VA_ARGS__); }
-- 
1.8.3.1