From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, yangxiaojuan@loongson.cn,
david@redhat.com, bin.meng@windriver.com,
mark.cave-ayland@ilande.co.uk, aleksandar.rikalo@syrmia.com,
jcmvbkbc@gmail.com, tsimpson@quicinc.com,
alistair.francis@wdc.com, edgar.iglesias@gmail.com,
chenhuacai@gmail.com, philmd@redhat.com, atar4qemu@gmail.com,
thuth@redhat.com, ehabkost@redhat.com,
richard.henderson@linaro.org, groug@kaod.org,
maobibo@loongson.cn, mrolnik@gmail.com, shorne@gmail.com,
alex.bennee@linaro.org, david@gibson.dropbear.id.au,
kbastian@mail.uni-paderborn.de, crwulff@gmail.com,
laurent@vivier.eu, palmer@dabbelt.com, pbonzini@redhat.com,
aurelien@aurel32.net
Subject: [PATCH v4 05/21] target/loongarch: Add fixed point shift instruction translation
Date: Thu, 2 Sep 2021 20:40:51 +0800 [thread overview]
Message-ID: <1630586467-22463-6-git-send-email-gaosong@loongson.cn> (raw)
In-Reply-To: <1630586467-22463-1-git-send-email-gaosong@loongson.cn>
This patch implement fixed point shift instruction translation.
This includes:
- SLL.W, SRL.W, SRA.W, ROTR.W
- SLLI.W, SRLI.W, SRAI.W, ROTRI.W
- SLL.D, SRL.D, SRA.D, ROTR.D
- SLLI.D, SRLI.D, SRAI.D, ROTRI.D
Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: XiaoJuan Yang <yangxiaojuan@loongson.cn>
---
target/loongarch/insn_trans/trans_shift.c | 154 ++++++++++++++++++++++++++++++
target/loongarch/insns.decode | 26 +++++
target/loongarch/translate.c | 1 +
3 files changed, 181 insertions(+)
create mode 100644 target/loongarch/insn_trans/trans_shift.c
diff --git a/target/loongarch/insn_trans/trans_shift.c b/target/loongarch/insn_trans/trans_shift.c
new file mode 100644
index 0000000..5fa1162
--- /dev/null
+++ b/target/loongarch/insn_trans/trans_shift.c
@@ -0,0 +1,154 @@
+/*
+ * LoongArch translate functions
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+static bool gen_r2_ui5(DisasContext *ctx, arg_slli_w *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ ctx->dst_ext = EXT_SIGN;
+ TCGv dest = gpr_dst(ctx, a->rd);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
+ TCGv src2 = tcg_constant_tl(a->ui5);
+
+ TCGv t0 = temp_new(ctx);
+
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+ func(dest, src1, t0);
+ gen_set_gpr(ctx, a->rd, dest);
+
+ return true;
+}
+
+static bool gen_r2_ui6(DisasContext *ctx, arg_slli_d *a,
+ void(*func)(TCGv, TCGv, TCGv))
+{
+ TCGv dest = gpr_dst(ctx, a->rd);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
+ TCGv src2 = tcg_constant_tl(a->ui6);
+
+ TCGv t0 = temp_new(ctx);
+
+ tcg_gen_andi_tl(t0, src2, 0x7f);
+ func(dest, src1, t0);
+
+ return true;
+}
+
+static void gen_sll_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+ tcg_gen_shl_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_srl_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+ tcg_gen_shr_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_sra_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+ tcg_gen_sar_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_sll_d(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x3f);
+ tcg_gen_shl_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_srl_d(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x3f);
+ tcg_gen_shr_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_sra_d(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x3f);
+ tcg_gen_sar_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_rotr_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv t0 = tcg_temp_new();
+
+ tcg_gen_andi_tl(t0, src2, 0x1f);
+
+ tcg_gen_trunc_tl_i32(t1, src1);
+ tcg_gen_trunc_tl_i32(t2, t0);
+
+ tcg_gen_rotr_i32(t1, t1, t2);
+ tcg_gen_ext_i32_tl(dest, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free(t0);
+}
+
+static void gen_rotr_d(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv t0 = tcg_temp_new();
+ tcg_gen_andi_tl(t0, src2, 0x3f);
+ tcg_gen_rotr_tl(dest, src1, t0);
+ tcg_temp_free(t0);
+}
+
+static void gen_rotri_w(TCGv dest, TCGv src1, TCGv src2)
+{
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+
+ tcg_gen_trunc_tl_i32(t1, src1);
+ tcg_gen_trunc_tl_i32(t2, src2);
+ tcg_gen_rotr_i32(t1, t1, t2);
+ tcg_gen_ext_i32_tl(dest, t1);
+
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t2);
+}
+
+static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
+{
+ TCGv dest = gpr_dst(ctx, a->rd);
+ TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);
+
+ tcg_gen_sextract_tl(dest, src1, a->ui5, 32 - a->ui5);
+ return true;
+}
+
+TRANS(sll_w, gen_r3, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
+TRANS(srl_w, gen_r3, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
+TRANS(sra_w, gen_r3, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sra_w)
+TRANS(sll_d, gen_r3, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
+TRANS(srl_d, gen_r3, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
+TRANS(sra_d, gen_r3, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
+TRANS(rotr_w, gen_r3, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
+TRANS(rotr_d, gen_r3, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
+TRANS(slli_w, gen_r2_ui5, tcg_gen_shl_tl)
+TRANS(slli_d, gen_r2_ui6, tcg_gen_shl_tl)
+TRANS(srli_w, gen_r2_ui5, tcg_gen_shr_tl)
+TRANS(srli_d, gen_r2_ui6, tcg_gen_shr_tl)
+TRANS(srai_d, gen_r2_ui6, tcg_gen_sar_tl)
+TRANS(rotri_w, gen_r2_ui5, gen_rotri_w)
+TRANS(rotri_d, gen_r2_ui6, tcg_gen_rotr_tl)
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode
index 1e0b755..9302576 100644
--- a/target/loongarch/insns.decode
+++ b/target/loongarch/insns.decode
@@ -17,6 +17,8 @@
%ui12 10:12
%si16 10:s16
%si20 5:s20
+%ui5 10:5
+%ui6 10:6
#
# Argument sets
@@ -27,6 +29,8 @@
&fmt_rdrjsi16 rd rj si16
&fmt_rdrjui12 rd rj ui12
&fmt_rdsi20 rd si20
+&fmt_rdrjui5 rd rj ui5
+&fmt_rdrjui6 rd rj ui6
#
# Formats
@@ -37,6 +41,8 @@
@fmt_rdrjrksa2 .... ........ ... .. ..... ..... ..... &fmt_rdrjrksa2 %rd %rj %rk %sa2
@fmt_rdrjsi16 .... .. ................ ..... ..... &fmt_rdrjsi16 %rd %rj %si16
@fmt_rdsi20 .... ... .................... ..... &fmt_rdsi20 %rd %si20
+@fmt_rdrjui5 .... ........ ..... ..... ..... ..... &fmt_rdrjui5 %rd %rj %ui5
+@fmt_rdrjui6 .... ........ .... ...... ..... ..... &fmt_rdrjui6 %rd %rj %ui6
#
# Fixed point arithmetic operation instruction
@@ -87,3 +93,23 @@ addu16i_d 0001 00 ................ ..... ..... @fmt_rdrjsi16
andi 0000 001101 ............ ..... ..... @fmt_rdrjui12
ori 0000 001110 ............ ..... ..... @fmt_rdrjui12
xori 0000 001111 ............ ..... ..... @fmt_rdrjui12
+
+#
+# Fixed point shift operation instruction
+#
+sll_w 0000 00000001 01110 ..... ..... ..... @fmt_rdrjrk
+srl_w 0000 00000001 01111 ..... ..... ..... @fmt_rdrjrk
+sra_w 0000 00000001 10000 ..... ..... ..... @fmt_rdrjrk
+sll_d 0000 00000001 10001 ..... ..... ..... @fmt_rdrjrk
+srl_d 0000 00000001 10010 ..... ..... ..... @fmt_rdrjrk
+sra_d 0000 00000001 10011 ..... ..... ..... @fmt_rdrjrk
+rotr_w 0000 00000001 10110 ..... ..... ..... @fmt_rdrjrk
+rotr_d 0000 00000001 10111 ..... ..... ..... @fmt_rdrjrk
+slli_w 0000 00000100 00001 ..... ..... ..... @fmt_rdrjui5
+slli_d 0000 00000100 0001 ...... ..... ..... @fmt_rdrjui6
+srli_w 0000 00000100 01001 ..... ..... ..... @fmt_rdrjui5
+srli_d 0000 00000100 0101 ...... ..... ..... @fmt_rdrjui6
+srai_w 0000 00000100 10001 ..... ..... ..... @fmt_rdrjui5
+srai_d 0000 00000100 1001 ...... ..... ..... @fmt_rdrjui6
+rotri_w 0000 00000100 11001 ..... ..... ..... @fmt_rdrjui5
+rotri_d 0000 00000100 1101 ...... ..... ..... @fmt_rdrjui6
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index e34ab39..8d3b96c 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -162,6 +162,7 @@ static bool gen_r3(DisasContext *ctx, arg_fmt_rdrjrk *a,
}
#include "insn_trans/trans_arith.c"
+#include "insn_trans/trans_shift.c"
static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
{
--
1.8.3.1
next prev parent reply other threads:[~2021-09-02 12:47 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-02 12:40 [PATCH v4 00/21] Add LoongArch linux-user emulation support Song Gao
2021-09-02 12:40 ` [PATCH v4 01/21] target/loongarch: Add README Song Gao
2021-09-02 12:40 ` [PATCH v4 02/21] target/loongarch: Add core definition Song Gao
2021-09-04 9:44 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 03/21] target/loongarch: Add main translation routines Song Gao
2021-09-04 9:45 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 04/21] target/loongarch: Add fixed point arithmetic instruction translation Song Gao
2021-09-04 11:04 ` Richard Henderson
2021-09-07 12:36 ` Song Gao
2021-09-02 12:40 ` Song Gao [this message]
2021-09-04 11:17 ` [PATCH v4 05/21] target/loongarch: Add fixed point shift " Richard Henderson
2021-09-02 12:40 ` [PATCH v4 06/21] target/loongarch: Add fixed point bit " Song Gao
2021-09-04 12:57 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 07/21] target/loongarch: Add fixed point load/store " Song Gao
2021-09-04 13:03 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 08/21] target/loongarch: Add fixed point atomic " Song Gao
2021-09-04 13:14 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 09/21] target/loongarch: Add fixed point extra " Song Gao
2021-09-05 8:39 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 10/21] target/loongarch: Add floating point arithmetic " Song Gao
2021-09-05 9:08 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 11/21] target/loongarch: Add floating point comparison " Song Gao
2021-09-05 9:24 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 12/21] target/loongarch: Add floating point conversion " Song Gao
2021-09-05 9:29 ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 13/21] target/loongarch: Add floating point move " Song Gao
2021-09-05 9:38 ` Richard Henderson
2021-09-05 9:45 ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 14/21] target/loongarch: Add floating point load/store " Song Gao
2021-09-05 9:46 ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 15/21] target/loongarch: Add branch " Song Gao
2021-09-05 9:49 ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 16/21] target/loongarch: Add disassembler Song Gao
2021-09-02 12:41 ` [PATCH v4 17/21] LoongArch Linux User Emulation Song Gao
2021-09-05 10:04 ` Richard Henderson
2021-09-08 9:50 ` Song Gao
2021-09-10 12:52 ` Richard Henderson
2021-09-11 5:58 ` Song Gao
2021-09-12 12:38 ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 18/21] default-configs: Add loongarch linux-user support Song Gao
2021-09-02 12:41 ` [PATCH v4 19/21] target/loongarch: Add target build suport Song Gao
2021-09-05 10:05 ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 20/21] target/loongarch: 'make check-tcg' support Song Gao
2021-09-05 10:06 ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 21/21] scripts: add loongarch64 binfmt config Song Gao
2021-09-05 10:08 ` Richard Henderson
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