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From: Song Gao <gaosong@loongson.cn>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, yangxiaojuan@loongson.cn,
	david@redhat.com, bin.meng@windriver.com,
	mark.cave-ayland@ilande.co.uk, aleksandar.rikalo@syrmia.com,
	jcmvbkbc@gmail.com, tsimpson@quicinc.com,
	alistair.francis@wdc.com, edgar.iglesias@gmail.com,
	chenhuacai@gmail.com, philmd@redhat.com, atar4qemu@gmail.com,
	thuth@redhat.com, ehabkost@redhat.com,
	richard.henderson@linaro.org, groug@kaod.org,
	maobibo@loongson.cn, mrolnik@gmail.com, shorne@gmail.com,
	alex.bennee@linaro.org, david@gibson.dropbear.id.au,
	kbastian@mail.uni-paderborn.de, crwulff@gmail.com,
	laurent@vivier.eu, palmer@dabbelt.com, pbonzini@redhat.com,
	aurelien@aurel32.net
Subject: [PATCH v4 03/21] target/loongarch: Add main translation routines
Date: Thu,  2 Sep 2021 20:40:49 +0800	[thread overview]
Message-ID: <1630586467-22463-4-git-send-email-gaosong@loongson.cn> (raw)
In-Reply-To: <1630586467-22463-1-git-send-email-gaosong@loongson.cn>

This patch add main translation routines and
basic functions for translation.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Signed-off-by: XiaoJuan Yang <yangxiaojuan@loongson.cn>
---
 target/loongarch/helper.h    |   9 +++
 target/loongarch/op_helper.c |  22 ++++++
 target/loongarch/translate.c | 165 +++++++++++++++++++++++++++++++++++++++++++
 target/loongarch/translate.h |  27 +++++++
 4 files changed, 223 insertions(+)
 create mode 100644 target/loongarch/helper.h
 create mode 100644 target/loongarch/op_helper.c
 create mode 100644 target/loongarch/translate.c
 create mode 100644 target/loongarch/translate.h

diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h
new file mode 100644
index 0000000..09bfcfd
--- /dev/null
+++ b/target/loongarch/helper.h
@@ -0,0 +1,9 @@
+/*
+ * QEMU LoongArch CPU
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+DEF_HELPER_2(raise_exception, noreturn, env, i32)
diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c
new file mode 100644
index 0000000..4d10b03
--- /dev/null
+++ b/target/loongarch/op_helper.c
@@ -0,0 +1,22 @@
+/*
+ * LoongArch emulation helpers for qemu.
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "cpu.h"
+#include "qemu/host-utils.h"
+#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
+#include "internals.h"
+
+/* Exceptions helpers */
+void helper_raise_exception(CPULoongArchState *env, uint32_t exception)
+{
+    do_raise_exception(env, exception, GETPC());
+}
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
new file mode 100644
index 0000000..4769004
--- /dev/null
+++ b/target/loongarch/translate.c
@@ -0,0 +1,165 @@
+/*
+ * LoongArch emulation for QEMU - main translation routines.
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "tcg/tcg-op.h"
+#include "exec/translator.h"
+#include "exec/helper-proto.h"
+#include "exec/helper-gen.h"
+
+#include "exec/translator.h"
+#include "exec/log.h"
+#include "qemu/qemu-print.h"
+#include "translate.h"
+#include "internals.h"
+
+/* global register indices */
+TCGv cpu_gpr[32], cpu_pc;
+static TCGv cpu_lladdr, cpu_llval;
+TCGv_i32 cpu_fcsr0;
+TCGv_i64 cpu_fpr[32];
+
+#define DISAS_STOP       DISAS_TARGET_0
+
+void generate_exception(DisasContext *ctx, int excp)
+{
+    tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+    gen_helper_raise_exception(cpu_env, tcg_constant_i32(excp));
+    ctx->base.is_jmp = DISAS_NORETURN;
+}
+
+static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
+{
+    return true;
+}
+
+static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+{
+    if (translator_use_goto_tb(&ctx->base, dest)) {
+        tcg_gen_goto_tb(n);
+        tcg_gen_movi_tl(cpu_pc, dest);
+        tcg_gen_exit_tb(ctx->base.tb, n);
+    } else {
+        tcg_gen_movi_tl(cpu_pc, dest);
+        tcg_gen_lookup_and_goto_ptr();
+    }
+}
+
+static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
+                                            CPUState *cs)
+{
+    DisasContext *ctx = container_of(dcbase, DisasContext, base);
+    int64_t bound;
+
+    ctx->page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
+    ctx->mem_idx = MMU_USER_IDX ;
+
+    /* Bound the number of insns to execute to those left on the page.  */
+    bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4;
+    ctx->base.max_insns = MIN(ctx->base.max_insns, bound);
+}
+
+static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
+{
+}
+
+static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
+{
+    DisasContext *ctx = container_of(dcbase, DisasContext, base);
+
+    tcg_gen_insn_start(ctx->base.pc_next);
+}
+
+static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
+{
+    CPULoongArchState *env = cs->env_ptr;
+    DisasContext *ctx = container_of(dcbase, DisasContext, base);
+
+    ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
+
+    if (!decode(ctx, ctx->opcode)) {
+        qemu_log_mask(LOG_UNIMP, "Error: unkown opcode. 0x%lx: 0x%x\n",
+                      ctx->base.pc_next, ctx->opcode);
+        generate_exception(ctx, EXCP_INE);
+    }
+
+    ctx->base.pc_next += 4;
+}
+
+static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
+{
+    DisasContext *ctx = container_of(dcbase, DisasContext, base);
+
+    switch (ctx->base.is_jmp) {
+    case DISAS_STOP:
+        tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
+        tcg_gen_lookup_and_goto_ptr();
+        break;
+    case DISAS_TOO_MANY:
+        gen_goto_tb(ctx, 0, ctx->base.pc_next);
+        break;
+    case DISAS_NORETURN:
+        break;
+    default:
+        g_assert_not_reached();
+    }
+}
+
+static void loongarch_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs)
+{
+    qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
+    log_target_disas(cs, dcbase->pc_first, dcbase->tb->size);
+}
+
+static const TranslatorOps loongarch_tr_ops = {
+    .init_disas_context = loongarch_tr_init_disas_context,
+    .tb_start           = loongarch_tr_tb_start,
+    .insn_start         = loongarch_tr_insn_start,
+    .translate_insn     = loongarch_tr_translate_insn,
+    .tb_stop            = loongarch_tr_tb_stop,
+    .disas_log          = loongarch_tr_disas_log,
+};
+
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
+{
+    DisasContext ctx;
+
+    translator_loop(&loongarch_tr_ops, &ctx.base, cs, tb, max_insns);
+}
+
+void loongarch_translate_init(void)
+{
+    int i;
+
+    cpu_gpr[0] = NULL;
+    for (i = 1; i < 32; i++) {
+        cpu_gpr[i] = tcg_global_mem_new(cpu_env,
+                                        offsetof(CPULoongArchState, gpr[i]),
+                                        regnames[i]);
+    }
+
+    for (i = 0; i < 32; i++) {
+        int off = offsetof(CPULoongArchState, fpr[i]);
+        cpu_fpr[i] = tcg_global_mem_new_i64(cpu_env, off, fregnames[i]);
+    }
+
+    cpu_pc = tcg_global_mem_new(cpu_env, offsetof(CPULoongArchState, pc), "pc");
+    cpu_fcsr0 = tcg_global_mem_new_i32(cpu_env,
+                    offsetof(CPULoongArchState, fcsr0), "fcsr0");
+    cpu_lladdr = tcg_global_mem_new(cpu_env,
+                    offsetof(CPULoongArchState, lladdr), "lladdr");
+    cpu_llval = tcg_global_mem_new(cpu_env,
+                    offsetof(CPULoongArchState, llval), "llval");
+}
+
+void restore_state_to_opc(CPULoongArchState *env, TranslationBlock *tb,
+                          target_ulong *data)
+{
+    env->pc = data[0];
+}
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
new file mode 100644
index 0000000..dff7d79
--- /dev/null
+++ b/target/loongarch/translate.h
@@ -0,0 +1,27 @@
+/*
+ * LoongArch translation routines.
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ *
+ * SPDX-License-Identifier: LGPL-2.1+
+ */
+
+#ifndef TARGET_LOONGARCH_TRANSLATE_H
+#define TARGET_LOONGARCH_TRANSLATE_H
+
+#include "exec/translator.h"
+
+typedef struct DisasContext {
+    DisasContextBase base;
+    target_ulong page_start;
+    uint32_t opcode;
+    int mem_idx;
+} DisasContext;
+
+void generate_exception(DisasContext *ctx, int excp);
+
+extern TCGv cpu_gpr[32], cpu_pc;
+extern TCGv_i32 cpu_fscr0;
+extern TCGv_i64 cpu_fpr[32];
+
+#endif
-- 
1.8.3.1



  parent reply	other threads:[~2021-09-02 12:47 UTC|newest]

Thread overview: 46+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-02 12:40 [PATCH v4 00/21] Add LoongArch linux-user emulation support Song Gao
2021-09-02 12:40 ` [PATCH v4 01/21] target/loongarch: Add README Song Gao
2021-09-02 12:40 ` [PATCH v4 02/21] target/loongarch: Add core definition Song Gao
2021-09-04  9:44   ` Richard Henderson
2021-09-02 12:40 ` Song Gao [this message]
2021-09-04  9:45   ` [PATCH v4 03/21] target/loongarch: Add main translation routines Richard Henderson
2021-09-02 12:40 ` [PATCH v4 04/21] target/loongarch: Add fixed point arithmetic instruction translation Song Gao
2021-09-04 11:04   ` Richard Henderson
2021-09-07 12:36     ` Song Gao
2021-09-02 12:40 ` [PATCH v4 05/21] target/loongarch: Add fixed point shift " Song Gao
2021-09-04 11:17   ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 06/21] target/loongarch: Add fixed point bit " Song Gao
2021-09-04 12:57   ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 07/21] target/loongarch: Add fixed point load/store " Song Gao
2021-09-04 13:03   ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 08/21] target/loongarch: Add fixed point atomic " Song Gao
2021-09-04 13:14   ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 09/21] target/loongarch: Add fixed point extra " Song Gao
2021-09-05  8:39   ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 10/21] target/loongarch: Add floating point arithmetic " Song Gao
2021-09-05  9:08   ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 11/21] target/loongarch: Add floating point comparison " Song Gao
2021-09-05  9:24   ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 12/21] target/loongarch: Add floating point conversion " Song Gao
2021-09-05  9:29   ` Richard Henderson
2021-09-02 12:40 ` [PATCH v4 13/21] target/loongarch: Add floating point move " Song Gao
2021-09-05  9:38   ` Richard Henderson
2021-09-05  9:45   ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 14/21] target/loongarch: Add floating point load/store " Song Gao
2021-09-05  9:46   ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 15/21] target/loongarch: Add branch " Song Gao
2021-09-05  9:49   ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 16/21] target/loongarch: Add disassembler Song Gao
2021-09-02 12:41 ` [PATCH v4 17/21] LoongArch Linux User Emulation Song Gao
2021-09-05 10:04   ` Richard Henderson
2021-09-08  9:50     ` Song Gao
2021-09-10 12:52       ` Richard Henderson
2021-09-11  5:58         ` Song Gao
2021-09-12 12:38           ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 18/21] default-configs: Add loongarch linux-user support Song Gao
2021-09-02 12:41 ` [PATCH v4 19/21] target/loongarch: Add target build suport Song Gao
2021-09-05 10:05   ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 20/21] target/loongarch: 'make check-tcg' support Song Gao
2021-09-05 10:06   ` Richard Henderson
2021-09-02 12:41 ` [PATCH v4 21/21] scripts: add loongarch64 binfmt config Song Gao
2021-09-05 10:08   ` Richard Henderson

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