Re: [PATCH v4 07/21] target/loongarch: Add fixed point load/store instruction translation

[Richard Henderson <richard.henderson@linaro.org>]

On 9/2/21 2:40 PM, Song Gao wrote:
> +static bool gen_load(DisasContext *ctx, arg_fmt_rdrjsi12 *a,
> +                     DisasExtend dst_ext, MemOp mop)
> +{
> +    ctx->dst_ext = dst_ext;
> +    TCGv dest = gpr_dst(ctx, a->rd);
> +    TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
> +    TCGv temp = NULL;
> +
> +    if (a->si12) {
> +        temp = tcg_temp_new();
> +        tcg_gen_addi_tl(temp, addr, a->si12);
> +        addr = temp;
> +    }
> +
> +    tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
> +
> +    if (ctx->dst_ext) {
> +        gen_set_gpr(ctx, a->rd, dest);
> +    }

You shouldn't ever need dst_ext for loads, since mop can control the extension.

> +static bool gen_loadx(DisasContext *ctx, arg_fmt_rdrjrk *a,
> +                      DisasExtend dst_ext, MemOp mop)

Likewise.

> +static bool gen_load_le(DisasContext *ctx, arg_fmt_rdrjrk *a,
> +                        DisasExtend dst_ext, MemOp mop)

Etc.

> +TRANS(ld_b, gen_load, EXT_SIGN, MO_SB)
> +TRANS(ld_h, gen_load, EXT_SIGN, MO_TESW)
> +TRANS(ld_w, gen_load, EXT_SIGN, MO_TESL)
...
> +TRANS(ld_bu, gen_load, EXT_ZERO, MO_UB)
> +TRANS(ld_hu, gen_load, EXT_ZERO, MO_TEUW)
> +TRANS(ld_wu, gen_load, EXT_ZERO, MO_TEUL)

Note that dst_ext is already matching the sign of mop.


r~