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* [PATCH 0/4] target/arm: fix some simd writes vs sve
@ 2020-02-14 19:46 Richard Henderson
  2020-02-14 19:46 ` [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT Richard Henderson
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Richard Henderson @ 2020-02-14 19:46 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, qemu-arm

The launchpad bug only mentions EXT, but I found three more
via inspection.  I really should extend RISU so that we can
do AdvSIMD testing with SVE enabled...


r~


Richard Henderson (4):
  target/arm: Flush high bits of sve register after AdvSIMD EXT
  target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
  target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
  target/arm: Flush high bits of sve register after AdvSIMD INS

 target/arm/translate-a64.c | 9 +++++++++
 1 file changed, 9 insertions(+)

-- 
2.20.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT
  2020-02-14 19:46 [PATCH 0/4] target/arm: fix some simd writes vs sve Richard Henderson
@ 2020-02-14 19:46 ` Richard Henderson
  2020-02-14 19:46 ` [PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Richard Henderson
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2020-02-14 19:46 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, qemu-arm

Writes to AdvSIMD registers flush the bits above 128.

Buglink: https://bugs.launchpad.net/bugs/1863247
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 7c26c3bfeb..620a429067 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6895,6 +6895,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resl);
     write_vec_element(s, tcg_resh, rd, 1, MO_64);
     tcg_temp_free_i64(tcg_resh);
+    clear_vec_high(s, true, rd);
 }
 
 /* TBL/TBX
-- 
2.20.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX
  2020-02-14 19:46 [PATCH 0/4] target/arm: fix some simd writes vs sve Richard Henderson
  2020-02-14 19:46 ` [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT Richard Henderson
@ 2020-02-14 19:46 ` Richard Henderson
  2020-02-14 19:46 ` [PATCH 3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Richard Henderson
  2020-02-14 19:46 ` [PATCH 4/4] target/arm: Flush high bits of sve register after AdvSIMD INS Richard Henderson
  3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2020-02-14 19:46 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, qemu-arm

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 620a429067..096a854aed 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -6964,6 +6964,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resl);
     write_vec_element(s, tcg_resh, rd, 1, MO_64);
     tcg_temp_free_i64(tcg_resh);
+    clear_vec_high(s, true, rd);
 }
 
 /* ZIP/UZP/TRN
-- 
2.20.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
  2020-02-14 19:46 [PATCH 0/4] target/arm: fix some simd writes vs sve Richard Henderson
  2020-02-14 19:46 ` [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT Richard Henderson
  2020-02-14 19:46 ` [PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Richard Henderson
@ 2020-02-14 19:46 ` Richard Henderson
  2020-02-14 19:46 ` [PATCH 4/4] target/arm: Flush high bits of sve register after AdvSIMD INS Richard Henderson
  3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2020-02-14 19:46 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, qemu-arm

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 096a854aed..b83d09dbcd 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7054,6 +7054,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_resl);
     write_vec_element(s, tcg_resh, rd, 1, MO_64);
     tcg_temp_free_i64(tcg_resh);
+    clear_vec_high(s, true, rd);
 }
 
 /*
-- 
2.20.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 4/4] target/arm: Flush high bits of sve register after AdvSIMD INS
  2020-02-14 19:46 [PATCH 0/4] target/arm: fix some simd writes vs sve Richard Henderson
                   ` (2 preceding siblings ...)
  2020-02-14 19:46 ` [PATCH 3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Richard Henderson
@ 2020-02-14 19:46 ` Richard Henderson
  3 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2020-02-14 19:46 UTC (permalink / raw)
  To: qemu-devel; +Cc: peter.maydell, qemu-arm

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-a64.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b83d09dbcd..bd68588a71 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7412,6 +7412,9 @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
     write_vec_element(s, tmp, rd, dst_index, size);
 
     tcg_temp_free_i64(tmp);
+
+    /* INS is considered a 128-bit write for SVE. */
+    clear_vec_high(s, true, rd);
 }
 
 
@@ -7441,6 +7444,9 @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
 
     idx = extract32(imm5, 1 + size, 4 - size);
     write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
+
+    /* INS is considered a 128-bit write for SVE. */
+    clear_vec_high(s, true, rd);
 }
 
 /*
-- 
2.20.1



^ permalink raw reply	[flat|nested] 5+ messages in thread

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Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2020-02-14 19:46 [PATCH 0/4] target/arm: fix some simd writes vs sve Richard Henderson
2020-02-14 19:46 ` [PATCH 1/4] target/arm: Flush high bits of sve register after AdvSIMD EXT Richard Henderson
2020-02-14 19:46 ` [PATCH 2/4] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Richard Henderson
2020-02-14 19:46 ` [PATCH 3/4] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Richard Henderson
2020-02-14 19:46 ` [PATCH 4/4] target/arm: Flush high bits of sve register after AdvSIMD INS Richard Henderson

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