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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com
Subject: [PATCH v6 12/15] target/riscv: Use gen_unary_per_ol for RVB
Date: Tue, 19 Oct 2021 20:17:06 -0700	[thread overview]
Message-ID: <20211020031709.359469-13-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org>

The count zeros instructions require a separate implementation
for RV32 when TARGET_LONG_BITS == 64.

Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/translate.c                | 16 ++++++++++++
 target/riscv/insn_trans/trans_rvb.c.inc | 33 ++++++++++++-------------
 2 files changed, 32 insertions(+), 17 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 8f5f39d143..7286791c0f 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -511,6 +511,22 @@ static bool gen_unary(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
     return true;
 }
 
+static bool gen_unary_per_ol(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+                             void (*f_tl)(TCGv, TCGv),
+                             void (*f_32)(TCGv, TCGv))
+{
+    int olen = get_olen(ctx);
+
+    if (olen != TARGET_LONG_BITS) {
+        if (olen == 32) {
+            f_tl = f_32;
+        } else {
+            g_assert_not_reached();
+        }
+    }
+    return gen_unary(ctx, a, ext, f_tl);
+}
+
 static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
 {
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index d6f9e9fc83..4eb41756fa 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -47,10 +47,18 @@ static void gen_clz(TCGv ret, TCGv arg1)
     tcg_gen_clzi_tl(ret, arg1, TARGET_LONG_BITS);
 }
 
+static void gen_clzw(TCGv ret, TCGv arg1)
+{
+    TCGv t = tcg_temp_new();
+    tcg_gen_shli_tl(t, arg1, 32);
+    tcg_gen_clzi_tl(ret, t, 32);
+    tcg_temp_free(t);
+}
+
 static bool trans_clz(DisasContext *ctx, arg_clz *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_ZERO, gen_clz);
+    return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw);
 }
 
 static void gen_ctz(TCGv ret, TCGv arg1)
@@ -58,10 +66,15 @@ static void gen_ctz(TCGv ret, TCGv arg1)
     tcg_gen_ctzi_tl(ret, arg1, TARGET_LONG_BITS);
 }
 
+static void gen_ctzw(TCGv ret, TCGv arg1)
+{
+    tcg_gen_ctzi_tl(ret, arg1, 32);
+}
+
 static bool trans_ctz(DisasContext *ctx, arg_ctz *a)
 {
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_ZERO, gen_ctz);
+    return gen_unary_per_ol(ctx, a, EXT_ZERO, gen_ctz, gen_ctzw);
 }
 
 static bool trans_cpop(DisasContext *ctx, arg_cpop *a)
@@ -317,14 +330,6 @@ static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
     return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
 }
 
-static void gen_clzw(TCGv ret, TCGv arg1)
-{
-    TCGv t = tcg_temp_new();
-    tcg_gen_shli_tl(t, arg1, 32);
-    tcg_gen_clzi_tl(ret, t, 32);
-    tcg_temp_free(t);
-}
-
 static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
 {
     REQUIRE_64BIT(ctx);
@@ -332,17 +337,11 @@ static bool trans_clzw(DisasContext *ctx, arg_clzw *a)
     return gen_unary(ctx, a, EXT_NONE, gen_clzw);
 }
 
-static void gen_ctzw(TCGv ret, TCGv arg1)
-{
-    tcg_gen_ori_tl(ret, arg1, (target_ulong)MAKE_64BIT_MASK(32, 32));
-    tcg_gen_ctzi_tl(ret, ret, 64);
-}
-
 static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a)
 {
     REQUIRE_64BIT(ctx);
     REQUIRE_ZBB(ctx);
-    return gen_unary(ctx, a, EXT_NONE, gen_ctzw);
+    return gen_unary(ctx, a, EXT_ZERO, gen_ctzw);
 }
 
 static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
-- 
2.25.1



  parent reply	other threads:[~2021-10-20  3:32 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-20  3:16 [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-20  3:16 ` [PATCH v6 01/15] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-20  3:16 ` [PATCH v6 02/15] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-20  3:16 ` [PATCH v6 03/15] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-20  3:16 ` [PATCH v6 04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-20  3:16 ` [PATCH v6 05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-20  3:17 ` [PATCH v6 06/15] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-20  3:17 ` [PATCH v6 07/15] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-20  3:17 ` [PATCH v6 08/15] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-20  3:17 ` [PATCH v6 09/15] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-20  3:17 ` [PATCH v6 10/15] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-20  3:17 ` [PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-20  3:17 ` Richard Henderson [this message]
2021-10-20  3:17 ` [PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-20  3:17 ` [PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-20  3:17 ` [PATCH v6 15/15] target/riscv: Compute mstatus.sd on demand Richard Henderson
2021-10-20 11:02 ` [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Alistair Francis
2021-10-22  8:26 ` LIU Zhiwei
2021-10-22 15:50   ` Richard Henderson
2021-10-25  9:24     ` LIU Zhiwei
2021-10-25 14:58       ` Richard Henderson

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