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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org
Subject: Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
Date: Mon, 25 Oct 2021 17:24:11 +0800	[thread overview]
Message-ID: <606880b5-83fc-6ab6-6d34-fb2b71536f99@c-sky.com> (raw)
In-Reply-To: <663d5df5-c107-c4ce-99e0-2a5d336a69ca@linaro.org>


On 2021/10/22 下午11:50, Richard Henderson wrote:
> On 10/22/21 1:26 AM, LIU Zhiwei wrote:
>> As the specification said, "PC bits above XLEN are ignored, and when
>> the PC is written, it is sign-extended to fill the widest supported 
>> XLEN."
>> We still need special process of PC for exceptions or jump instructions.
>>
>> I have two methods to implement  PC register access,
>> but not sure which is the right way.
>>
>> First, normally process the PC register as the specification points.
>> That means expanding  the PC when setting the global TCGv variable
>> cpu_pc, and truncating the pc_first and  pc_next fields in
>> DisasContextBase before decoding instructions.    I am not sure
>> whether the sign-extended pc is compatible with QEMU common code.
>
> I think extending on write is the correct thing. 

Thanks. I will pick this way.

> Jumps, exception entry and return, gdb write.

If we carefully process jumps and gdb write, I think we can omit 
exception entry and return. Is it right?

>
> Note that the read from PC for translation is in cpu_get_tb_cpu_state, 
> before translation.  You should not need to change anything wrt 
> pc_first/pc_next/etc, because it will already have been done.

Good! Thanks.

Best Regards,
Zhiwei

>
>> Second,  ignore ignore the PC special process for jump instructions.
>> Just expand or truncate the PC register when exception processing,
>> gdb read, or cpu dump registers. It is not a stright way,  but I 
>> think it is still right.
>
> I think you could make it work that way, but I don't know that it's 
> less difficult, or that you'd have fewer changes.
>
>
> r~


  reply	other threads:[~2021-10-25  9:26 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-20  3:16 [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-20  3:16 ` [PATCH v6 01/15] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-20  3:16 ` [PATCH v6 02/15] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-20  3:16 ` [PATCH v6 03/15] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-20  3:16 ` [PATCH v6 04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-20  3:16 ` [PATCH v6 05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-20  3:17 ` [PATCH v6 06/15] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-20  3:17 ` [PATCH v6 07/15] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-20  3:17 ` [PATCH v6 08/15] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-20  3:17 ` [PATCH v6 09/15] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-20  3:17 ` [PATCH v6 10/15] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-20  3:17 ` [PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-20  3:17 ` [PATCH v6 12/15] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-20  3:17 ` [PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-20  3:17 ` [PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-20  3:17 ` [PATCH v6 15/15] target/riscv: Compute mstatus.sd on demand Richard Henderson
2021-10-20 11:02 ` [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Alistair Francis
2021-10-22  8:26 ` LIU Zhiwei
2021-10-22 15:50   ` Richard Henderson
2021-10-25  9:24     ` LIU Zhiwei [this message]
2021-10-25 14:58       ` Richard Henderson

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