From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com
Subject: [PATCH v6 02/15] target/riscv: Create RISCVMXL enumeration
Date: Tue, 19 Oct 2021 20:16:56 -0700 [thread overview]
Message-ID: <20211020031709.359469-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org>
Move the MXL_RV* defines to enumerators.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu_bits.h | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 999187a9ee..e248c6bf6d 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -364,9 +364,11 @@
#define MISA32_MXL 0xC0000000
#define MISA64_MXL 0xC000000000000000ULL
-#define MXL_RV32 1
-#define MXL_RV64 2
-#define MXL_RV128 3
+typedef enum {
+ MXL_RV32 = 1,
+ MXL_RV64 = 2,
+ MXL_RV128 = 3,
+} RISCVMXL;
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
--
2.25.1
next prev parent reply other threads:[~2021-10-20 3:28 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 3:16 [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-20 3:16 ` [PATCH v6 01/15] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-20 3:16 ` Richard Henderson [this message]
2021-10-20 3:16 ` [PATCH v6 03/15] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-20 3:16 ` [PATCH v6 04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-20 3:16 ` [PATCH v6 05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-20 3:17 ` [PATCH v6 06/15] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-20 3:17 ` [PATCH v6 07/15] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-20 3:17 ` [PATCH v6 08/15] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-20 3:17 ` [PATCH v6 09/15] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-20 3:17 ` [PATCH v6 10/15] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-20 3:17 ` [PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-20 3:17 ` [PATCH v6 12/15] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-20 3:17 ` [PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-20 3:17 ` [PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-20 3:17 ` [PATCH v6 15/15] target/riscv: Compute mstatus.sd on demand Richard Henderson
2021-10-20 11:02 ` [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Alistair Francis
2021-10-22 8:26 ` LIU Zhiwei
2021-10-22 15:50 ` Richard Henderson
2021-10-25 9:24 ` LIU Zhiwei
2021-10-25 14:58 ` Richard Henderson
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