From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@c-sky.com>, qemu-devel@nongnu.org
Cc: alistair.francis@wdc.com, qemu-riscv@nongnu.org
Subject: Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
Date: Mon, 25 Oct 2021 07:58:30 -0700 [thread overview]
Message-ID: <4de33722-7cb9-7566-6830-a45709eda452@linaro.org> (raw)
In-Reply-To: <606880b5-83fc-6ab6-6d34-fb2b71536f99@c-sky.com>
On 10/25/21 2:24 AM, LIU Zhiwei wrote:
>> I think extending on write is the correct thing.
>
> Thanks. I will pick this way.
>
>> Jumps, exception entry and return, gdb write.
>
> If we carefully process jumps and gdb write, I think we can omit exception entry and
> return. Is it right?
No, though you'd probably have to create a special test case to see it.
On exception return, a 64-bit OS can write a 64-bit value into SEPC. But when SEPC is
copied to PC during SRET, UXL should be examined and the assignment should extend for a
32-bit user program.
Exception entry would seem to be limited on its face by SXLEN; STVEC will always contain
the same number of bits as PC, so no (additional) extension would be required. But we do
have to be careful to interpret the target_ulong value properly for the current SXLEN.
r~
prev parent reply other threads:[~2021-10-25 14:59 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 3:16 [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-20 3:16 ` [PATCH v6 01/15] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-20 3:16 ` [PATCH v6 02/15] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-20 3:16 ` [PATCH v6 03/15] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-20 3:16 ` [PATCH v6 04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-20 3:16 ` [PATCH v6 05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-20 3:17 ` [PATCH v6 06/15] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-20 3:17 ` [PATCH v6 07/15] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-20 3:17 ` [PATCH v6 08/15] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-20 3:17 ` [PATCH v6 09/15] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-20 3:17 ` [PATCH v6 10/15] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-20 3:17 ` [PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-20 3:17 ` [PATCH v6 12/15] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-20 3:17 ` [PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-20 3:17 ` [PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-20 3:17 ` [PATCH v6 15/15] target/riscv: Compute mstatus.sd on demand Richard Henderson
2021-10-20 11:02 ` [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Alistair Francis
2021-10-22 8:26 ` LIU Zhiwei
2021-10-22 15:50 ` Richard Henderson
2021-10-25 9:24 ` LIU Zhiwei
2021-10-25 14:58 ` Richard Henderson [this message]
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