From: Alistair Francis <alistair23@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
Alistair Francis <alistair.francis@wdc.com>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
liuzhiwei <zhiwei_liu@c-sky.com>
Subject: Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length
Date: Wed, 20 Oct 2021 21:02:58 +1000 [thread overview]
Message-ID: <CAKmqyKN8TxxtaCg06q7jLvmO_22jNfaOZuWKFxMbpO4tnXfE0Q@mail.gmail.com> (raw)
In-Reply-To: <20211020031709.359469-1-richard.henderson@linaro.org>
On Wed, Oct 20, 2021 at 1:26 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> This is a partial patch set attempting to set things in the
> right direction for both the UXL and RV128 patch sets.
>
>
> r~
>
>
> Changes for v6:
> * Rebase on riscv-to-apply.next.
>
> Changes for v5:
> * Fix cpu_dump, which asserted for -accel qtest.
> Instead of filtering CSRs explicitly in cpu_dump,
> let the riscv_csr_operations predicate do the job.
> This means we won't dump S-mode registers when RVS
> is not enabled, much like we currently filter on RVH.
>
> Changes for v4:
> * Use riscv_csrrw_debug for cpu_dump.
> This fixes the issue that Alistair pointed out wrt the
> MSTATUS.SD bit not being correct in the dump; note that
> gdbstub already uses riscv_csrrw_debug, and so did not
> have a problem.
> * Align the registers in cpu_dump.
>
> Changes for v3:
> * Fix CONFIG_ typo.
> * Fix ctzw typo.
> * Mark get_xlen unused (clang werror)
> * Compute MSTATUS_SD on demand.
>
> Changes for v2:
> * Set mxl/sxl/uxl at reset.
> * Set sxl/uxl in write_mstatus.
>
>
> Richard Henderson (15):
> target/riscv: Move cpu_get_tb_cpu_state out of line
> target/riscv: Create RISCVMXL enumeration
> target/riscv: Split misa.mxl and misa.ext
> target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
> target/riscv: Add MXL/SXL/UXL to TB_FLAGS
> target/riscv: Use REQUIRE_64BIT in amo_check64
> target/riscv: Properly check SEW in amo_op
> target/riscv: Replace is_32bit with get_xl/get_xlen
> target/riscv: Replace DisasContext.w with DisasContext.ol
> target/riscv: Use gen_arith_per_ol for RVM
> target/riscv: Adjust trans_rev8_32 for riscv64
> target/riscv: Use gen_unary_per_ol for RVB
> target/riscv: Use gen_shift*_per_ol for RVB, RVI
> target/riscv: Use riscv_csrrw_debug for cpu_dump
> target/riscv: Compute mstatus.sd on demand
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.h | 73 +++------
> target/riscv/cpu_bits.h | 8 +-
> hw/riscv/boot.c | 2 +-
> linux-user/elfload.c | 2 +-
> linux-user/riscv/cpu_loop.c | 2 +-
> semihosting/arm-compat-semi.c | 2 +-
> target/riscv/cpu.c | 195 +++++++++++++-----------
> target/riscv/cpu_helper.c | 92 ++++++++++-
> target/riscv/csr.c | 104 ++++++++-----
> target/riscv/gdbstub.c | 10 +-
> target/riscv/machine.c | 10 +-
> target/riscv/monitor.c | 4 +-
> target/riscv/translate.c | 174 +++++++++++++++------
> target/riscv/insn_trans/trans_rvb.c.inc | 140 +++++++++--------
> target/riscv/insn_trans/trans_rvi.c.inc | 44 +++---
> target/riscv/insn_trans/trans_rvm.c.inc | 36 ++++-
> target/riscv/insn_trans/trans_rvv.c.inc | 29 ++--
> 17 files changed, 576 insertions(+), 351 deletions(-)
>
> --
> 2.25.1
>
>
next prev parent reply other threads:[~2021-10-20 11:18 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-20 3:16 [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length Richard Henderson
2021-10-20 3:16 ` [PATCH v6 01/15] target/riscv: Move cpu_get_tb_cpu_state out of line Richard Henderson
2021-10-20 3:16 ` [PATCH v6 02/15] target/riscv: Create RISCVMXL enumeration Richard Henderson
2021-10-20 3:16 ` [PATCH v6 03/15] target/riscv: Split misa.mxl and misa.ext Richard Henderson
2021-10-20 3:16 ` [PATCH v6 04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl Richard Henderson
2021-10-20 3:16 ` [PATCH v6 05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS Richard Henderson
2021-10-20 3:17 ` [PATCH v6 06/15] target/riscv: Use REQUIRE_64BIT in amo_check64 Richard Henderson
2021-10-20 3:17 ` [PATCH v6 07/15] target/riscv: Properly check SEW in amo_op Richard Henderson
2021-10-20 3:17 ` [PATCH v6 08/15] target/riscv: Replace is_32bit with get_xl/get_xlen Richard Henderson
2021-10-20 3:17 ` [PATCH v6 09/15] target/riscv: Replace DisasContext.w with DisasContext.ol Richard Henderson
2021-10-20 3:17 ` [PATCH v6 10/15] target/riscv: Use gen_arith_per_ol for RVM Richard Henderson
2021-10-20 3:17 ` [PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64 Richard Henderson
2021-10-20 3:17 ` [PATCH v6 12/15] target/riscv: Use gen_unary_per_ol for RVB Richard Henderson
2021-10-20 3:17 ` [PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI Richard Henderson
2021-10-20 3:17 ` [PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump Richard Henderson
2021-10-20 3:17 ` [PATCH v6 15/15] target/riscv: Compute mstatus.sd on demand Richard Henderson
2021-10-20 11:02 ` Alistair Francis [this message]
2021-10-22 8:26 ` [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length LIU Zhiwei
2021-10-22 15:50 ` Richard Henderson
2021-10-25 9:24 ` LIU Zhiwei
2021-10-25 14:58 ` Richard Henderson
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