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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 09/12] hw/riscv: opentitan: Fixup resetvec
Date: Fri, 23 Sep 2022 14:07:01 +1000	[thread overview]
Message-ID: <20220923040704.428285-10-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220923040704.428285-1-alistair.francis@opensource.wdc.com>

From: Alistair Francis <alistair.francis@wdc.com>

The resetvec for the OpenTitan machine ended up being set to an out of
date value, so let's fix that and bump it to the correct start address
(after the boot ROM)

Fixes: bf8803c64d75 "hw/riscv: opentitan: bump opentitan version"
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220914101108.82571-3-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/riscv/opentitan.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index af13dbe3b1..45c92c9bbc 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -142,7 +142,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490,
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000400,
                             &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 
-- 
2.37.3



  parent reply	other threads:[~2022-09-23  4:24 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-23  4:06 [PULL 00/12] riscv-to-apply queue Alistair Francis
2022-09-23  4:06 ` [PULL 01/12] hw/ssi: ibex_spi: fixup typos in ibex_spi_host Alistair Francis
2022-09-23  4:06 ` [PULL 02/12] hw/ssi: ibex_spi: update reg addr Alistair Francis
2022-09-23  4:06 ` [PULL 03/12] docs/system: clean up code escape for riscv virt platform Alistair Francis
2022-09-23  4:06 ` [PULL 04/12] target/riscv: Remove sideleg and sedeleg Alistair Francis
2022-09-23  4:06 ` [PULL 05/12] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h} Alistair Francis
2022-09-23  4:06 ` [PULL 06/12] target/riscv: remove fflags, frm, and fcsr from riscv-*-fpu.xml Alistair Francis
2022-09-23  4:06 ` [PULL 07/12] target/riscv: remove fixed numbering from GDB xml feature files Alistair Francis
2022-09-23  4:07 ` [PULL 08/12] target/riscv: Set the CPU resetvec directly Alistair Francis
2022-09-23  4:07 ` Alistair Francis [this message]
2022-09-23  4:07 ` [PULL 10/12] hw/riscv: opentitan: Expose the resetvec as a SoC property Alistair Francis
2022-09-23  4:07 ` [PULL 11/12] target/riscv: Check the correct exception cause in vector GDB stub Alistair Francis
2022-09-23  4:07 ` [PULL 12/12] hw/riscv/sifive_e: Fix inheritance of SiFiveEState Alistair Francis
2022-09-26 19:28 ` [PULL 00/12] riscv-to-apply queue Stefan Hajnoczi
2022-09-26 20:59   ` Alistair Francis
2022-09-26 21:04     ` Stefan Hajnoczi

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